DE19501226A1 - Field programmable gate array element for the implementation of register files and associative memories - Google Patents

Abstract

A programmable logic cell for implementing RAMs, content-addressable-memories, and multiported register files in programmable gate arrays combines the functions of a memory (102) and a comparator (104) in a small number of gates. The programmable logic circuit includes a multiplexing circuit (103) that permits one of the inputs to the comparator (104) to be switched between the data stored in the memory cell (100) and an external data signal. The programmable logic circuits can be connected together in a two-dimensional array together with decoders to implement a small RAM, content-addressable-memory or a multiported register file. <IMAGE>

Description

The present invention relates to integrated Circuits and in particular on an improved Archi architecture for programmable logic arrays.

Programmable logic is for the purposes of this discussion as a digital circuit structure of a fixed connection defined by a user can become arbitrary topo to other digital systems emulate logic quickly. It can be used to both fast logic simulators and configurable to generate bare computer machines that are able to Su per computer for certain tasks for a fraction of the Exceed costs. Programmable logic systems that are capable of large digital circuits (with hundreds of thousands of gates) are expensive, with typi costs of the order of two to four dollars per emulated gate, and require a large number of inte ized circuits that have a variety of complex Circuit boards are distributed.

A class of programmable logic is based on the technology of field-programmable gate arrays (FPGA technology FPGA = Field Programmable Gate Array). This approach uses a number of FPGAs that are interconnected in a fixed topology. Each FPGA includes two types of equipment: ( 1 ) a number of programmable logic cells (PLCs) that can be programmed or configured to perform a specific logic function (such as "AND" or "EXCLUSIVE OR"); and (2) signal routing means that can be programmed to connect the logic cells to each other and to external input / output pins. The programmed FPGA thus forms a usable logic circuit that represents a subset of the entire logic system that is to be simulated. The total amount of FPGAs taken together then functionally simulates the desired logical system. Since the FPGAs in these architectures have fixed physical connections to one another that cannot be changed, the simulation of a logical system requires a mapping of the circuit for the logical system of interest to the interconnected FPGAs such that the logical functions and connections of the original circuit can be represented exactly by programming the FPGAs. A fast simulation is possible because the logic cells in the FPGAs perform their calculations in parallel, where they transmit their results to one another via the signal routing network.

The flexibility of FPGA systems makes it possible to be quick Prototype new logical designs without the hassle of Building the design from discrete components or Creating the design in a custom integrier circuit. However, this flexibility not achieved without additional effort. Because an FPGA is meant to is, a wide variety of logical designs that are not Archi. must be known from the start FPGA architecture a signal routing and logic function lity that is unlikely in all applications is to be used. In addition, universal FPGA-Be often poor adaptation to certain means Circuit types. Therefore, the efficiency of one tends FPGA resource usage for a given application compared to the one with a bespoke integrated circuit implementation can be achieved  to be minor. This loss of efficiency becomes common mitigated by the flexibility of the device. Each but there are some digital circuits that are one of the kind of show poor efficiency if you rely on a conventional FPGA that represent the implementation of the same in an FPGA or a system of FPGAs is ugly.

In particular are multi-port register files and association tive memory (CAMs; CAM Content-Addressable Memories) two Circuit types with poor efficiency Map commercially available FPGAs. Still, these are Circuit types important components in many logical Systems. If implemented with pure Boolean logic are associative memories and multi-port registers files with large numbers of gates. E.g. requires an 80 bit wide register file of 96 registers with 4 write inputs and 8 read inputs more than 250,000 gates with two inputs gene or other functions. The cost of such FPGAs are intolerable. Therefore, multi-port registers remain parts and associative memory outside the circuit blocker toirs of most FPGA systems.

It is the object of the present invention to provide a verb to create a FPGA system in which register files and Associative memory can be implemented more efficiently.

This task is accomplished through a programmable gate array according to claims 1 and 4 and a programmable Logical circuit according to claim 7 solved.

The present invention is a programmable logic Cell for implementing RAMs (Random Access Memories = Random access memory), associative memory and multi-port Register files in programmable gate arrays. The pro programmable logic circuit combines the functions a memory cell and a comparator in a small one Number of gates. The programmable logic circuit  includes a multiplexer circuit that enables one of the inputs of the comparator between the data that are stored in the memory cell, and an external Switch data signal. The programmable logic Circuits can be combined with decoders in two dimensional array to be connected to one another small RAM, an associative memory or a multi-port Implement register file.

Preferred embodiments of the present invention are described below with reference to the accompanying Drawings explained in more detail. Show it:

Fig. 1 is a block diagram of a multiport register file;

Fig. 2 is a block diagram of an implementation of a write input for use with a multiport register file;

Fig. 3 is a block diagram of an implementation of a reading beginning sterdatei for use with a multiport regi;

Fig. 4 is a block diagram of an implementation of a regi sterdatenbits for use with a multiport register file;

Fig. 5 is a block diagram of an associative memory;

Fig. 6 is a block diagram of an FPGA;

Fig. 7 is a block diagram of a logic memory cell according to the present invention;

Fig. 8 is a schematic diagram of the preferred embodiment of an exporting approximately logical memory cell according to the present invention;

Figure 9 is a block diagram of a RAM cherzellen of logical SpeI builds up in accordance with the present invention.

FIG. 10 is a schematic diagram of a memory cell for storing a register bits according to the present invention;

FIG. 11 is a block diagram of a register file that cherzellen from SpeI and Registerbitzellen the vorlie constricting invention is constructed in accordance with;

Fig. 12 is a block diagram of an associative memory, which the present invention is built up from memory cells according to.

The present invention can be better understood in relation to the logical structure and the conventional implementation of multi-port register files and associative memories. Fig. 1 is a block diagram of a multiport register file 10.. A multi-port register file corresponds to an array of registers that can be written to by multiple write inputs and read by multiple read inputs simultaneously. Exemplary registers are at 13 - shown 15th Exemplary reading inputs and write inputs are at 16 - shown 12-17 and 11 respectively. Each write input requires three inputs, an address specifying the register to be written, the data to be written to the register, and a trigger signal which must be activated to actually perform the write. Each read input requires only an address that specifies the register to be read.

The registers can be taken as a group as a two-dim sional array of one-bit memory cells can be considered. To simplify the following discussion, registers used with a width of one bit. For professionals however, it is obvious that registers of any  Latitude using the teachings of the present Er can be built up.

Figure 2 is a block diagram of a possible implementation of a write input. The write input 20 is constructed from two demultiplexers 21 and 22 , which supply a pair of signals to each of N single-bit registers in the register file. The demultiplexer 21 decodes the address and the trigger signal and generates the FILE_WRITE signal and couples it to the register specified by ADDRESS. The demultiplexer 22 generates a FILE_DATEN signal that has the same value as DATA and feeds this signal to the register specified by ADDRESS when the TRIGGER signal is activated. Each write input is only able to write to a single register in the file. When a plurality of write inputs exist, the FILE_WRITE and FILE_DATA signals generated by the different write inputs for each register are ORed together to provide a single pair of signals for each register. It will be apparent to those skilled in the art that a particular mechanism must be provided to ensure that the same address is not offered to more than one write input at a time.

In contrast to a write input, a read input is much easier to implement. A read input can be implemented from a single N: 1 multiplexer 31 , as shown in FIG. 3. A multitude of read inputs simply share the outputs of the register file bits and do not require any combining operations analogous to the OR operation described above.

The current register bit can be stored in a flip-flop 33 , as shown at 33 in FIG. 4. The FILE_DATEN signal is clocked into the flip-flop at the next clock cycle after the FILE_WRITE signal is activated.

Now that the logical structure of a register file has been clarified, the logical structure of an associative memory explained in more detail. For the purposes of this discussion A CAM can be viewed as a memory that the user-specific read and write operation of a RAM supports, but additionally a parallel search operation that supports a target bit pattern of a fixed Width with a "tag field" (label field) of the same Width compares that belongs to every word of memory.

Figure 5 is a block diagram of a typical CAM architecture. The CAM 40 is divided into a number of data sets 42 . Each data record comprises a tag field 43 and a data field 44 . Each data record also has a comparator 45 belonging to the same. A target pattern is coupled to a bus 46 which is connected to the comparators. Each comparator 45 compares the target pattern with the content of the tag field 43 of its associated data set. If the content of the tag field matches the target pattern, the comparator generates a match signal which causes a signaling means (router) 47 belonging to the data set to couple the data field 44 of this data set to a bus 48 . Furthermore, a match signal indicating a successful match or lack thereof is coupled to bus 48 . The present invention relates to the implementation of the tag field and the comparison functions of a CAM in an FPGA.

Fig. 6 is a block diagram of a typical FPGA 50th The FPGA 50 comprises two major classes of components, programmable logic cells (PLCs) 52 that implement certain combination logic and memory functions, and configurable signal routing means that form a signaling network 54 that is used to control the inputs and outputs of the PLCs to connect with each other and with external I / O pins (I / O = input-output). The PLCs are of primary interest for the present invention.

A typical PLC is a functional cell that has several Records inputs and generates one or more outputs. Each output can include a flip-flop.

The present invention solves the problems encountered with known FPGA architectures by creating a novel PLC that can be configured to efficiently implement multi-port register files and CAMs as well as conventional RAMs. This cell is referred to as CRR memory cell (CRR = C AM / R AM / R egfile = associative memory / random access memory / register file) in the discussion below.

A CRR cell consists of a combination of an association tiv memory with a random access memory and a register file.

A block diagram illustrating the basic features of a CRR memory cell 100 in accordance with the present invention is shown in FIG. 7. The CRR memory cell 100 can be viewed as a one-bit memory cell 102 , a multiplexer 103 and a comparator 104 . The multiplexer 103 determines whether the data stored in the memory cell 102 or an external signal 106 is compared by the comparator 104 with the DATA input signal.

A schematic of the preferred embodiment of a CRR memory cell 200 is shown in FIG. 8. The memory cell is formed by cross-coupled inverters 202 and 203 and transistors 205 and 206 , which are normally in the conductive state. The memory cell can be written to in two ways. In the first method, the data to be written is driven onto the WRITE_DATA line. When the WRITE_RELEASE and WORD signals are asserted, gate 201 turns transistor 204 on and transistor 205 off, allowing the value of the WRITE_DATA signal to overwrite the previous value in the memory cell.

In the second method, the complement of the data to be written is driven on line 224 , thereby overwriting the stored value when a transistor 206 is turned off and a transistor 207 is turned on by activating the REGFILE signal. It should be noted that the WRITE or REG FILE signals must be interrupted and held at a low logic level to complete the write cycle and enable the data in the memory cell to be read.

The memory cell is read by bringing the WORD line high logic. This causes the stored value to be driven through the tri-state buffer 207 onto the READ_DATA line.

The comparison function is implemented via an exclusive OR gate 208 . Gate 208 compares the data on the WRITE_DATA line to the content of the memory cell or the complement of the data on line 224 depending on the state of transistors 206 and 207 . A transistor 209 enables the comparison result to pull the line down when either a transistor 211 or a transistor 212 is conductive. The manner in which gate 210 operates will be apparent from the discussion of the WRITE_INPUT signal when implementing the register files, as discussed below with reference to FIG. 11. Transistors 206 and 207 perform the multiplexer function described above.

The CRR memory cells can be combined with a decoder and control logic to produce a simple RAM 300 as shown in FIG. 9. The RAM 300 is an eight word by one bit RAM made up of eight CRR memory cells 301 and a decoder 302 that decodes a three bit address. When used in this manner, the REG FILE, WRITE_ INPUT and SEARCH lines are kept at a low logic level and the and lines are not used. The address lines in RAM are decoded by decoder 302 to drive the word line of the corresponding CRR memory cell to a high logic level, thereby controlling the value of the selected CRR memory cell on a READ_DATA bus 304 . When the WRITE_RELEASE signal on line 305 is logic high (HIGH) after the decoded address and the WRITE_DATA signals are stable, the data on WRITE_DATA line 306 is written to the CRR memory cell.

A CRR memory cell selected by the WORD line in accordance with the present invention may be combined with the one-bit memory cell shown in FIG. 10 and certain decoder circuits to implement a multi-port register file, such as is shown in Fig. 11. Referring first to Fig. 10, there is shown a schematic diagram of a circuit for storing a single bit of a register in a register file. This circuit is referred to as an RBIT in the following discussion. An RBIT cell stores a bit and it generates a signal that indicates the stored value. The content of the cell is complemented if the stored data is not in a fixed relationship with a second signal. In the preferred embodiment of the present invention, an RBIT 350 is constructed from a D flip-flop 351 and an exclusive OR gate 352 , as shown in FIG. 10. In this embodiment, the content of flip-flop 351 is complemented at the next clock pulse if it does not match.

Fig. 11 is a block diagram of a multi-port register file 400 according to the present invention. The multi-port register file 400 is shown with one bit wide registers to simplify the drawing. The multi-port register file 400 is constructed from a plurality of simple RAM memories, described above, by adding an RBIT cell to each RAM and by connecting the - and - lines that implement the RAM function have not been used. Exemplary RAM memory are shown at 402-404. Each RAM includes a decoder 407 and a plurality of CRR memory cells 401 . In the example shown in FIG. 11, there are eight CRR memory cells per RAM. However, it will be apparent to those skilled in the art that other configurations can be used.

The data stored in the register bits is stored in the corresponding RBIT cells. The signals and each RBIT cell belong to different - and lines in each of the RAMs, as shown in FIG . The DATA lines of each row of CRR memory cells are also connected to the corresponding line. The manner in which the data is written to the RBIT cells is explained in more detail below.

In this application, the CRR memory cells are used for Im use the read and write inputs not for storing data bits. The signal REGFILE in the CRR memory cell is at a high logic level controlled (HIGH) and the SEARCH signal goes to a low controlled logic level. Each RAM either serves as a Le se input or as write input for the register file. A RAM in which the WRITE_INPUT signal goes high driven logic level is a write input, wuh rend a RAM, in which the signal WRITE_INPUT to a low logic level, is a read input.

The complement of the register data bit stored in each RBIT cell is sent over the lines to each of the read and write inputs. For example, each RBIT cell 405 sends its content over a (0) line, the RBIT cell 408 sends its content over a DATA (1) line, etc.

A read input operates in a manner analogous to the operation of a RAM, with the exception that the data placed on the READ_DATA line is taken from the corresponding line instead of the internal memory cell. It is e.g. For example, assume that RAM 402 is connected as a read input. If address 0 is the input to decoder 407 , CRR memory cell 401 is selected. Since REG FILE is activated, transistor 207 , gate 203 , transistor 205 and gate 202 (see FIG. 8) in CRR memory cell 401 connect line (0) through inverting driver 207 , which is provided by the output of the decoder 407 , which is connected to the WORD line of the CRR memory cell 401 , is operated with the READ_DATA line.

A write input works in an analog way. The register file bit to be written is addressed with the same data lines that are used to select a CRR memory cell when operating as a RAM. The WRITE_RELEASE signal is activated and the selected CRR memory cell tries to write the value of WRITE_DATA to the memory cell in the CRR memory cell. However, since the REGFILE signal is also activated, the connection to the memory cell in the CRR memory cell is interrupted. Thus, the values compared by the exclusive-OR gate 208 are the values on the WRITE_DATA line and the value on the line, via transistor 207 and gate 203 , which inverts the value of the line. is coupled. If the value to be written differs from the stored value, it is driven to a low logic level, which complements the RBIT cell data on the next cycle.

Furthermore, by combining a number of RAM memories, a CAM tag field and a search function can be implemented. Fig. 12 is a block diagram of the tag Ab-section of a CAM 500 constructed from a plurality of RAMs, for the RAMs 502 to 504 are typical. The RAMs are constructed from CRR memory cells in an analogous manner as described above with respect to FIG. 11. In this case, however, the memory cells in the CRR memory cell are used to store the information, ie the tag field values. The tag fields of the CAM entries are stored in the horizontal arrays of the CRR memory cells. The example shown in Fig. 12 consists of eight tag fields with N bits per tag field. For this functionality, the lines are routed horizontally in terms of bus and pulled to a high logic level by a weak pull-up. Each line is shared by all CRR memory cells on the same horizontal line. WRITE_INPUT and REG FILE are controlled to a low logic level and are not used.

Reading and writing of the tag fields is accomplished in the same manner described with respect to the RAM 300 shown in FIG. 9. The WRITE_DATA inputs of the CRR memory cells are connected to a line 510 , while the READ_DATA outputs are connected to a line 511 in RAM 502 . Similar connections are made for the other tag bits in each RAM.

A parallel search for a tag field that matches a spe target destination is matched by delivering the target bit pattern and activation of the SEARCH signal initiated. The Target pattern is delivered on the WRITE_DATA lines, one bit per RAM. Any mismatch between the Target bit array and the stored tag field causes the line for this row to one  low logic level is drawn. All tag fields will be searched in parallel, creating a signal for each row  is generated by an additional programmable logic are processed in the FPGA can move the pointer to the desired word in the CAM produce.

The functionalities described above were all based on RAMs which were formed from CRR memory cells and a decoder. In the preferred embodiment of the present invention, each RAM comprises 16 CRR memory cells. This number is based on a study that shows the optimal size for access tables in FPGAs. The RAMs would be interconnected in arrays of 16 RAMs via the and buses. This provides multi-port register files with up to 16 read and write inputs and provides CAM tag fields that are 16 bits wide and 16 bits deep. Wider and deeper register files and CAM tag fields can be created by using additional programmable logic in the FPGA and by routing the lines to the further logic in the case of a CAM.

In principle, each RAM can have a single PLC in the FPGA Represent signal routing network. With the preferred off exemplary embodiment of the present invention is, however Array of 16 RAMs packed as a single PLC. This con figuration has the advantage of reducing the length of the and lines in the typical Case, which for the CAM and register file operations an increased speed is delivered.

Claims (21)

1. Programmable gate array with the following features: a plurality of programmable logic circuits ( 300 , 400 , 500 ), each programmable logic circuit having a plurality of input ports and an output port, each programmable logic circuit having an output signal in response to one or more input signals at the input ports generated at the output terminal; and
a signal routing device ( 54 ) for connecting the input and output connections in one of the programmable logic circuits to a further one of the programmable logic circuits, one of the programmable logic circuits ( 300 , 400 , 500 ) being a CRR cell ( 100 , 200 ) has the following characteristics: means for receiving an external comparison signal ( 106 );
means for receiving an external data signal;
storage means ( 102 ) for storing a bit of information and generating a stored bit signal indicative of the value of the stored bit in response to receiving an external word signal;
comparing means ( 107 ) for comparing the first and second signals and generating a comparison signal indicative of whether the first and second signals are the same, the first signal being generated from an external data signal; and
multiplexer means ( 103 ) responsive to an externally generated comparison selection signal for selecting either the stored bit signal or the external comparison signal as the second signal. 2. Programmable gate array according to claim 1, wherein the programmable logic circuits ( 300 , 400 , 500 ) further have the following features: a second CRR cell ( 301 );
means for receiving an address signal specifying one of the CRR cells; and
decoding means ( 302 ) for generating and coupling the word signal to the specified CRR cell. 3. Programmable gate array according to claim 1 or 2, wherein the programmable logic circuits ( 300 , 400 , 500 ) further have the following features: means ( 351 ) including an RBIT cell ( 350 ) for storing a bit of information and generating a first signal indicative of the stored bit; and
comparing means ( 352 ) for causing the stored bit to change states when the first signal is in a fixed relationship with a second signal coupled to the RBIT cell. 4. Programmable gate array with the following features: a plurality of programmable logic circuits ( 300 ; 400 ; 500 ), each programmable logic circuit having a plurality of input ports and an output port, each programmable logic circuit having an output signal in response to one or more input signals on the input ports the output port generated; and
a signal routing device ( 54 ) for connecting the input and output connections in one of the programmable logic circuits to another of the programmable logic circuits,
wherein at least one of the programmable logic circuits has a CRR memory cell ( 100 ; 200 ). 5. Programmable gate array according to claim 4, wherein the CRR memory cell ( 100 ; 200 ) has the following features: a bit memory cell ( 102 ) for storing a bit of information;
a multiplexer (103) connected (102) operatively connected to the bit SpeI cherzelle, for selecting either the stored bits of information from the bit storage cell (102) or a first external signal as a selected signal; and
a comparator ( 104 ), operatively connected to the multiplexer ( 103 ), for comparing a second external signal with the selected signal. 6. Programmable gate array according to claim 5, wherein at least one of the programmable logic circuits ( 300 ; 400 ; 500 ) further has the following features: an RBIT cell ( 350 ), including means ( 351 ) for storing a bit of information and generating a first signal indicative of the stored bit; and
comparing means ( 352 ) for causing the stored bit to change states when the first signal is in a fixed relationship with a second signal coupled to the RBIT cell ( 350 ). 7. Programmable gate array according to claim 6, wherein at least one of the programmable logic circuits ( 300 ; 400 ; 500 ) further has the following features: a plurality of CRR cells ( 100 ; 200 ); and
a decoder ( 407 ; 507 ) for receiving an address signal specifying one of the CRR cells ( 100 ; 200 ) and for generating and coupling a word signal to the specified CRR cell. 8. Programmable logic circuit with the following note to paint: a plurality of CRR cells ( 401 , 501 ) arranged in two dimensional arrays with columns ( 402-404 ; 502-504 ) and rows, each CRR cell having the following features: means for receiving an external comparison signal;
means for receiving an external data signal;
storage means ( 102 ) for storing a bit of information and generating a stored bit signal indicative of the value of the stored bit in response to receiving an external word signal;
comparing means ( 102 ) for comparing the first and second signals and generating a comparison signal indicative of whether the first and second signals were the same, the first signal being generated from an external data signal; and
multiplexer means ( 103 ) responsive to an externally generated comparison selection signal for selecting either the stored bit signal or the external comparison signal as the second signal,
wherein the CRR cells in each column are connected to a decoder ( 407 , 507 ) to receive a signal specifying one of the CRR cells and to generate the word signal and to couple it to the specified CRR cell , and
wherein the generating means in each comparing means of the CRR cells in each row are connected to each other. 9. Programmable logic circuit according to claim 8, at the means for generating the memory bit connected to each CRR cell in each row they are. 10. Programmable logic circuit according to claim 8 or 9, wherein at least one of the columns ( 402-404 ) has the following features: means ( 351 ) including an RBIT cell ( 350 ) for storing a bit of information and generating a first signal indicative of the stored bit; and
comparing means ( 352 ) for causing the stored bit to change states when the first signal is in a fixed relationship with a second signal coupled to the RBIT cell.