GB9505060D0 - Programmable gate array - Google Patents

Programmable gate array

Info

Publication number
GB9505060D0
GB9505060D0 GBGB9505060.5A GB9505060A GB9505060D0 GB 9505060 D0 GB9505060 D0 GB 9505060D0 GB 9505060 A GB9505060 A GB 9505060A GB 9505060 D0 GB9505060 D0 GB 9505060D0
Authority
GB
United Kingdom
Prior art keywords
programmable gate
gate array
array
programmable
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GBGB9505060.5A
Other versions
GB2287815A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of GB9505060D0 publication Critical patent/GB9505060D0/en
Publication of GB2287815A publication Critical patent/GB2287815A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
GB9505060A 1994-03-25 1995-03-13 Programmable gate array Withdrawn GB2287815A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US21844294A 1994-03-25 1994-03-25

Publications (2)

Publication Number Publication Date
GB9505060D0 true GB9505060D0 (en) 1995-05-03
GB2287815A GB2287815A (en) 1995-09-27

Family

ID=22815143

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9505060A Withdrawn GB2287815A (en) 1994-03-25 1995-03-13 Programmable gate array

Country Status (3)

Country Link
JP (1) JPH07273640A (en)
DE (1) DE19501226A1 (en)
GB (1) GB2287815A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3616518B2 (en) 1999-02-10 2005-02-02 日本電気株式会社 Programmable device
US6407576B1 (en) 1999-03-04 2002-06-18 Altera Corporation Interconnection and input/output resources for programmable logic integrated circuit devices

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5245227A (en) * 1990-11-02 1993-09-14 Atmel Corporation Versatile programmable logic cell for use in configurable logic arrays
US5245226A (en) * 1991-02-25 1993-09-14 Lattice Semiconductor Corporation Output logic macrocell
US5231312A (en) * 1992-03-12 1993-07-27 Atmel Corporation Integrated logic circuit with functionally flexible input/output macrocells
GB9303084D0 (en) * 1993-02-16 1993-03-31 Inmos Ltd Programmable logic circuit

Also Published As

Publication number Publication date
JPH07273640A (en) 1995-10-20
DE19501226A1 (en) 1995-10-05
GB2287815A (en) 1995-09-27

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)