DE2008585A1 - Circuit arrangement for connecting a plurality of data processing units to a peripheral memory device - Google Patents

Description

Patent attorney

7 Stuttgart-Feuerbach
Short Street 8

G.J.LeStrat-M.Bradane 5-2

INTERNATIONAL STANDARD ELECTRIC CORPORATION, NEW YORK

Circuit arrangement for connecting a plurality of data processing units to a peripheral memory device

The invention relates to a circuit arrangement for connecting several data processing units with a peripheral storage device, in particular for recording charges in telephone switching systems. In the exemplary embodiment explained in more detail The data processing units are used to record the charges briefly referred to as a calculator, although its function goes somewhat beyond that of an arithmetic unit.

It has already been proposed to determine telephone charges with a device in the manner of a computer. Each computer can control several long-distance calls at the same time and store the data required for billing in a fast, temporary memory (number of the calling subscriber, number of the called subscriber, rate, start > end and, if applicable, duration of the call). After the end of a call, it is necessary to clear the space occupied by this data in the fast, temporary memory, since this memory has only a limited capacity, and to transfer the data to a storage device comprising a permanent memory of large capacity, e.g. a magnetic tape or a punched tape.

27 ,. January 197o

Vl / Kn. «/ - ■

'009838/1128

- 2 G. j'.LeStrat-M.Bradane 5-2

The relocation process runs relatively slowly *>, but comes also comparatively seldom. It is therefore advisable for reasons of economy to have several computers or data processing units to be re-stored in a peripheral memory. Of course, care must be taken that not During the transfer from one computer, another computer also starts a transfer. In addition, must but also prevent a simultaneous request from two computers leading to a double connection.

It is the task of the circuit arrangement according to the invention to provide this access of several data processing units to a peripheral one Arrange memory. The recording of charges is only an example of all problems of the same kind in transmission of data between temporary storage and permanent storage.

The circuit arrangement according to the invention is characterized by occupancy devices for displaying the free or occupied state the storage device, through occupancy control devices, occupancy blocking devices and program interruption devices, which, combined in groups, are each assigned to a data processing unit, each Group can connect itself to the storage device and any other group can act to create duplicate connections to prevent.

■ A special design of the circuit arrangement according to the invention Is characterized in that the occupancy devices consist of flip-flops, the outputs of which are of one type with the occupancy control devices or interruption devices of the same group and their other outputs are connected to the locking devices of all other groups are that the occupancy locking devices AND circuits whose outputs are connected to the corresponding occupancy control devices connected to the same group and that each

009838/1928 " ^A.

G.J.LeStrat-M.Bradane 5-2

Occupancy control device an occupancy control circuit and a Occupancy acceptance circuit includes whose outputs with each other and on the one hand with the input of the occupancy devices and on the other hand are connected to an acknowledgment input of the data processing unit of the same group.

A further development of the circuit arrangement according to the invention is characterized in that an occupancy control circuit by a first request from the associated data processing unit is switched on when the storage device is free and an occupancy toggle of the same group is switched, wherein said flip-flop is capable. on the one hand, an input of the occupancy acceptance circuit to enable and on the other hand to block the inputs of the control devices of the other groups that the output of each Occupancy control circuit is able to confirm the confirmation device the data processing unit of the same group to actuate, and that each occupancy acceptance circuit is confirmed by a second request from the data processing unit which is initiated by the above-mentioned confirmation device, unless there are further initial requirements according to the same. storage device templates.

0 09838/1928

G.J.LeStrat-M.Bradane 5-2

The invention is explained below using an exemplary embodiment in the form of a connecting device between several Computers and a peripheral memory, in context explained with the drawings.

Plg.l shows in an overview the one assigned to a computer Device group,

2 shows the sub-figures to be viewed side by side 2a and 2b show the connections between three groups of devices shown in detail.

The basic function can be seen in Fig.l. If a computer 1 has to transmit information to the common peripheral machine 9, in the example a memory, then it sends a test pulse to the occupancy control device via line 2 . When the peripheral machine is free, a pulse is transmitted via line 5 to the occupancy tilting stage 4 in order to display the occupied state in device 6 and to prevent any response to a request from another computer. At the same time, a pulse is transmitted from the control device 3 to the computer 1 via the line 7 in order to confirm receipt of its request. In order to ensure that only one request has been registered and that there is no risk of a double connection, the computer 1 sends a request confirmation via the line 6. If the Bele / runpskippstufe 4 of the other computers are in the idle position, the occupancy tilt stage 4 of the requesting computer is in position 1, then a pulse is transmitted to the requesting realist via the line 7 to indicate to him that he can send information to the peripheral machine as it is connected to the latter.

Because the peripheral machine, whatever it is, a lot works slower than the computer, the writing takes place character by character,

0CS838 / 1928

- 5 G.J.LeStrat-M.Bradane 5-2

When the peripheral machine is writing a character has finished / then it gives an impulse on the line ll, the one. Interrupting device 12 in the connected Computer belonging to the group operated. An interrupt signal is then sent to the computer via line 14. However, since the computer can receive interrupt requests of various origins, it must first activate the device identify that the interrupt is requesting. For this If the computer transmits an impulse on line Io and receives a response as an impulse back over line 13.

When the transfer of information is finished, then there the computer sends a pulse to the line 15, which the occupancy tilting stage 4 and makes the peripheral machine accessible to other computers again.

In the example, the peripheral memory has. 9 a line 16 which is common to all computing device groups and through which memory can be locked to all computers.

Pig.2 shows the connecting lines between the first two Device groups and a final device group. The number of computers that can be connected to a memory naturally depends on the traffic load to be handled. In the exemplary embodiment, the fee recording of an exchange is the The number of computers that can be connected to a memory is limited to eight.

It is assumed that there is a request from the computer 1 for a writing process in the peripheral device 9. The computer sends a pulse to its line 2 and an "i" is output at the output of the inverter 17. The gate circuit 18 thus has an "1" at its two inputs 19 and 2o, since all Bfil ^ -. Un ^ fiklpnotufen 4 ( as long as the periphe.ro "machine is free;) oelcij are in a rest position, with ^{an 11} I" appearing at the output 21 of each Klppstufan , the four inputs of the

'"". . 009838/1928 ■ " ^/ "

BATH ORIGINAL

G. J. LeStrat-M.Bradane 5-2

Gate circuit 22 and those of the extension gate circuit 23 If a "1" is therefore supplied, a "θ" appears at the output of the gate circuit 22 and, because of the inverter 24, becomes a "1" is supplied to the input 2o of the gate circuit 18. The gate circuit 18 is therefore conductive, and that via the line 2 transmitted pulse appears again on lines 5 and 25 · The trigger stage 48 is triggered by the pulse on the line 5 switched to their other state so that on theirs Output 28 an "1" and at its output 21 an "O" appears. All gate circuits 22 of the other computers are therefore locked and the input 29 of the gate circuit 30 is a "l" supplied. The pulse on line 25 reaches the computer via inverters 26 and 27 (required for technological reasons) and is used by the latter as confirmation the acceptance of his request sent over the line 2 counted. The receipt of the confirmation of acceptance triggers the Computer to send out a pulse as a request confirmation via line 8. Via the inverter 31 is then the input 32 the gate circuit 30 is supplied with an "1". This gate circuit is now conductive, since it has an "1" at its three inputs (input 33 is in the same state as the input Po of the gate circuit 18). A pulse is therefore sent again to lines 5 and 25 via the gate circuit, D reader impulse has no effect on line 5, while it informs the computer on line 25 (via line 7) about it, that his requirement can be taken into account, since the peripheral machine is not called by any other computer will.

If, on the other hand, two computers have issued a request and have changed, for example, the state of two tilt levels 4 o and V 1, then finds; ο in over the line ei eint ret'i '-ncU; t · Buisbätltfungiilmpul fi dlo'l'oriicihal do? ¹ ; Ίο im nlohtleltetultMi

, since the latter has * Ί.ιΐί "() ^ri at Filtu ^ ani ¹ ; '**> and ο in * " l "at Un Y? and: · Ο., I) Le :; thereby comes i'iuiLaiulü, iLius you

ü 0 9 B Ί B / 1 d 2 B

IAD ORIGINAL

G.J.LeStrat-M.Bradane 5-2

Flip-flop 34 has changed its position after receiving the ^{seizure pulse on line 35, so that it shows a "0 Ti} at the output '36, which appears at the corresponding input of the gate circuit 22. Since this gate circuit is non-conductive, there is a" at its output. i ¹ 'and because of the inverter 24 there is a "θ" at the input 33 of the torso posture 30.

Under the conditions of the previous paragraph, the two computers do not receive the second confirmation via the line 7 or 37 and supply their trigger stage # 8 or J> K via the input lines 15 and 38 with a triggering pulse. The two flip-flops are reset and the two computers are | who renew their request impulses, which now have the opportunity to appear at different times.

As already indicated above, the memory device 9 applies an "1" potential as a program interrupt request to the line 11 after the writing of a character has ended. This potential appears in the example started at the input 42 of the gate circuit 4o. Since the computer 1 is now connected to the peripheral machine 9, there is a "1 ¹ V" at the input 41 of the gate circuit 4o to request I

As soon as the computer has received the program interruption request, it sends a test pulse over the line Io and at the output of the inverter 43 appears on the line 44 a ^; On the other hand, the "θ" at the output of the gate circuit 4o supplies an "l" on the line 46 at the output of the inverter 47. The gate circuit 45 thus has an "l" at both inputs 44, 46 and conducts, with a "θ "appears as an output signal on the line 12, which causes the computer to transmit another character to the memory device 9. ·

009838/1928

G.J.LeStrat-M.Bradane 5-2

If the character is written, then the peripheral machine requests a program interrupt again and the cycle begins again. When all characters have been transmitted to the memory device in this way, the computer then transmits a trigger pulse via line 15, which resets the flip-flop 48 so that the memory device can again be reached by all computers.

For the purpose of maintenance or testing, a line 16 common to all computers allows the storage device to be put out of operation. If this line is supplied with a ¹ O ", then none of the gates 22 in the occupancy devices 6 be more conductive and none of the gates H may be more direct in the assignment control devices 3, thus no request may be a computer, for example via the line Ρ, get through more.

In a special embodiment of the invention, the arithmetic unit includes charge-recording devices in which the content of a memory cell has to be transferred to the peripheral memory device when the memory cell assigned to a connection is full. The memory-programmed computer 1 sends a test pulse on line 2 to the device when it carries out a test command 1OT. Depending on whether the V'irriolitujir 3 is free or not, that is, whether a character arrives on the Ldtuiii- $ 7 or not, dai switches; Program to the next command or skips a command. In the case of a jump, the next command to be carried out consists of a corresponding test command UOT), but of a command recorded at a different point. The computer 1 then sends a new test pulse to the device% An over the line <■>, depending on whether the device 3 answers or not, vdrd again switched to the next command or jumped. Β »im, '''hai ton to the nlinhot en command this causes 7, unaechr; i, dasr; after an njch bel <nniiten procedure a first sign / Ίΐιιι]) oi'i phei-en r. [) eicliei. · transferred.

^ Pn1 --ent ftjjpprüclH, Ί Bl./eielmun^cii., ? characters

009838/1928

Claims (3)

G.J.LeStrat-M.Bradane. 5-2 Claims . I .. Circuit arrangement for connecting several data processing units to a peripheral storage device, characterized by occupancy devices (4) for displaying the free or occupied state of the storage device (9) * by occupancy control devices (3) > occupancy blocking devices (6) and program interruption devices (12), which in groups summarized in each case one? Data processing unit (1) are assigned, each group being able to connect itself to the storage device and to act on every other group in order to prevent double connections. 2. Circuit arrangement according to claim 1, characterized in that the occupancy devices consist of flip-flops (4) whose outputs are of one type ("l" or "θ") with the occupancy control devices (3) or interruption devices (12) of the same group and the other outputs of which are connected to the occupancy blocking devices (6) of all other groups, that the occupancy blocking devices are AND circuits (22,23) whose outputs are connected to the corresponding occupancy control devices (18,30) of the same group, and that each occupancy control device is one Occupancy control circuit (18) and an acceptance circuit (30), the outputs of which are connected to one another and, on the one hand, to the input (5) of the occupancy control circuit and, on the other hand, to a confirmation input (25..7) of the data processing unit (1) of the same group. 3. Circuit arrangement according to claim 2, characterized in that an occupancy control circuit (18) by a first request from the associated data processing unit (1) 009838/1928 G.J \ LeStrat-M.Bradane 5-2 is switched on when the storage device (9) is free and an occupancy toggle stage (48) of the same group is switched over, wherein said flip-flop is able, on the one hand, to have an input (29) of the occupancy acceptance r circuit (j5o) and on the other hand the inputs of the control devices (6) of the other groups to block the output of each occupancy control circuit in the Is able to operate the confirmation device of the data processing unit of the same group, and that each occupancy acceptance circuit (3o) is actuated by a second request (8) from the data processing unit, which is initiated by the above-mentioned confirmation device, unless further initial requirements according to the same storage device. 009838/1928