DE19983746T1 - Speichersteuerung die durch Neuordnen von Speicheranforderungen die Busverwendung erhöht - Google Patents

Speichersteuerung die durch Neuordnen von Speicheranforderungen die Busverwendung erhöht

Info

Publication number
DE19983746T1
DE19983746T1 DE19983746T DE19983746T DE19983746T1 DE 19983746 T1 DE19983746 T1 DE 19983746T1 DE 19983746 T DE19983746 T DE 19983746T DE 19983746 T DE19983746 T DE 19983746T DE 19983746 T1 DE19983746 T1 DE 19983746T1
Authority
DE
Germany
Prior art keywords
memory
reordering
bus usage
increases bus
requests
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19983746T
Other languages
English (en)
Inventor
Henry Stracovsky
Piotr Szabelski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE19983746T1 publication Critical patent/DE19983746T1/de
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE19983746T 1998-11-16 1999-11-15 Speichersteuerung die durch Neuordnen von Speicheranforderungen die Busverwendung erhöht Ceased DE19983746T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10893098P 1998-11-16 1998-11-16
US09/439,857 US6385708B1 (en) 1998-11-16 1999-11-12 Using a timing-look-up-table and page timers to determine the time between two consecutive memory accesses
PCT/US1999/027018 WO2000029959A1 (en) 1998-11-16 1999-11-15 Memory controller which increases bus utilization by reordering memory requests

Publications (1)

Publication Number Publication Date
DE19983746T1 true DE19983746T1 (de) 2001-11-29

Family

ID=26806434

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19983746T Ceased DE19983746T1 (de) 1998-11-16 1999-11-15 Speichersteuerung die durch Neuordnen von Speicheranforderungen die Busverwendung erhöht

Country Status (7)

Country Link
US (1) US6385708B1 (de)
JP (1) JP2003535380A (de)
KR (1) KR100679362B1 (de)
CN (1) CN1199109C (de)
DE (1) DE19983746T1 (de)
GB (1) GB2358943B (de)
WO (1) WO2000029959A1 (de)

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US6941428B2 (en) * 2002-09-25 2005-09-06 International Business Machines Corporation Memory controller optimization
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US20060026371A1 (en) * 2004-07-30 2006-02-02 Chrysos George Z Method and apparatus for implementing memory order models with order vectors
GB2425230B (en) * 2005-04-15 2011-03-23 Filmlight Ltd A method and apparatus for image processing
CN100444142C (zh) * 2007-03-14 2008-12-17 北京中星微电子有限公司 同步动态存储器的访问控制方法及同步动态存储器控制器
US9021482B2 (en) * 2007-05-04 2015-04-28 International Business Machines Corporation Reordering data responses using ordered indicia in a linked list
KR100947745B1 (ko) * 2008-02-26 2010-03-17 한양대학교 산학협력단 메모리로의 접근 요청을 재정렬하는 요청 재정렬 장치 및그 방법
KR100978206B1 (ko) * 2008-02-26 2010-08-25 한양대학교 산학협력단 메모리로의 접근 요청을 재정렬하는 다중 대기큐를포함하는 요청 재정렬 장치 및 그 방법
EP2262140B1 (de) 2008-03-31 2019-11-20 Panasonic Intellectual Property Management Co., Ltd. Empfänger, empfangsverfahren, empfangsprogramm, integrierte schaltung und digitales fernsehen
JP5338008B2 (ja) * 2009-02-13 2013-11-13 ルネサスエレクトロニクス株式会社 データ処理装置
US8199759B2 (en) * 2009-05-29 2012-06-12 Intel Corporation Method and apparatus for enabling ID based streams over PCI express
JP4640870B2 (ja) * 2009-10-22 2011-03-02 富士通株式会社 受信装置
US8615629B2 (en) * 2010-01-18 2013-12-24 Marvell International Ltd. Access scheduler
US9842068B2 (en) 2010-04-14 2017-12-12 Qualcomm Incorporated Methods of bus arbitration for low power memory access
US8539129B2 (en) * 2010-04-14 2013-09-17 Qualcomm Incorporated Bus arbitration techniques to reduce access latency
JP5625737B2 (ja) * 2010-10-22 2014-11-19 富士通株式会社 転送装置、転送方法および転送プログラム
US9632954B2 (en) 2011-11-07 2017-04-25 International Business Machines Corporation Memory queue handling techniques for reducing impact of high-latency memory operations
CN102522065A (zh) * 2011-12-23 2012-06-27 深圳市奥拓电子股份有限公司 一种led显示系统及其通信控制方法
KR101292309B1 (ko) * 2011-12-27 2013-07-31 숭실대학교산학협력단 반도체칩 및 메모리 제어방법, 그리고 그 방법을 컴퓨터에서 실행시키기 위한 프로그램을 기록한 기록매체
US8909874B2 (en) * 2012-02-13 2014-12-09 International Business Machines Corporation Memory reorder queue biasing preceding high latency operations
KR101818967B1 (ko) 2012-06-15 2018-01-16 인텔 코포레이션 명확화 없는 비순차 load store 큐
CN104823154B (zh) 2012-06-15 2017-12-29 英特尔公司 包括虚拟加载存储队列的处理器和系统
KR101993562B1 (ko) 2012-06-15 2019-09-30 인텔 코포레이션 Load store 재정렬 및 최적화를 구현하는 명령어 정의
KR101702788B1 (ko) * 2012-06-15 2017-02-03 소프트 머신즈, 인크. 스토어 상위 서열에 기초하여 상이한 스레드들로부터의 포워딩을 구현하는 스레드에 무관한 로드 스토어 버퍼
WO2013188701A1 (en) 2012-06-15 2013-12-19 Soft Machines, Inc. A method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimization
EP2862062B1 (de) 2012-06-15 2024-03-06 Intel Corporation Speicherwarteschlange für virtuelle last mit dynamischem versandfenster mit verteilter struktur
KR101825585B1 (ko) 2012-06-15 2018-02-05 인텔 코포레이션 명확화 없는 비순차 load store 큐를 갖는 재정렬된 투기적 명령어 시퀀스들
CN102799487A (zh) * 2012-06-29 2012-11-28 记忆科技(深圳)有限公司 基于阵列/lun的io调度方法及装置
KR102205899B1 (ko) * 2014-02-27 2021-01-21 삼성전자주식회사 메모리의 뱅크 충돌을 방지하기 위한 방법 및 장치
US9921754B2 (en) 2015-07-28 2018-03-20 Futurewei Technologies, Inc. Dynamic coding algorithm for intelligent coded memory system
US9760432B2 (en) 2015-07-28 2017-09-12 Futurewei Technologies, Inc. Intelligent code apparatus, method, and computer program for memory
US10180803B2 (en) 2015-07-28 2019-01-15 Futurewei Technologies, Inc. Intelligent memory architecture for increased efficiency
US10437480B2 (en) 2015-12-01 2019-10-08 Futurewei Technologies, Inc. Intelligent coded memory architecture with enhanced access scheduler
CN109426484B (zh) * 2017-08-28 2021-08-31 华为技术有限公司 一种数据排序装置、方法及芯片
US10409739B2 (en) * 2017-10-24 2019-09-10 Micron Technology, Inc. Command selection policy
US11099778B2 (en) * 2018-08-08 2021-08-24 Micron Technology, Inc. Controller command scheduling in a memory system to increase command bus utilization
CN113918216A (zh) 2020-07-10 2022-01-11 富泰华工业（深圳）有限公司 数据读/写处理方法、装置及计算机可读存储介质
TWI758778B (zh) * 2020-07-10 2022-03-21 鴻海精密工業股份有限公司 資料讀/寫處理方法、裝置及電腦可讀存儲介質
WO2022246036A1 (en) * 2021-05-20 2022-11-24 Micron Technology, Inc. Adjustable timer component for semiconductor devices
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US5990913A (en) 1997-07-30 1999-11-23 Intel Corporation Method and apparatus for implementing a flush command for an accelerated graphics port device
US5974571A (en) 1997-09-30 1999-10-26 Intel Corporation Method and apparatus for avoiding deadlock in the issuance of commands that are reordered and require data movement according to an original command order

Also Published As

Publication number Publication date
GB0111922D0 (en) 2001-07-04
KR20010092745A (ko) 2001-10-26
US6385708B1 (en) 2002-05-07
CN1383511A (zh) 2002-12-04
CN1199109C (zh) 2005-04-27
GB2358943A (en) 2001-08-08
KR100679362B1 (ko) 2007-02-05
GB2358943B (en) 2003-07-23
JP2003535380A (ja) 2003-11-25
WO2000029959A1 (en) 2000-05-25

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
R016 Response to examination communication
R002 Refusal decision in examination/registration proceedings
R016 Response to examination communication
R006 Appeal filed
R008 Case pending at federal patent court
R003 Refusal decision now final
R011 All appeals rejected, refused or otherwise settled