DE19948901A1 - Semiconductor component controllable by field effect - Google Patents
Semiconductor component controllable by field effectInfo
- Publication number
- DE19948901A1 DE19948901A1 DE1999148901 DE19948901A DE19948901A1 DE 19948901 A1 DE19948901 A1 DE 19948901A1 DE 1999148901 DE1999148901 DE 1999148901 DE 19948901 A DE19948901 A DE 19948901A DE 19948901 A1 DE19948901 A1 DE 19948901A1
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- semiconductor component
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- conductivity type
- semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 230000005669 field effect Effects 0.000 title description 2
- 238000002347 injection Methods 0.000 claims abstract description 19
- 239000007924 injection Substances 0.000 claims abstract description 19
- 108091006146 Channels Proteins 0.000 description 19
- 239000002800 charge carrier Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005352 clarification Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Die vorliegende Erfindung betrifft ein Halbleiterbauelement
das folgende Merkmale aufweist:
The present invention relates to a semiconductor component which has the following features:
- - einen Halbleiterkörper mit einer Leitungszone eines ersten Leitungstyps, einer Anschlußzone des ersten Leitungstyps, ei ner zwischen der Anschlußzone und der Leitungszone (4) ange ordneten Kanalzone eines zweiten Leitungstyps und mit einer Vielzahl von beabstandet zueinander in der Leitungszone ange ordneten Bereichen des zweiten Leitungstyps,a semiconductor body with a line zone of a first line type, a connection zone of the first line type, egg ner between the connection zone and the line zone ( 4 ) arranged channel zone of a second line type and with a plurality of spaced apart areas in the line zone of the second line type,
- - eine isoliert gegenüber der Kanalzone angeordnete Steuere lektrode.- An isolated control from the channel zone electrode.
Derartige Halbleiterbauelemente sind aus der DE 198 15 907 C1 bekannt. Die darin beschriebenen nleitenden Vertikal-MOSFET und Lateral-MOSFET weisen einen Halbleiterkörper mit einer n- leitenden Leitungszone als Drain-Zone auf, in der eine Viel zahl p-leitender Gebiete angeordnet sind. In den Halbleiter körper sind weiterhin p-leitende Kanalzonen eingebracht, in denen n-leitende Anschlußzonen als Source-Zonen eingebracht sind. Zur Ansteuerung des MOSFET ist eine Steuerelektrode vorgesehen, die isoliert gegen die Kanalzone auf dem Halblei terkörper angebracht ist. Derartige Halbleiterbauelemente be sitzen in leitendem Zustand eine gute Leitfähigkeit, d. h. ei nen geringen Einschaltwiderstand Ron bedingt durch die n-lei tende Leitungszone. In gesperrtem Zustand besitzen sie eine hohe Spannungsfestigkeit, weil sich mit zunehmender Drain- Source-Spannung bzw. mit zunehmender sich in der Leitungszone ausbildender Raumladungszone die vorzugsweise hochdotierten p-leitenden Gebiete und die diese umgebenden n-dotierten Be reiche der Leitungszone sich gegenseitig ausräumen, wodurch eine Verarmung an Ladungsträgern in der Leitungszone statt findet. Such semiconductor components are known from DE 198 15 907 C1. The conductive vertical MOSFET and lateral MOSFET described therein have a semiconductor body with an n-conductive line zone as a drain zone, in which a large number of p-conductive regions are arranged. In the semiconductor body p-type channel zones are also introduced, in which n-type connection zones are introduced as source zones. To control the MOSFET, a control electrode is provided, which is mounted insulated against the channel zone on the semiconductor body. Such semiconductor components have a good conductivity in the conductive state, ie a low on-resistance R on due to the n-conductive line zone. In the blocked state, they have a high dielectric strength, because with increasing drain-source voltage or with increasing space charge zone forming in the line zone, the preferably highly doped p-type regions and the n-doped regions of the line zone surrounding them mutually clear each other, causing depletion of charge carriers in the line zone.
Um zu verhindern, daß die ausgeräumten Zonen um die p-lei tenden Gebiete erhalten bleiben bzw. daß die p-leitenden Ge biete aufgeladen bleiben, wenn die Drain-Source-Spannung ab nimmt und der MOSFET wieder leiten soll, ist bei dem bekann ten Halbleiterbauelement ein "schwacher Injektor" vorgesehen, der beispielsweise als Schottky-Kontakt oder als p-leitende Schicht zwischen die Leitungsschicht und einen Drain-Anschluß des MOSFET oder als p-leitende Wanne(n) in dem/den Be reich(en) der Kontaktzone(n) ausgebildet ist. Durch den In jektor werden im leitenden Zustand des MOSFET Löcher oder p- Ladungsträger in die Leitungszone injiziert, die die p-lei tenden Gebiete entladen und so eine gute Leitfähigkeit der Leitungszone wiederherstellen.To prevent the cleared zones around the p-lei tend areas are preserved or that the p-type Ge offer to remain charged when the drain-source voltage decreases takes and the MOSFET should conduct again, is known to the a "weak injector" is provided in the semiconductor component, for example as a Schottky contact or as a p-type Layer between the line layer and a drain connection of the MOSFET or as a p-type well (s) in the / the Be rich (s) of the contact zone (s) is formed. By the In ejectors are holes or p- in the conductive state of the MOSFET Charge carriers are injected into the conduction zone that the p-lei unloading areas and thus good conductivity of the Restore line zone.
Nachteilig wirkt sich dabei aus, daß insbesondere das Vorse hen des schwachen Injektors zwischen der Leitungszone und dem Drain-Anschluß einen zusätzlichen Widerstand bzw. einen zu sätzlichen Spannungsabfall hervorruft.The disadvantage here is that in particular the front weak injector between the line zone and the Drain connection an additional resistance or one too causes additional voltage drop.
Der vorliegenden Erfindung liegt die Aufgabe zugrunde, ein durch Feldeffekt steuerbares Halbleiterbauelement zur Verfü gung zu stellen, das in gesperrtem Zustand eine hohe Span nungsfestigkeit und in leitendem Zustand eine gute Leitfähig keit aufweist und das insbesondere die oben genannten Nach teile nicht aufweist.The present invention is based on the object Semiconductor component controllable by field effect to provide a high span when locked tensile strength and good conductivity in a conductive state speed and in particular the above mentioned parts does not have.
Diese Aufgabe wird durch ein Halbleiterbauelement gelöst, das neben den eingangs genannten Merkmalen ein in den Halbleiter körper eingebrachtes Injektionsgebiet des zweiten Lei tungstyps aufweist, das an eine Ladungsquelle angeschlossen ist.This object is achieved by a semiconductor component which in addition to the features mentioned in the introduction injection area of the second lei tion type connected to a charge source is.
Wenn das Halbleiterbauelement leiten soll, liefert die La dungsquelle Ladungsträger des zweiten Leitungstyps in die Leitungszone, um die nach dem Sperren des Halbleiterbauele ments aufgeladenen Gebiete des zweiten Leitungstyps zu entla den und so eine gute Leitfähigkeit zu gewährleisten. If the semiconductor device is to conduct, the La Charge source of the second conductivity type in the Conduction zone to the after locking the semiconductor device discharged areas of the second conduction type to ensure good conductivity.
Das Injektionsgebiet des ersten zweiten Leitungstyps ist vor zugsweise hochdotiert und in ein hochdotiertes Gebiet des er sten Leitungstyps eingebettet. Das Injektionsgebiet des zwei ten Leitungstyps und das umgebende des ersten Leitungstyps Gebiet wirken als Injektor nach Art einer Zenerdiode.The injection area of the first second line type is in front preferably highly endowed and in a highly endowed area of the he most embedded line type. The injection area of the two th line type and the surrounding line of the first line type Area act as an injector in the manner of a Zener diode.
Die Ladungsquelle ist vorzugsweise eine zwischen das Injekti onsgebiet und ein Bezugspotential geschaltete Kapazität. Die Kapazität wird bei sperrendem Halbleiterbauelement auf das Potential der an die Leitungszone angeschlossenen Klemme des Halbleiterbauelements abzüglich der Durchbruchspannung der Zenerdiode aufgeladen. Bei leitendem Halbleiterbauelement wird die in der Kapazität gespeicherte Ladung in die Lei tungszone injiziert, um die Gebiete des zweiten Leitungstyps zu entladen und eine gute Leitfähigkeit zu erreichen. Die vol le Leitfähigkeit wird bereits kurz nach Anlegen einer ent sprechenden Steuerspannung an die Steuerelektrode erreicht.The charge source is preferably one between the injectors ons area and a reference potential switched capacity. The Capacity is on the blocking semiconductor device Potential of the terminal of the Semiconductor device minus the breakdown voltage of the Zener diode charged. With a conductive semiconductor component the charge stored in the capacity is transferred to the Lei tion zone injected to the areas of the second conduction type to discharge and achieve good conductivity. The vol The conductivity is removed shortly after the creation of a speaking control voltage reached to the control electrode.
Gemäß einer weiteren Ausführungsform ist vorgesehen, das In jektionsgebiet, vorzugsweise über einen Widerstand und eine Diode an ein Hilfspotential anzulegen.According to a further embodiment, the In area, preferably via a resistor and a Apply diode to an auxiliary potential.
Das Halbleiterbauelement ist vorzugsweise als vertikaler MOSFET ausgebildet, wobei eine erste Anschlußklemme an einer Rückseite des Halbleiterkörpers an die Leitungszone ange schlossen ist. Die Kanalzone befindet sich dabei im Bereich einer Vorderseite des Halbleiterkörpers, über der die Steuer elektrode angeordnet ist. Vorzugsweise sind wannenartig im Bereich der Vorderseite angeordnete, die Kanalzone(n) umge bende Gebiete des zweiten Leitungstyps vorgesehen, die lei tend mit darüber angeordneten Feldplatten verbunden sind.The semiconductor component is preferably a vertical one MOSFET formed, with a first terminal on a Back of the semiconductor body to the conduction zone is closed. The channel zone is located in the area a front of the semiconductor body over which the tax electrode is arranged. Are preferably tub-like in Area of the front arranged, the channel zone (s) reversed Providing areas of the second conduction type, the lei tend to be connected with field plates arranged above.
Aufgabe dieser Gebiete des zweiten Leitungstyps und der Feld platten ist es, die Ausbreitung von Ladungsträgern in latera ler Richtung zu begrenzen. Das Injektionsgebiet ist vorzugs weise beabstandet zu den Kanalzonen, getrennt durch diese Ge biete angeordnet.Abandon these areas of the second conduction type and the field plates is the spread of charge carriers in latera limit your direction. The injection area is preferred spaced apart from the channel zones, separated by this Ge offer arranged.
Die vorliegende Erfindung wird nachfolgend in Ausführungsbei spielen anhand von Figuren näher erläutert. Es zeigen:The present invention is hereinafter described play with the help of figures. Show it:
Fig. 1 Querschnitt durch einen Ausschnitt eines erfindungs gemäßen Halbleiterbauelements; FIG. 1 is cross-section through a section of a semiconductor component according to Inventive;
Fig. 2 Ersatzschaltbild des erfindungsgemäßen Halbleiter bauelements mit einer Ladungsquelle gemäß einer er sten Ausführungsform; Fig. 2 equivalent circuit diagram of the semiconductor device according to the invention with a charge source according to a first embodiment;
Fig. 3 Ersatzschaltbild des erfindungsgemäßen Halbleiter bauelements mit einer Ladungsquelle gemäß einer zweiten Ausführungsform. Fig. 3 equivalent circuit diagram of the semiconductor device according to the invention with a charge source according to a second embodiment.
In den Figuren bezeichnen, sofern nicht anders angegeben, gleiche Bezugszeichen gleiche Teile und Bereiche mit gleicher Bedeutung.In the figures, unless otherwise stated, same reference numerals same parts and areas with the same Importance.
Fig. 1 zeigt einen Querschnitt durch einen Ausschnitt einer Ausführungsform eines erfindungsgemäßen Halbleiterbauele ments, das im Wesentlichen als vertikaler n-Kanal-MOSFET aus gebildet ist. Das Halbleiterbauelement weist einen Halblei terkörper 2 mit einer n-dotierten Leitungszone 4 aufweist, die sich im Wesentlichen zwischen einer Vorderseite und einer Rückseite des Halbleiterkörpers 2 erstreckt, und die als Drain-Zone des MOSFET funktioniert. An der Rückseite des Halbleiterkörpers 2 ist eine gut elektrisch leitende Schicht 3, beispielsweise aus Metall oder einem n+-dotierten Halblei termaterial zum Anschluß einer ersten Anschlußklemme D (Drain-Anschluß) des Halbleiterbauelements aufgebracht. In die Leitungszone 4 sind im Bereich der Vorderseite des Halb leiterkörpers 2 p-dotierte Kanalzonen 8 eingebracht, in denen wiederum n+-dotierte Anschlußzonen 6, die Source-Zonen des MOSFET, eingebracht sind. Die Kanalzonen 8 und die Anschluß zonen 6 sind in dem Ausführungsbeispiel durch eine gut elek trisch leitende Schicht 7, vorzugsweise aus Metall oder Poly silizium, die zum Anschluß einer zweiten Anschlußklemme S (Source-Anschluß) des Halbleiterbauelements dient, kurzge schlossen. Über den Kanalzonen 8 sind Steuerelektroden 20 an geordnet, die gegenüber dem Halbleiterkörper durch eine Iso lationsschicht, vorzugsweise ein Oxid, getrennt sind und die als Gate-Elektroden des MOSFET funktionieren. Fig. 1 shows a cross section through a section of an embodiment of a semiconductor component according to the invention, which is essentially formed as a vertical n-channel MOSFET. The semiconductor component has a semiconductor body 2 with an n-doped conduction zone 4 , which extends essentially between a front side and a rear side of the semiconductor body 2 , and which functions as a drain zone of the MOSFET. On the back of the semiconductor body 2 is a highly electrically conductive layer 3 , for example made of metal or an n + -doped semiconductor material for connecting a first connection terminal D (drain connection) of the semiconductor component. In the line zone 4 in the region of the front of the semiconductor body 2 p-doped channel zones 8 are introduced, in which in turn n + -doped connection zones 6 , the source zones of the MOSFET, are introduced. The channel zones 8 and the connection zones 6 are in the embodiment by a good elec trically conductive layer 7 , preferably made of metal or poly silicon, which is used to connect a second terminal S (source connection) of the semiconductor component, short-circuited. Above the channel zones 8 , control electrodes 20 are arranged, which are separated from the semiconductor body by an insulation layer, preferably an oxide, and which function as gate electrodes of the MOSFET.
In der Leitungszone 4 sind eine Vielzahl p+-dotierter Gebiete 10 beabstandet zueinander angeordnet. Diese hochdotieren Ge biete 10 können willkürlich in der Leitungszone 4 verteilt oder, wie in dem dargestellten Ausführungsbeispiel, in ver schiedenen Ebenen des Halbleiterkörpers angeordnet sein und weisen vorzugsweise eine kugelförmige, ellipsoidförmige oder ähnliche Form auf. Der Halbleiterkörper ist vorzugsweise durch aufeinanderfolgendes Abscheiden mehrere Epitaxieschich ten hergestellt, wobei die Gebiete 10 während des Herstel lungsprozesses auf den einzelnen Epitaxieschichten gebildet werden.A multiplicity of p + -doped regions 10 are arranged at a distance from one another in the line zone 4 . These highly doped regions 10 can be distributed arbitrarily in the line zone 4 or, as in the exemplary embodiment shown, be arranged in different planes of the semiconductor body and preferably have a spherical, ellipsoidal or similar shape. The semiconductor body is preferably produced by successive deposition of a plurality of epitaxial layers, the regions 10 being formed on the individual epitaxial layers during the production process.
Wenigstens einige der Gebiete 10 einer Ebene sind vorzugswei se untereinander gitterartig durch p+-dotierte Kanäle 14 mit einander verbunden. Vorzugsweise sind nur die Gebiete 10 mit einander verbunden, die im Bereich unter den Kanalzonen 8, bzw. den Source-Zonen 6 angeordnet sind. In Fig. 1 sind dies die Gebiete, die rechts der zur Verdeutlichung eingezeichne ten gestrichelten Linie angeordnet sind.At least some of the areas 10 of a plane are preferably connected to one another in a lattice-like manner by p + -doped channels 14 . Preferably, only the regions 10 are connected to one another, which are arranged in the region below the channel zones 8 or the source zones 6 . In Fig. 1, these are the areas that are arranged to the right of the dashed line shown for clarification.
In den Halbleiterkörper 2 ist in dem Ausführungsbeispiel im Bereich der Vorderseite ein p+-dotiertes Injektionsgebiet 16 eingebracht, das an eine Ladungsquelle C angeschlossen ist. Die Ladungsquelle C ist in dem Ausführungsbeispiel eine Kapa zität C, die zwischen dem Injektionsgebiet 16 und einem Be zugspotential M angeschlossen ist. Das Injektionsgebiet ist in eine n+-dotierte Wanne 18 in dem Halbleiterkörper 2 einge bettet. Das Injektionsgebiet 16 und die n+-dotierte Wanne 18 bilden eine Zenerdiode, die von der Leitungszone 4 bzw. dem n-Substrat des Halbleiterkörpers 2 zu der Kapazität in Sper richtung gepolt ist.In the exemplary embodiment, a p + -doped injection region 16 , which is connected to a charge source C, is introduced into the semiconductor body 2 in the region of the front side. In the exemplary embodiment, the charge source C is a capacitance C which is connected between the injection region 16 and a reference potential M. The injection area is embedded in an n + -doped well 18 in the semiconductor body 2 . The injection region 16 and the n + -doped well 18 form a zener diode which is poled from the conduction zone 4 or the n-substrate of the semiconductor body 2 to the capacitance in the reverse direction.
Das Halbleiterbauelement gemäß der Ausführungsform weist wei terhin wenigstens ein p-dotiertes Gebiet 30 auf, das in den Halbleiterkörper 2 eingebracht ist und das die Kanalzonen 8 bzw. die Source-Bereiche 6 ringartig umgibt. Das Gebiet 30 und auch die "äußerste" der Kanalzonen 8 sind an Feldplatten 32 angeschlossen, die in einer Isolationsschicht Ox über dem Halbleiterkörper angeordnet sind. Eine äußerte Feldplatte 36, die als "channel stopper" dient, ist leitend mit dem n- Substrat des Halbleiterkörpers 2 verbunden. Aufgabe des Ge biets 30 und der Feldplatten 32, 36 ist es, die Ausbreitung der Ladungsträger der Leitungszone in lateraler Richtung des Halbleiterkörpers 2 zu begrenzen.The semiconductor component according to the embodiment furthermore has at least one p-doped region 30 which is introduced into the semiconductor body 2 and which surrounds the channel zones 8 and the source regions 6 in a ring-like manner. The area 30 and also the “outermost” of the channel zones 8 are connected to field plates 32 , which are arranged in an insulation layer Ox above the semiconductor body. An outer field plate 36 , which serves as a "channel stopper", is conductively connected to the n-substrate of the semiconductor body 2 . The task of Ge area 30 and the field plates 32 , 36 is to limit the spread of the charge carriers of the conduction zone in the lateral direction of the semiconductor body 2 .
Das Injektionsgebiet 16 bzw. die Zenerdiode 16, 18 ist ge trennt durch das p-Gebiet 30 bzw. die Feldplatten 32, 36, von den Kanalzonen 8 bzw. den Source-Bereichen angeordnet. Gemäß einer weiteren nicht näher dargstellten Ausführungsform ist vorgesehen, das Injektionsgebiet zwischen den Kanalzonen an zuordnen, wobei das Injektionsgebiet dann vollständig von ei ner entsprechenden p-Gebiet- und Feldplattenstruktur umgeben sein müßte.The injection region 16 or the zener diode 16 , 18 is separated by the p-region 30 or the field plates 32 , 36 , from the channel zones 8 and the source regions. According to a further embodiment, which is not shown in any more detail, provision is made to assign the injection area between the channel zones, the injection area then then having to be completely surrounded by a corresponding p-area and field plate structure.
Die Funktionsweise des erfindungsgemäßen Halbleiterbauele ments wird im folgenden kurz beschrieben.The mode of operation of the semiconductor component according to the invention is briefly described below.
Bei Anlegen eines positiven Potentials an die Gate-Elektrode G, bzw. bei Anlegen einer positiven Spannung zwischen der Ga te-Elektrode und dem Source-Anschluß S bildet sich in der Ka nalzone 8 ein n-leitender Kanal aus, der bei positiver Drain- Source-Spannung einen Stromfluß ermöglicht. Der Widerstand der Leitungszone 4 ist bei Spannungen, die unterhalb der Spannungsfestigkeit des Halbleiterbauelements liegen abhängig von der Dotierung der Leitungszone 4. When a positive potential is applied to the gate electrode G, or when a positive voltage is applied between the gate electrode and the source terminal S, an n-type channel is formed in the channel zone 8 , which, when the drain is positive, Source voltage allows current to flow. The resistance of the line zone 4 is dependent on the doping of the line zone 4 at voltages which are below the dielectric strength of the semiconductor component.
Sperrt der Kanal in der Kanalzone 8 bei Wegnehmen des Ansteu erpotentials und baut sich eine große Drain-Source-Spannung, beispielsweise einige hundert Volt bei Verwendung des Halb leiterbauelements zur Ansteuerung einer Zündspule in einem Kraftfahrzeug oder einem Schaltnetzteil, auf, so breitet sich ausgehend von der Vorderseite des Halbleiterkörpers eine Raumladungszone aus, die nach und nach die in den einzelnen Ebenen angeordneten p+-Gebiete 10 erfasst. Dabei räumen sich die p-Gebiete 10 und die diese umgebenden n-Bereiche der Lei tungszone 4 gegenseitig aus, so daß es zu einer Verarmung an Ladungsträgern in der Leitungszone 4 kommt, was zu einer ho hen Spannungsfestigkeit führt. Bei diesen Vorgang wird die Kapazität C über die Zenerdiode 16, 18 auf das Potential an dem Drain-Anschluß D abzüglich der Durchbruchspannung der Zenerdiode aufgeladen. Während sich die miteinander verbunde nen p-Gebiete 10 einer Ebene auf gleichem Potential befinden, nimmt das Potential der nicht verbundenen p-Gebiete 10 in la teraler Richtung des Halbleiterkörpers ab.Locks the channel in the channel zone 8 when removing the control potential and builds up a large drain-source voltage, for example a few hundred volts when using the semiconductor component for controlling an ignition coil in a motor vehicle or a switching power supply, spreads from the front of the semiconductor body from a space charge zone, which gradually captures the p + regions 10 arranged in the individual planes. The p regions 10 and the surrounding n regions of the line zone 4 clear each other, so that there is a depletion of charge carriers in the line zone 4 , which leads to a high voltage resistance. In this process, the capacitance C is charged via the Zener diode 16 , 18 to the potential at the drain terminal D minus the breakdown voltage of the Zener diode. While the interconnected p-regions 10 of a plane are at the same potential, the potential of the non-connected p-regions 10 decreases in the la teral direction of the semiconductor body.
Wird das Halbleiterbauelement anschließend durch Anlegen ei ner Ansteuerspannung an die Gate-Elektrode G leitend gemacht, bleiben die p-Gebiete 10 zunächst aufgeladen und die Lei tungszone 4 an Ladungsträgern verarmt. Jedoch wird beim Ein schalten die in der Kapazität C gespeicherte Ladung über die in Flußrichtung gepolte Zenerdiode 16, 18 in die Leitungszone 4 injiziert um die p+-Gebiete 10 zu entladen und die volle Leitfähigkeit der Leitungszone 4 wiederherzustellen. Dieser Vorgang erfolgt schnell nach dem Einschalten des Halbleiter bauelements.If the semiconductor component is then made conductive by applying a drive voltage to the gate electrode G, the p regions 10 initially remain charged and the line zone 4 is depleted of charge carriers. However, when switching on, the charge stored in the capacitance C is injected into the conduction zone 4 via the Zener diode 16 , 18 polarized in the direction of flow in order to discharge the p + regions 10 and to restore the full conductivity of the conduction zone 4 . This process takes place quickly after switching on the semiconductor component.
Der erfindungsgemäße Injektor mit der Zenerdiode 16, 18 ver ursacht keinen zusätzlichen Spannungsabfall über der Last strecke, d. h. der Drain-Source-Strecke, des MOSFET.The injector according to the invention with the Zener diode 16 , 18 causes no additional voltage drop across the load path, ie the drain-source path, of the MOSFET.
Fig. 2 zeigt ein Ersatzschaltbild des erfindungsgemäßen Halbleiterbauelements, die sich als Verschaltung eines MOSFET T mit einer Zenerdiode Z darstellt, wobei die Zenerdiode an das Substrat des MOSFET M angeschlossen ist. Zwischen einer Klemme 34 und einem Bezugspotential M ist die Kapazität C ge schaltet, die bei sperrendem MOSFET über das Substrat und die Zenerdiode Z aufgeladen wird und bei leitendem MOSFET die ge speicherte Ladung wieder an das Substrat abgibt. Fig. 2 shows an equivalent circuit diagram of the semiconductor device according to the invention, which presents itself as a connection of a MOSFET T with a zener diode Z, the zener diode is connected to the substrate of the MOSFET M. Between a terminal 34 and a reference potential M, the capacitance C is switched, which is charged when the MOSFET is turned off via the substrate and the Zener diode Z and, when the MOSFET is conductive, releases the stored charge to the substrate again.
Das Ersatzschaltbild einer weiteren Ausführungsform des er findungsgemäßen Halbleiterbauelements ist in Fig. 3 darge stellt. Dabei ist die Klemme 34 über einen Widerstand R und eine Diode D an ein Hilfspotential U+ angeschlossen, wobei Ladung an das Substrat abgegeben wird, bzw. p-Ladungsträger in das Substrat injiziert werden, um die p-Gebiete 10 zu ent laden, wenn der MOSFET leiten soll. The equivalent circuit diagram of a further embodiment of the semiconductor device according to the invention is shown in FIG. 3 Darge. The terminal 34 is connected via a resistor R and a diode D to an auxiliary potential U +, wherein charge is released to the substrate, or p-charge carriers are injected into the substrate in order to discharge the p-regions 10 when the MOSFET should conduct.
22nd
Halbleiterkörper
Semiconductor body
33rd
leitende Schicht
conductive layer
44th
Leitungszone
Conduction zone
66
n+ n +
-Anschlußzone
-Connection zone
88th
p-Kanalzone
p-channel zone
1010th
p+ p +
-Gebiet
Area
1414
p+ p +
-Verbindungen
-Links
1616
p+ p +
-Injektionsgebiet
- injection area
1818th
n+ n +
-Wanne
Tub
2020th
Steuerelektrode
Control electrode
3030th
p-Gebiet
p-area
3232
Feldplatten
Field plates
3636
Feldplatte
C Kapazität
D Drain-Anschluß
DI Diode
G Gate-Anschluß
M Bezugspotential
Ox Isolationsschicht
R Widerstand
S Source-Anschluß
U+ Hilfspotential
V+ Versorgungspotential
Z Zenerdiode
Field plate
C capacity
D drain connector
DI diode
G gate connector
M reference potential
Ox insulation layer
R resistance
S source connector
U + auxiliary potential
V + supply potential
Z zener diode
Claims (8)
- - einen Halbleiterkörper (2) mit einer Leitungszone (4) eines ersten Leitungstyps, einer Anschlußzone (6) des ersten Lei tungstyps, einer zwischen der Anschlußzone (6) und der Lei tungszone (4) angeordneten Kanalzone (6) eines zweiten Lei tungstyps und mit einer Vielzahl von beabstandet zueinander in der Leitungszone angeordneten Bereichen (10, 12) des zwei ten Leitungstyps,
- - eine isoliert gegenüber der Kanalzone (8) angeordnete Steu erelektrode (20),
ein in dem Halbleiterkörper (2) angeordnetes Injektionsgebiet (16) des zweiten Leitungstyps, das an eine Ladungsquelle an geschlossen ist.1. Semiconductor component which has the following features:
- - a semiconductor body (2) of a first conductivity type, a connecting zone (6) processing type of the first Lei with a conduit region (4), one between the connection zone (6) and the Lei processing zone (4) arranged channel region (6) processing type of a second Lei and with a plurality of regions ( 10 , 12 ) of the second conduction type which are arranged at a distance from one another in the conduction zone,
- - A control electrode ( 20 ) arranged isolated from the channel zone ( 8 ),
an injection region ( 16 ) of the second conductivity type arranged in the semiconductor body ( 2 ), which is connected to a charge source.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE1999148901 DE19948901B4 (en) | 1999-10-11 | 1999-10-11 | Field effect controllable semiconductor device |
| PCT/EP2000/009962 WO2001028002A1 (en) | 1999-10-11 | 2000-10-10 | Semiconductor component, controlled by field effect |
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| Application Number | Priority Date | Filing Date | Title |
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| DE1999148901 DE19948901B4 (en) | 1999-10-11 | 1999-10-11 | Field effect controllable semiconductor device |
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| DE19948901A1 true DE19948901A1 (en) | 2001-04-19 |
| DE19948901B4 DE19948901B4 (en) | 2008-05-08 |
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| DE1999148901 Expired - Fee Related DE19948901B4 (en) | 1999-10-11 | 1999-10-11 | Field effect controllable semiconductor device |
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| WO (1) | WO2001028002A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10108046A1 (en) * | 2001-02-20 | 2002-09-12 | Infineon Technologies Ag | Semiconductor device e.g. compensation FET has compensation regions connected to active zone via resistance |
| EP1294024A2 (en) * | 2001-09-17 | 2003-03-19 | Infineon Technologies AG | Semiconductor device |
| DE102005023026A1 (en) * | 2005-05-13 | 2006-11-16 | Infineon Technologies Ag | Vertical power transistor with plate capacitor structure for use in, e.g., clocked switch power packages, has edge plate attached at front side between edge and edge connector, and laminated on field plate to form plate capacitor structure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05283702A (en) * | 1992-04-03 | 1993-10-29 | Hitachi Ltd | Composite control type semiconductor device and power converter using thereof |
| DE19815907C1 (en) * | 1998-04-08 | 1999-05-27 | Siemens Ag | Field effect semiconductor element |
| DE19819590C1 (en) * | 1998-04-30 | 1999-06-24 | Siemens Ag | Power MOSFET for high conductivity transistor switch |
-
1999
- 1999-10-11 DE DE1999148901 patent/DE19948901B4/en not_active Expired - Fee Related
-
2000
- 2000-10-10 WO PCT/EP2000/009962 patent/WO2001028002A1/en active Application Filing
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10108046A1 (en) * | 2001-02-20 | 2002-09-12 | Infineon Technologies Ag | Semiconductor device e.g. compensation FET has compensation regions connected to active zone via resistance |
| DE10108046B4 (en) * | 2001-02-20 | 2006-10-19 | Infineon Technologies Ag | Semiconductor device |
| EP1294024A2 (en) * | 2001-09-17 | 2003-03-19 | Infineon Technologies AG | Semiconductor device |
| DE10145723A1 (en) * | 2001-09-17 | 2003-04-10 | Infineon Technologies Ag | Semiconductor structure |
| EP1294024A3 (en) * | 2001-09-17 | 2005-05-11 | Infineon Technologies AG | Semiconductor device |
| DE102005023026A1 (en) * | 2005-05-13 | 2006-11-16 | Infineon Technologies Ag | Vertical power transistor with plate capacitor structure for use in, e.g., clocked switch power packages, has edge plate attached at front side between edge and edge connector, and laminated on field plate to form plate capacitor structure |
| US7872300B2 (en) | 2005-05-13 | 2011-01-18 | Infineon Technologies Ag | Power semiconductor component with plate capacitor structure |
| DE102005023026B4 (en) * | 2005-05-13 | 2016-06-16 | Infineon Technologies Ag | Power semiconductor device with plate capacitor structure |
Also Published As
| Publication number | Publication date |
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| DE19948901B4 (en) | 2008-05-08 |
| WO2001028002A1 (en) | 2001-04-19 |
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