DE19924113A1 - Signal processing method for active movement sensor in motor vehicle involves delaying output pulse with respect to input pulse by integration using capacitor to suppress interference having period shorter than delay time - Google Patents

Abstract

Sensor produces a first sequence of input pulses containing movement information. Each input pulse in a sequence is integrated and a corresponding output pulse is generated within a period during which the integrated signal exceeds a second threshold, after exceeding a first threshold, so that the output pulse is delayed with respect to the input pulse. The generated signal is produced by charging a capacitor, the thresholds being defined by the voltage drop across the capacitor. An Independent claim is given for a signal processing circuit.

Description

The invention relates to a method and a circuit Regulations for signal processing for an active movement sensor, the at least a first sequence of movement information generated input pulses, in particular for an active speed sensor.

Active motion sensors generally consist of one Sensor with a magnetostatically sensitive Element with a permanent magnet (sensor element) that lead magnetically to a movement to be detected is coupled to the encoders. The sensorele ment speaks to one by this movement called change in the flux density or the field vector. The The output signal of the sensor element is sent to a modulator performed either a periodic sensor voltage or generates a periodic sensor current, the frequency is determined by the speed of movement.

A particular advantage over these active sensors the known passive sensors is that the Voltage of the generated sensor signal from the Bewegungsver hold and in particular the speed of movement is dependent and thus level adjustments and protection circuits are largely superfluous. For this reason, Akti ve motion sensors increasing prevalence. Depending on the version tion is generally a pulse voltage or a Pulse current generated as a sensor signal of a signal processing device is fed to processed and  evaluated and then for example to a drive or Brake slip control as a motion signal to who transmitted the.

However, precautions must also be taken here to avoid interference and in the event that a malfunction occurs, ensure that none of the driving reactions that could endanger tool operation. In In this connection a distinction must be made between disturbances conditions that lead to a total failure of the sensor signal, and those disturbances that affect this signal in a way influence that the acted regulation no longer in one appropriate to the actual vehicle operating condition reacted wisely. These latter disorders can for example by ignition pulses, ESD discharges and others re signals are generated, their duration up to one Third of the useful signal duration can be. They cause that by superimposing the sensor signal on its frequency temporarily changed and erroneously changed by the signal processing device changes the movement speed is displayed.

Since a distinction between a change in Sen sorsignal due to an actual change of the Bewe behavior and a change due to that Sensor signal impairing interference difficult and on is maneuverable, has apparently been based on precautions for ver preventing a possible misinterpretation of the sensori gnals waived.

The invention is therefore based on the object, a Ver drive and a circuit arrangement for signal processing for an active motion sensor of the aforementioned Way of creating the effects of disturbance  conditions that occur only temporarily and in a way which lead to a misinterpretation of the sensor signal can, are essentially preventable.

This task is solved with a signaling method processing for an active motion sensor at the beginning mentioned type, which is characterized in that each one integrated pulse of a pulse sequence and an assigned Output pulse is generated during a period in which the integrated signal after exceeding a predeterminable first threshold value over a predeterminable second Threshold is so that the output pulse compared to the Input pulse is delayed.

The task is also carried out with a circuit arrangement Signal processing for an active motion sensor solved type mentioned, which at least one inte has filtering circuit with which each input pulse integrated into a pulse sequence and an assigned off is generated during a period in which the integrated signal after exceeding a predetermined he most threshold value above a predeterminable second threshold value so that the output pulse is opposite the input pulse has a time delay.

These solutions have the advantage that interference is shorter are as the delay time, this ver only slightly lengthen and as a small change in speed within of a tolerable range can be classified. Just such disturbances that last longer than those caused by the Integration caused delay, can ver an error cause, but only with this time delay problem occurs.  

The subclaims have advantageous developments of Invention to the content.

Then the integrating filter circuit can be an analog Filters with a capacitor and at least one current be source for charging the capacitor and for Er generation of the integrated signal with the input pulse be can be opened, the first and the second threshold value in each case by a predetermined, on the capacitor falling voltage value is determined.

Alternatively, the integrating filter circuit can also be a digital filter with at least one counter that the input pulse can be acted upon for activation, wherein the integrated signal represents a counter reading and the first and second thresholds each by ei NEN predetermined meter reading to be achieved is determined.

Further details, features and advantages emerge from the following description of preferred embodiment shape using the drawings. Show it:

FIG. 1 is a principle block diagram of a sensor array having signal processing means for active movement sensors;

Fig. 2 is a first filter circuit;

Fig. 3 different waveforms in the first filter circuit;

Fig. 4 shows a second filter circuit; and

Fig. 5 different waveforms in the second filter circuit.

Fig. 1 shows a general schematic block diagram of a sensor arrangement with a circuit arrangement for signal processing for active motion sensors. In the case shown, an encoder 1 is provided which executes a rotary movement to be detected and acts on a sensor element 2 via a change in the flux density or the field vector. The sensor element is part of an assembly which is combined to form a sensor module 3 and which has a modulator 4 and a current source 5 . The modulator 4 controls in dependence on the output signal of the sensor element 2 and an optional data signal supplied via an additional connection K5 the current source, so that a first sequence of input pulses containing movement information and a second sequence of input pulses containing additional information is generated. It is a so-called 3-level sensor with which, in contrast to the 2-level sensors, additional information (data) can be transmitted in addition to the movement information. These follow in the pulse are fed to suppress interference a first and a second filter circuit FS1, FS2, the output pulses of which are processed further in the signal processing device 6 .

In order to suppress the type of interference mentioned at the beginning, the first and second filter circuits FS1, FS2 are described below with reference to FIGS. 2 and 4. With regard to the selection of the filter circuit, a distinction must be made between a disturbance in the movement signal and a disturbance in the data signal. Since the motion signal is used, for example, to calculate a dynamic vehicle state, it must be filtered in a particularly interference-free manner. For this purpose, the first filter circuit according to FIG. 2 with an integrated analog filter offers itself, since this has a largely constant delay and freedom from jitter.

The data signals are generally not equally relevant for vehicle dynamics, so that more errors can be tolerated for this. For this reason, the application of the second filter circuit shown in FIG. 4 with an integrated digital filter and digital delay elements is generally sufficient.

Fig. 2 shows the first filter circuit, which also includes a circuit unit for converting and dividing the various current levels of the sensor signal into voltage levels. Both 2-level and 3-level sensor signals can be applied. The filter circuit has a first input ASI for the sensor current signal, which is connected to a circuit part 10 for current limitation and con figurable current mirroring. About a second and a third control signal input ASDE, ASHC, which are also connected to the circuit part 10 , the mirror factor that determines the ratio between the input current and the output current of the circuit part 10 is adjustable, so that an adjustment of the filter scarf device to different sensors with different current levels and thus a normalization of the sensor current is possible.

To mirror the sensor current, the output of the switching device part 10 leads to ground via a shunt resistor RS1 to which a corresponding sensor voltage drops. In the case in which the sensor module 3 or the modulator 4 generates a suitable sensor voltage instead of the sensor current, the current mirroring is of course superfluous.

To evaluate the current converted into voltage level gel, the sensor voltage is on the non-inverting  Inputs of a first to fourth comparator K1, K2, K3, K4 on. In a fourth input CURREF of the filter circuit a reference current is fed, whereby between this Input and ground of a first series connection from a he most to fourth resistor R1, R2, R3, R4 and one to it parallel connected second series connection of a five ten to seventh resistor R5, R6, R7.

The fourth input CURREF is also inverted connected to the input of the fourth comparator K4. An in vertical input of the third comparator K3 is over a first switch S1 optionally with a first Ab reached between the first and the second resistor R1, R2 or a second tap between the fifth and the sixth resistor R5, R6 connectable. An inverting Input of the second comparator K2 is with a third Tap between the second and the third resistor R2, R3 connected. An inverting input of the first compa rators K1 is finally a second switch S2 optionally with a fourth tap between the third and the fourth resistor R3, R4 or a fifth Ab reached between the sixth and seventh resistor R6, R7 connectable. The switches S1, S2 are over the off gear of a first OR gate O1 actuated, the inputs with the second or third input connection ASDE, ASHC are connected to the filter circuit.

With this circuit unit, the sensor signal present at the first input ASI is classified into five different current or voltage levels. These levels correspond to the following states:

• a) Sensor supply current too low (if no sensor connected or it is defective),  
• b) sensor quiescent current in the target range,
• c) data signal at high level (only with 3-level sensors),
• d) high level motion signal,
• e) Sensor supply current too high (if on at the input Short circuit to ground or the sensor is defective is).

The reference voltages are determined using the four th input CURREF applied reference current and at the series resistor circuits are and are - with Exception in the case where the second and third Ein ASDE, ASHC low potential and the order switch S1, S2 for switching between two voltages thresholds are applied - due to the standardization of the Sensor current constant for all sensors.

At the respective exit of the first to fourth Kompara tors K1 to K4 depends on the current one Sensor voltage level a first to fourth output signal LVL1 to LVL4. These signals are used to filter the Data signal of the second filter circuit (output LVL [4: 1]) fed. To filter the motion signal, the Output signals LVL2 and LVL3 of the second and third com parators K2, K3 fed to a first multiplexer M1. For Control of this multiplexer is a first AND gate U1 provided at the inputs of the second and third tax signal input ASDE, ASHC and its output with connected to a control input of the first multiplexer M1 is.

The first multiplexer M1 is controlled so that in the case one 2-level sensor the output signal LVL2 of the second Comparator K2 and in the case of a 3-level sensor the off gear signal LVL3 of the third comparator K3 as a comparator  signal LVLASO switched through and a control connection Analog switch S3 is supplied. The one he depicted The first filter circuit is designed for a 3-level sensor, because here the motion signal in favor of transmission the data signals must be shortened. The analog switch S3 is thus to the extent that the movement signal through the reference fed into the fourth input CURREF current-generated threshold reached, opened and closed.

By closing and opening the analog switch S3, who connected the first and a series-connected second current source I1, I2, which are connected between a positive supply voltage (5V) and ground. A capacitor C is connected in parallel with the first current source I1 and is thus constantly charged with a constant current. By closing the analog switch S3, an additional current flows (approximately 2.I1), so that a substantially linear rising or falling Ver course of the voltage UI_AS0 is achieved on the capacitor. The capacitor voltage is supplied to a non-inverting input terminal of a fifth comparator K5. At an inverting input of the fifth comparator K5, which has a hysteresis U _th , there is a constant voltage of approximately 2.5V. The output of the fifth comparator K5 is connected to an output terminal ASO of the first filter circuit, to which the delayed motion sensor pulse signal ASL3 is applied.

For the function of the first filter circuit it is important that the motion signal (wheel pulse) always the capacitor C. can charge up to the limit. Here are all toles the sensor pulse width, from scattering of the capaci Actual value of the capacitor C and deviations in the currents the first and second current sources I1, I2  The hysteresis of the fifth comparator K5 is thereby chosen as large as possible, since they go directly into the interference suppressor received. It is also required that the delay of the S3 analog switch when opening and closing the analog delay is negligible. The delays However, the fifth comparator K5 is irrelevant as long as its delay time is smaller than the sensor signal pulse duration.

The function of the first filter circuit will be explained below with reference to the voltage and current curves shown in FIG. 3. By moving the encoder 1 , a sensor pulse voltage BP (motion signal) is generated in the sensor, the pulses of which, after appropriate preparation according to FIG. 3a, are essentially rectangular and have an essentially constant pulse duration T0. The sensor current I _ASI generated by the modulator 4 is shown in FIG. 3b. With a rising edge of the sensor pulse BP, this current increases from a first value I _SENS1 , which is slightly above the first current _threshold I _LVL1 , essentially linearly to a third value I _SENS3 . When the third current _threshold I _{LVL3 is reached} after a first time period T1p, the output LVL3 of the third comparator K3 according to FIG. 3c switches to a high level, so that the analog switch S3 is closed and the capacitor C is charged.

The course of the voltage UI_ASO across the capacitor C and thus also at the non-inverting input of the fifth comparator K5 is shown in FIG. 3d. This voltage rises linearly from a minimum value Vmin below a lower threshold value LO_THR to a maximum value Vmax, which is formed by the supply voltage of 5V and is above an upper threshold value UP_THR. When the voltage UI_ASO reaches the upper threshold value UP_THR = 2.5V + U _TH / 2 after a second time period T3p, the output voltage ASL3 of the fifth comparator K5 is set to a high level at the output ASO according to FIG. 3e.

As soon as the sensor pulse voltage BP according to FIG. 3a drops to a low level again after the pulse duration T0 has elapsed, the sensor current I _ASI according to FIG. 3b also drops substantially linearly back to its original first value I _SENS1 . When the third current _threshold I _{LVL3 is reached} after a third time period T1n, the high level (with fourth time period T2) of the output signal LVL3 of the third comparator K3 according to FIG. 3c is reset to low level. As a result, the analog switch S3 is opened again, so that the capacitor voltage UI_ASO according to FIG. 3d essentially linearly drops from its maximum value Vmax back to its original minimum value Vmin. When the lower threshold LO_THR = 2.5V - U _TH / 2 is reached after a fifth time period T3n, the high level (with sixth time period T4) of the output ASL3 of the fifth comparator K5 according to FIG. 3e is reset to a low level.

With the first filter circuit, the sensor current I _ASI is thus integrated. The value ASL3 present at the output of the filter circuit changes its level as soon as the upper or lower threshold value UP_THR, LO_THR of the fifth comparator K5 is reached. In the fault-free case, this leads to a constant delay of the filter output signal ASL3 (= ASO) compared to the sensor signal present at the input by the sum of the first and the second time period T1p, T3p, this sum being the first filter time and the sum of the third and fifth time duration T1n, T3n should accordingly be referred to as the second filter time. A disturbance of the type mentioned, which superimposes a residual current on the sensor signal useful current, does not result in a change in the output signal ASL3 of the fifth comparator K5, but only in an extension of the delay, provided it is shorter than the filter time.

The filter circuit must therefore be designed so that a possible filter time is as long as possible and this is due to a fault caused filter time extension in a tolerier area remains, which means that a connected Control the disturbance only as a low speed interpreted difference.

The second and fifth time periods T3p, T3n can each be a maximum of as long as the minimum pulse duration T0. If a malfunction of the type mentioned occurs, this leads to a change in the sign of the slope of the capacitor voltage UI_ASO. For example, assume that the sensor current I _ASI has exceeded the third threshold I _LVL3 , but the second time period T3p has not yet expired. This fault then leads to the fact that the already integrated voltage UI_ASO on capacitor C is integrated for the duration of the fault. So that the output signal is still switched correctly, this disintegration must be reversed after the fault has disappeared. This takes as long as the fault itself was present. From Fig. 3 it is apparent that a failure remains without consequences if their duration does not exceed the value T _sturgeon = 0.5. (T2 T3p). A second and fifth time duration T3p, T3n of 70% of the sensor pulse duration T0 has proven to be a particularly advantageous compromise. A detailed explanation of this follows below.

A calculation example should now be given below:
The critical case to which the filter circuit must be designed is the shortest fourth time period T2min, within which the capacitor C must be charged up to the supply voltage Vmax. The following values are assumed:
Duration of a sensor pulse BP:
T0 = 40 to 60 µs;
First to fourth current thresholds:
I _LVL1 = 4.5 mA, I _LVL2 = 10 mA, I _LVL3 = 20 mA, I _LVL4 = 38 mA;
Threshold tolerance: +/- 10%;
First to third sensor current:
I _SENS1 = 7 mA, I _SENS2 = 14 mA, I _SENS3 = 28 mA;
Sensor tolerance: -16% to + 20%;
Capacitor _tolerance : C _TOl = +/- 30%;
Hysteresis: U _Hyst = 2V;
Current rise rate of the sensor:
SR _I = 6 - 14 mA / µs;
Minimum fourth period
T2min = T0min + T1nmin - T1pmax;
Maximum delay of the first time period T1p until the third comparator K3 switches its output LVL3 to a high level:
T1pmmax = (I _LVL3 max - I _SENS1 min) / SR _I min
T1pmax = (22 mA - 5.88 mA) / 6 mA / µs
T1pmax = 2.69 µs;
Minimum delay of the third time period T1n until the third comparator K3 switches its output LVL3 to a low level:
T1nmin = (I _SENS3 min - I _LVL3 max) / SR _I max
T1nmin = (23.52 mA - 22 mA) / 14 mA / µs
T1nmin = 0.11 µs;
Minimum fourth period of time T2min within which the capacitor should be charged at the latest in order to ensure an equal delay from the rising to the falling edge of the capacitor voltage:
T2min = (40 + 0.11 - 2.69) µs
T2min = 37.42 µs;
Charging the capacitor:
UI_ASO = (I1.t) / C
Maximum capacitance value of the capacitor at which the capacitor voltage is still limited with a minimum sensor pulse width:
Cmax = (I1.T2min) / (Vmax - Vmin)
Cmax = C. (1 + C _Tol )
C = (I1.T2min) / (Vmax - Vmin) / (1 + C _Tol )

Determination of the maximum suppressible fault

A fault leads to a change in the sign of the integra tion. In the case considered above, this means that the end value is not achieved. This case is for the sensor Pulse particularly critical because it is shorter than that Pulse with which data is transmitted. The interpretation must therefore take place so that the switching threshold lower lies as the limit and thus also in the event of a fault a switchover takes place.

The maximum suppressible disturbance is calculated as follows:
T _Stör max = 0.5. (T2min - T3p)
T3p = (UP_THR - Vmin) .C. (1 + C _Tol ) / I1

T _Stör max should be around 15% of T2min. For the value UP_THR this means:
UP_THR = 0.7. (Vmax - Vmin).

For the value of LO_THR, the following results analogously:
LO_THR = 0.3. (Vmax - Vmin)

Determination of the specified parameters

It is not readily possible to measure internal quantities within an integrated circuit. In particular, the capacitance of the capacitor and the current value cannot be measured from the outside. However, since only the interference suppression per se, that is, the time required to switch the output signal ASO from the filter circuit, is of interest, the following measurement can be carried out: The first input connection ASI is in the manner that at the output ASO adjacent, delayed sensor pulse signal coupled back that an oscillation occurs. This oscillation represents the internal charging and discharging of the capacitor within the two thresholds UP_THR and LO_THR and is the measure for interference suppression:

0.22.37 µs </ = T _{L_ASO} = T _{H_ASO} </ = 0.4.37 µs

Another test measures the delay between a change in the sensor current and the reaction at the output connection ASO of the filter circuit. This test shows whether the output switches correctly even with the shortest wheel pulse:

0.4.37 µs </ = T3p = T3n </ = 0.7.37 µs.

FIG. 4 shows a block diagram of a digital second filter circuit, which is provided in particular for the data signals transmitted with the sensor signals. Dieje nige circuit unit, which includes the circuit part 10 , the first to fourth comparators K1 to K4, the first to seventh resistor R1 to R7, the first and second changeover switches S1, S2, the shunt resistor RS1 and the first OR gate O1, is not shown. Instead of the first input ASI for the sensor signal, four inputs LVL1, LVL2, LVL3, LVL4 are thus provided, at each of which the corresponding outputs of the first to fourth comparators K1 to K4 according to FIG. 2 (there the outputs LVL [4: 1] ). The second and third inputs ASDE, ASHC according to FIG. 2 are also present here.

The second filter circuit includes for each sensor in the we a first and a second integrating digi tales filter IF1, IF2, and a third and a fourth simple digital filter F3, F4. Clock inputs CLK des er The first and second filters IF1, IF2 have a first Clock input TU286 of the filter circuit, clock inputs CLK of the third and fourth filters F3, F4 are with a second Clock input T1U1 of the filter circuit connected. Farther are reset inputs CLR CLRB of the first to fourth fil ters IF1 to F4 with a reset input MRESET of the fil circuit connected.

The second and third inputs ASDE, ASHC are over a second AND gate U2 linked together, the output signal on the one hand via a first inverter In1 to the control input of a second multiplexer M2, see above as continues to the control input of a third multiple xers M3 is performed. At a 1 input of the second multi plexers M2, the LVL3 input is connected to a 0 input of the second multiplexer M2 the input LVL4 on, the off gang of the second multiplexer M2 via a second inverter ter In2 ver with an input CLRA of the third filter F3 is bound. The input LVL3 of the second filter circuit is the ON with the input UP / DN of the first filter IF1 gang LVL2 with an input UP / DN of the second filter IF2 and the LVLI input with the fourth fil. CLRA input ters F4 connected.  

The output signals of the filters are used to carry out ei a plausibility check as follows ties: the output of the first filter IF1 is due to one 1 input of a third multiplexer M3 and a first Input of a third AND gate U3. The exit of the wide filter IF2 is at a first input of a fourth AND gate U4, a first input of a second OR gate O2 and at a second output ASL2 Filter circuit on. The output of the third filter is IF3 with a second input of the third AND gate U3 and connected to a second input of the fourth AND gate U4. The output of the fourth filter IF4 is finally egg nem inverting second input of the second OR gate O2 connected.

The output of the third AND gate U3 is the fourth Output ASL4 of the second filter circuit led while the output of the second OR gate O2 with the first off gang ASL1 of the second filter circuit is connected. The The fourth AND gate U4 has an output at the 0 input of the third multiplexer M3, the output of which third output ASL3 of the filter circuit is connected.

With the third and fourth (simple) digital filters F3, F4, the data signal is delayed by a constant time, these filters being reset immediately if error information is no longer present. The first and the second (integrating) digital filter IF1, IF2 works in principle like the analog sensor signal filtering according to FIG. 2. The signals at the inputs LVL2, LVL3 give the counting direction of the counters in the first and the second filter IF1, IF2 before. An upper and a lower limit stop are implemented in each counter. As soon as these stops are reached, the counter in question is blocked for the corresponding counting direction, and the signal at the output concerned changes in accordance with the counting direction.

Because of the different filter characteristics of the digi The filter is also the plausibility check intended. This means that the lower current value corresponds not under a signal at the first output ASL1 can be stepped if the current value above it corresponding to a signal at the second output ASL2 is exceeded. The same applies accordingly for the current values, which are output signals at the third th and fourth outputs ASL3, ASL4 are represented.

This digital second filter circuit is especially for Filtering interference due to a lack of electro magnetic compatibility (EMC) of other devices hen. For an overcurrent and undercurrent caused by this the lower time limit results from the forde tion that an overcurrent in a motion sensor signal should be recognizable. With the first and second integrie renden digital filters IF1, IF2 are interference that a Data protocol concern, filtered out. Doing so for the data protocol the second and third current threshold LVL2, LVL3 used. The first and second filters IF1, IF2 works in a similar way to the analog first fil terschaltung for the motion sensor signals, it will but the current threshold evaluation to control a up or down counter. A kri tical case arises in the pause between the movements and the data pulses. The inte filter first at the upper stop and must be in the break can return to zero. In this Be Both the analog values and the  Tolerance of the time base.

FIG. 5 shows the different voltage and current profiles in the second filter circuit according to FIG. 4.

By moving the encoder 1 , a motion sensor pulse voltage is generated in the sensor, the processed pulses BP of which are essentially rectangular according to FIG. 5a and have an essentially constant pulse duration T0. Wei further, a data signal is to be transmitted according to FIG. 5b, which also consists of essentially rectangular pulses DP, which are generated at a distance of approximately T0 / 2 after a sensor pulse BP and which have a duration of T0 / 2 exhibit. These two pulse sequences are fed to the modulator 4 .

The total sensor current I _ASI generated by the modulator 4 is shown in FIG. 5c. With a rising edge of the sensor pulse BP, this current increases from a first value I _SENS1 , which is slightly above the first current _threshold I _LVL1 , essentially linearly to a third value I _SENS3 . When the second current _threshold I _{LVL2 is reached} , the input LVL2 switches according to FIG. 5g to a high level, when the third current _threshold I _{LVL3 is reached} , the input LVL3 switches according to FIG. 5d to a high level.

After the time period T0 and the end of the movement pulse BP, the sensor current I _ASI also drops substantially linearly back to its first value I _SENS1 . With reaching the third current _threshold I _LVL3 , the input LVL3 according to FIG. 5d again assumes low potential, with reaching the second current _threshold I _LVL2 after the time period T1n, the input LVL2 according to FIG. 5g also drops back to its low level .

With a rising edge of the data pulse DP, the sensor current I _ASI rises from its first value I _SENS1 to a second value I _SENS2 in a substantially linear _manner . With the reaching of the second current _threshold I _LVL2 after the time T1p, the second input LVL2 is again switched to high level according to FIG. 5g. Conversely, with the end of the data pulse DP, after the time period T0 / 2 has elapsed, the sensor current I _ASI drops again substantially _linearly to its first value I _SENS1 , the input LVL2 as its reaching the second current _threshold I _LVL2 assumes a low level (see FIG. 5g).

FIG. 5e shows the course of a third counter voltage ASL3ctr, which increases from a minimum value Vmin substantially linearly to a maximum value Vmax when the third input voltage LVL3 according to FIG. 5d assumes the high potential. Conversely, the counter voltage ASLctr drops again to the value Vmin when the third input voltage LVL3 again assumes the low potential. The corresponding course of the third output voltage ASL3 is shown in FIG. 5f. This voltage assumes a high level when the third counter voltage ASL3ctr has reached its maximum value Vmax and drops again to a low level when the counter voltage ASL3ctr again assumes the minimum value Vmin.

Fig. 5h and 5i show the waveforms of a second counter voltage ASL2ctr and the second output voltage ASL2 function of the second input voltage LVL2. Thereafter, the second counter voltage ASL2ctr rises from its minimum value Vmin to its maximum value Vmax with a rising edge of the second input voltage LVL2 and falls again to its minimum value Vmin within a time period Tctr with a falling edge of the second input voltage. When the second counter voltage ASL2ctr has reached its maximum value, the second output voltage ASL2 also switches to high potential according to FIG. 5i. This potential changes back to the low value when the second counter voltage ASL2ctr has reached its minimum value again. After the period T2 has elapsed, the second counter voltage ASL2ctr rises again with the rising edge of the second input voltage LVL2 according to FIG. 5g. After reaching its maximum value, the second output voltage ASL2 is switched to a high level. With the falling edge of the second input voltage LVL2, the second counter voltage ASL2ctr drops again and, after reaching its minimum value, also switches the second output voltage ASL2 back to a low level.

In the following a calculation example for be given the second filter circuit. As a basis for this, let an oscillator frequency f0 = 3.52 MHz and one Oscillator tolerance of +/- 25% assumed.

For correct functioning of the integrating first and second filters IF1, IF2, T2 <0 must remain:

T2 = T0 / 2 + T1p - T1n - Tctr <0

To be as insensitive to interference as possible To create, the filter time Tctr should be maximum.

In this case, T2 = 0:
T1n - <maximum,
T1p - <minimal,
T0 / 2 - <minimal.
T1nmax = (I _SENS3 max - I _LVL2 min) / SR _I min
T1nmax = (33.6 mA - 9 mA) / 6 mA / µs
T1nmax = 4.1 µs
T1pmin = (I _LVL2 min - I _SENS1 max) / SR _I max
T1pmin = (9 mA - 8.4 mA) / 14 mA / µs
T1pmin = 43 ns
Tctrmax = T0 / 2min + T1p - T1n
Tctrmax = (20 + 0.043 - 4.1) µs
Tctrmax = 15.86 µs

The counter is clocked at the oscillator frequency, so that the time Tctr can be expressed as a function of the counter reading N and the clock frequency:
Tctr = N / f0
Tctrmax = N / f0min
Nmax = Tctrmax.f0min
Nmax = 15.86 µs. (3.52 MHz. (1 - 0.25))
Nmax = 41

This counter reading is maxi under unfavorable conditions times reachable and gives the maximum achievable filter kung. Every fault leads to a change in the counting direction of the filter so that it only corresponds to its stop Reached later and thus also its exit speaking later changes. This means in the considered above In the event that even minor disturbances are sufficient to get one Prevent change of output. That's why it's a compro between the filtering effect and the data suppression necessary. The compromise is particularly advantageous if  the meter reading N is 2/3 of the maximum value calculated above tes, d. H. is chosen as N = 24.

The digital third and fourth filters F3, F4 are to be designed for overcurrent and undercurrent. The goal is to detect an overcurrent even during a motion sensor pulse. The minimum time T _Iover min of the overcurrent is calculated as follows:
T _Iover min = T0min- (I _LVL4 max-I _SENS1 min) / SR _I min
T _Iover min = 40 µs- (41.8 mA - 5.88 mA) / 6 mA / µs
T _Iover min = 34 µs

This time is measured with the frequency divided by four oscillators so that the number of periods can be specified as follows:
T _Iover min = Nmax / f0min. 4
Nmax = T _Iover min.f0min / 4
Nmax = 22

In order to also be able to record overcurrents that a delay from the start of the movement pulse set, this value is reduced to N = 18.

The device according to the invention is also for use with a passive motion sensor suitable when making a cut is provided with which the sensor signal le, whose amplitude generally depends on the movement gene speed is dependent, in corresponding signals with a motion-dependent frequency can be converted.

Claims (8)

1. A method for signal processing for an active motion sensor which generates at least a first sequence of input pulses containing motion information, characterized in that each input pulse integrates a pulse sequence and an associated output pulse is generated during a period in which the integrated signal after exceeding a prespecified ren first threshold is above a predeterminable two-th threshold, so that the output pulse is delayed over the input pulse. 2. The method according to claim 1, characterized in that the integrated signal is generated by charging a capacitor (C) and represents the capacitor voltage, the he and the second threshold by one given chip dropping at the capacitor value (UP_THR, LO_THR) is determined. 3. The method according to claim 1 or 2, characterized in that the integrated signal by activating at least one counter (IF1, IF2) is generated and represents a counter reading, where the first and the second threshold value in each case a predetermined meter reading to be reached is true. 4. The method according to any one of the preceding claims, the motion sensor being a second sequence of Zu input pulses containing sentence information  testifies characterized in that each input pulse of first pulse follow by charging a capacitor (C) and each input pulse of the second pulse train by activating at least one counter (IF1, IF2) is integrated. 5. Circuit arrangement for signal processing for one active motion sensor, the at least one first Sequence of Ons containing motion information gear pulses generated, characterized in that at least one integral rende filter circuit is provided with which everyone Input pulse of a pulse sequence integrated and a zuge ordered output pulse generated for a period of time in which the integrated signal after exceeding a predefinable first threshold value above a predeterminable second threshold value, so that the Output pulse compared to the input pulse a time che delay. 6. Circuit arrangement according to claim 5, characterized in that the integrating filter circuit an analog filter with a capacitor (C) and at least one current source (I1, I2) points to charge the capacitor (C) and Generation of the integrated signal with the input pulse can be applied, the first and the second threshold value in each case by a predetermined, voltage drop across the capacitor (UP_THR, LO_THR) is determined.   7. Circuit arrangement according to claim 6, characterized in that a first and a two te power source is provided, wherein to achieve a largely linear course of the integrated Signals the first current source (I1) the capacitor (C) with a constant first current and the second current source (I2) through the input pulse is struck. 8. Circuit arrangement according to claim 5, characterized in that the integrating filter circuit a digital filter with at least one Counter (IF1, IF2), which for activation with the input pulse can be acted upon, the inte grated signal represents a counter reading and first and second threshold values each by one predetermined meter reading to be achieved is.