DE19751740A1 - Integrated electronic circuit manufacturing method, e.g. for CMOS BiCMOS - Google Patents

Abstract

The method involves forming an insulation groove (7a,7b,7c) in the region of a main surface of a substrate (1). The grooves insulate adjacent active elements in the substrate. An insulation material is then applied. The insulating material (9) is etched away down to the substrate in at least one region (13) from at least an insulation groove. Next, in regions in which the insulation material is etched away, second insulation grooves (14) are formed by selectively etching away the substrate. Finally these insulation grooves are filled with an electrically insulating material (15).

Description

The invention relates to a method for producing a integrated electrical circuit.

With integrated electrical circuits, it is known that In addition to the first isolation areas, they also have additional isolas tion areas, the further insulation areas through isolation trenches that go deep into the substrate urge to be formed.

In a known method, the deep isolation trenches are etched so that they first penetrate an insulation layer made of SiO ₂ and then several areas of the semiconductor substrate (RH Havemann, IEDM 1987, pp. 841-843). The insulation layer was manufactured according to a LOCOS process. The additional isolation trenches have been shown there as a possible variation of the circuit. Special advantages of these isolation trenches were not explained here.

It has also been proposed (see T. Park et al. IEDM 1994, pp. 675-678) to generate an isolation structure from SiO ₂ by means of a LOCOS process and then to etch isolation trenches in the existing isolation structure which are caused by the SiO ₂ penetrate into an underlying silicon semiconductor substrate. Then the isolation trenches are filled with an isolation material. This process is a combination of a LOCOS process and deep trench etching. This method also provides for the active area of field effect transistors to be protected from oxidation by the application of a silicon nitride layer. The silicon nitride layer also serves as a stop layer for the planarization step that takes place after the second isolation trenches have been filled.

In a LOCOS process, the insulation structure can be targeted removal of a non-oxidizable material det, that with the help of an arrangement of Isolati insulation mask defining structure. The insulation structure is then replaced by local thermi cal oxidation formed. This works a structured deck layer as an oxidation mask. At the local thermal oxi dation becomes the one not covered by the structured cover layer Part of the semiconductor layer to form the insulation structure through oxidized. This creates sub-areas of struktu rated semiconductor layer, each by the Isolati ons structures are separated.

The LOCOS process can also be carried out in such a way that With the help of the insulation mask, both the top layer and the Semiconductor layer are etched. The local thermal oxide tion to form the isolation structures then takes place on the Surface of the substrate.

In an STI (shallow trench isolation) process, the Trenches etched into the substrate using an etching mask  then filled up with insulating material.

The known methods require a large number of individual ones Process steps to make a semiconductor structure with different realizing deep trenches.

Furthermore, an undesirable topology level arises that leads to egg leads to a bend in the gate electrode. This is the Danger of using a photolithography process line width fluctuations occur.

The production of the insulation structure according to the LOCOS process is also associated with the disadvantage that a wider Transition area between field oxide and gate oxide forms. The This transition area is called because of its typical profile Called bird's beak. A disadvantage of the bird's beak is that it grows into the active transistor area and so convert valuable active area into inactive field oxide areas delt.

The invention has for its object the disadvantages of To overcome the state of the art. In particular, a poss The simplest and most reliable manufacturing process an integrated electrical circuit can be created. The integrated electrical circuit produced should be possible have the most effective insulation structures.

According to the invention, this object is achieved by a method for producing an integrated electrical circuit,

• - In the area of a main surface of a substrate  first isolation trenches are created that are adjacent isolate active elements in the substrate,
• - where an insulation material is applied,
• - in which subsequently the insulation material in little at least part of the first isolation trenches up to is etched away from the substrate,
• - where after that in areas where isolation material was etched away, second isolation trenches by selectively etching away the substrate the, and
• - The second isolation trenches with an electrically insulating material the.

The invention thus sees a combination of different pros steps ahead. The sequence shown here corresponds to Sequence of process steps in a particularly preferred one Embodiment of the method according to the invention. The Erfin However, the order also includes a different order of the individual process steps.

According to one embodiment of the invention, a sub strat, which is preferably a monocrystalline silicon wafer is a dielectric layer and a semiconductor layer upset. Instead of the semiconductor layer, a other conductive layer can be applied.

First isolation trenches are created on the substrate. The Isolation trenches can be created so that a distance left between individual gate electrodes of the circuit  is what happens, for example, that targeted Be areas of the substrate are etched away.

The structured semiconductor layer is used to form the ak tive elements doped.

The isolation trenches are used in a further process step filled with an insulation material, the type of filling process and the generation of the insulation material as desired are. The fill level is so great that electrically active Elements on their top surface with the insulation mat rial are covered.

It is particularly advantageous that the isolation trenches in the loading range of the gate electrodes at least up to the height of the upper edge of the semiconductor layer with the insulation material are filling.

After filling the isolation trenches, the isolation mat targeted etching away in some areas. This etching away continues until these areas There is no insulation material in the substrate.

Then the substrate is removed in these areas to the To allow formation of second isolation trenches.

Then the second isolation trenches with a electrically insulating material filled. The electrically iso lating material can have a different chemical composition than that for filling the first isolation trenches  have turned insulation material. In particular it is possible, a particularly flowable electrically insulating Use material. Increased fluidity of the elec trisch isolating material can by suitable chemical Additives can be achieved. The electrically insulating material can also contain chemical additives that Ga Teoxidation were affected. The advantageous Variabi lity of the chemical composition of the electrical isolie Material results from the fact that the gate oxidation before abge the application of the electrically insulating material is closed. In addition, the lower area is the gate electrode trode surrounded by the insulation material and so in front of one chemical impact through the electrically insulating mate rial protected.

The inventive method can be particularly simple cher and expedient way so that at least part of the second isolation trenches using a Mask, for example a planarization mask becomes. This can preferably be done so that a mask is set, which is designed as a paint mask. It is expedient that areas of the inte circuit covered by the mask, and that an etching process is then carried out. With the etching pro zeß is preferably an oxide or silicon um etching process.

Self-adjusted isolation structures, where the second Isolation trenches compared to the first isolation trenches can be directed in a particularly simple and advantageous  ter way can be realized in that the mask on a side flank of the insulation material is aligned.

A particularly good positioning of the second insulation level ben can be achieved in that the distance between the Mask and the side flank of the insulation material in the essentially a distance between two adjacent seitli Chen flanks of the insulation material corresponds.

Preferably, the distance between the mask and the lateral flank of the insulation material 0.2 µm to 3 µm.

It is particularly advantageous to carry out the method in such a way that after the second isolation trenches with the electrical insulating material have been filled and planarized upper area of the gate electrode is applied.

An expedient embodiment of the method stands out characterized in that the upper region of the gate electrode is common is structured with the semiconductor layer. This enables light a larger process window for oxide planarization. In addition, a parasitic corner or Kan Avoid ten effect on the upper edge of the trench. The parasitic "Corner" effect, which in the from IEDM 1994, pp. 671-674 be known process occurs, can not be a leg the electrical field distribution.

The upper part of the gate electrode can have any shape exhibit. However, it is particularly advantageous to do so shape that he laterally over the insulation structure  extends. Extending the top of the gate electrode about the insulation structure is appropriate because on this Way who further improves the insulation properties that can.

In this way, the upper part of the gate electrode can be called Ga serve te line. An embodiment of the upper part of the Gate electrode as a gate line has the particular advantage that in a manufacturing process where the structuring the lower and the upper part of the gate electrode together done with the same gate mask, the need for a se separate process step for the production of the gate line ent falls.

The invention also relates to an integrated electrical cal circuit, in which the upper region of the gate electrode a first transistor with at least one differently doped th gate electrode of another MOS transistor electrically connected is.

The upper area of the gate electrode can be made of any Material. However, it preferably consists of the same material as the lower area of the gate electrode. This has the advantage that with a final planari tion process, which is preferably a chemical mechanical planarization is a high selectivity of the removal process can be achieved. Besides, will the dry etching used to structure the gate electrode process facilitated by the homogeneous structure of the gate electrode tert and the selectivity towards the thin gate dielectric  cum increased.

Polycrystalline is suitable as the material for the gate electrode silicon is particularly good.

Through the isolation structure or the isolation structures the neighboring transistors in the substrate become each other isolated.

It is advisable to carry out the procedure in such a way that - after the second isolation trenches with an electrical insulating material - a planarization lacquer is deposited, and that there is then an etching.

The inventive method is suitable for both Iso lation trenches with a shallow depth as well as with a great depth of up to 500 nm, for example.

It is particularly advantageous that the selective etching away of the Substrate until the second isolation trenches up to a doped layer located in the substrate pass.

It is appropriate that the selective etching away of the substrate until the second isolation trenches up to egg ner insulation layer in the substrate are sufficient. In this way it is particularly possible to isolati to improve on properties so that a complete electrical insulation of different parts of the in tegrierte electrical circuit is achieved against each other.  

This can result in high electrical voltages in some areas are present without this causing sensitive electrically active Elements are affected.

Other advantages, practical training and special units of the invention emerge from the subclaims and the following presentation of preferred embodiments play with the drawings.

From the drawings shows

Fig. 1 a cross section through a substrate with n and p do oriented troughs 2, 3 and a semiconductor layer 5

The substrate Fig. 2 shown in Fig. 1 after the etching of the first insulating trenches 7 a, 7 b, 7 c,

Fig. 3 shows a cross section through the substrate after filling the isolation trenches 7 a, 7 b, 7 c,

Fig. 4 is a cross-sectional ke through the substrate after application of a serving for global planarization Lackmas,

Fig. 5 shows a cross section through the substrate after the etching of the substrate surface,

Fig. 6 shows a cross section through the substrate after the etching of the second isolation trenches 14,

Fig. 7 shows a cross section through the substrate after filling the second isolation trenches 14 with an electrically insulating material 15 and planarization of a planarization resist 16,

Fig. 8 shows a cross section through the substrate after the etching of the electrically insulating material 15,

Fig. 9 shows a cross section through the substrate after separating from the upper region 17 of the gate electrode

Fig. 10 is a plan view of the substrate after patterning of the gate level, and

Fig. 11 shows a cross section through the substrate with isolation trenches 14 , which extend to an insulation layer 1 b located in the substrate.

On a substrate 1 , a dielectric layer 4 , a semiconductor layer 5 , preferably made of silicon, forming the lower region of gate electrode, and a hard mask 6 are first applied over the entire area (see FIG. 1). The substrate 1 contains, for example, a monocrystalline silicon wafer. The dielectric layer 4 serves in the finished MOS transistor as a gate dielectric. The dielectric layer 4 is preferably formed by the thermal oxidation of a semiconductor material. The dielectric layer 4 can, however, also be produced by a deposition method such as CVD (Chemical Vapor Deposition). The dielectric layer 4 can be made of any dielectric material. For example, the dielectric layer 4 can also be a nitride layer. An integration in the course of the process can be realized particularly easily if the dielectric layer 4 is formed by SiO ₂ . The thickness of the dielectric layer is 1.5 nm to 20 nm, with a layer thickness of less than 5 nm being preferred. It is particularly advantageous if the dielectric layer has a thickness of 1.5 nm to 3.5 nm.

The semiconductor layer 5 , which in its structured state forms the so-called bottom polySi, that is to say a lower region of gate electrodes, consists of polycrystalline or amorphous silicon of 50 nm to 400 nm thickness which is deposited over the entire surface.

The hard mask 6 serves as a stop layer for a chemical mechanical planarization (CMP) of the insulation structure and is formed by deposition of a nitride such as Si ₃ N ₄ in a chemical vapor deposition (CVD) process. The thickness of the hard mask is preferably 50 nm to 200 nm.

By means of an n-well mask, not shown, an n-doped well and channel region 2 and a p⁺-doping of the semiconductor layer 5 , that is, the lower region of a gate electrode of a PMOS transistor, are formed by implanting ions in succession. During the implantation of phosphorus with energies in the range from 100 keV to 500 keV and preferably 200 keV to 250 keV and a dose in the order of 10 ¹² at / cm ² to 10 ¹³ at / cm ^2, the doping of the n-doped wells - And channel area 2 take place, the pierung-doping by implantation of boron with low energies, preferably in the range of 5 keV and a dose of the order of 5 × 10 ¹⁵ at / cm ² exactly in the semiconductor layer 5 , that is preferably carried out in the gate silicon.

After removing the n-well mask ("lacquer stripping"), the process is repeated for the NMOS transistor. For this purpose, a p-doped well and channel region 3 and an n⁺-doping of an n⁺-doped region of the semiconductor layer 5 , that is to say the lower region of a gate electrode, are now in succession by means of a p-well mask (not shown) by implantation of ions an NMOS transistor (so-called Gate-PolySi doping). While the p-doped well and channel region 3 is formed by implantation of boron with energies in the range of 250 keV and a dose in the order of magnitude of 1 × 10 ¹³ at / cm ^2, the channel implantation with boron takes place at one energy of 100 keV and a dose of 3 × 10 ¹² at / cm ² . By implanting arsenic at an energy of 60 keV to 100 keV and a dose of the order of 5 × 10 ¹⁵ at / cm ² , the semiconductor layer 5 is n⁺-doped in the region of the NMOS transistor.

A hard mask 6 is subsequently defined using conventional photolithographic process steps (not explicitly shown) (see FIG. 2). With the help of an anisotropic multi-stage dry etching process, for example first with Cl ₂ and then with a gas mixture of HBr, Cl ₂ , O ₂ and He, the hard mask 6 and subsequently the semiconductor layer 5 , the dielectric layer 4 and the substrate 1 are etched ( FIG . 2). In accordance with the mask layout, flat isolation trenches 7 a, 7 b, 7 c with different widths w _a , w _b , w _c and active regions 8 of the future MOS transistors are formed.

The side walls of the substrate 1 and the side walls of the semiconductor layer 5 are then thermally oxidized (not shown), a wide transition region being formed between the semiconductor layer 5 and the dielectric layer 4 . Because of its typical profile, this transition area is referred to as a bird's beak.

An insulation material 9 is then deposited on the structure in a thickness of 200 nm to 800 nm ( FIG. 3). The insulation material 9 , for example SiO ₂ , is preferably deposited by a CVD (Chemical Vapor De position) method.

The wide isolation areas 7 a and other non-etching oxide areas (not shown) are covered with a resist mask 10 ( FIG. 4). The distance 11 of the resist mask to the etched edge of the substrate 1 is chosen so that a sufficient distance 12 a between the resist mask 10 and the face mask 10 facing flank of the insulating material is formed as 9 . The distance 12 a thus defined preferably corresponds approximately to a distance 12 b between adjacent edges of the insulation material. As a result, it is sufficient that after application of an anisotropic oxide etching ( FIG. 5), for example with NH4 and HF, the surfaces 13 of the substrate 1 are exposed. Then the second, deep isolation trenches 14 are etched selectively to oxide using anisotropic Si etching — for example with a gas mixture of HBr, Cl ₂ , O ₂ and He ( FIG. 6).

The side walls of the isolation trenches 14 can be thermally oxidized (not shown) and / or optionally also doped. On this structure, as far as it is expedient because of the aspect ratio, a flowable planarization oxide (for example Flowable Oxide, FOX, from the manufacturer Dow Corning) is deposited and flowed ( FIG. 7). The planarization oxide is equal to the ren Isolie and is translated to fill the second isolation trenches 14 te electrically insulating material 15. Of course, other electrically-insulating material 15 may be used. However, the use of a flowable Planari sierungsoxids with the particular advantage that it fills the second isolation trenches 14 in a simple and reliable manner.

It is particularly advantageous to apply the electrically insulating material 15 in a thickness which is so large that there is a coherent surface which lies above the active regions 8 of the MOS transistors. Thus, who covered the active areas 8 of the MOS transistors. In this case, subsequent planarization is particularly easy to carry out. So it is also possible to do without chemical-mechanical polishing.

To further improve the planarization, a planarizing varnish 16 is deposited with a long planarization length of preferably at least 200 μm (for example Accuflo from the manufacturer Allied Signal). The planar surface thus produced is then etched back to the upper surface of the semiconductor layer 5 using a conventional anisotropic dry etching process, for example using an etching gas consisting of CHF ₃ , NF ₃ and Ar, the process etching oxide and lacquer with the same etching rate ( FIG . 8).

Then an entire area 17 of the gate electrode is deposited over the entire surface (see FIG. 9), which can be done, for example, by a CVD process or by sputtering. The upper region 17 of the gate electrode is also referred to as the top gate electrode.

Then the lower region 5 and the upper region 17 of the gate electrode are structured together by means of conventional photolithographic process steps of the gate phototechnology, so that excess silicon of the semiconductor layer 5 on the active regions 8 is removed. Fig. 10 shows a plan view of the resulting structure.

Then the integrated electrical circuit is on known way through finishing steps (back-end Process) such as the formation of an intermediate oxide, for example BPSG, contact hole etching, and application of a metallization completed. For this purpose, the known methods steps are used.

Fig. 11 shows an embodiment in which an SOI (Silicon On Insulator) substrate is used an electric circuit produced in fiction, modern way. The SOI material consists of a semiconductor wafer (support wafer) 1 a, a silicon layer 1 c, which is also referred to as an SOI layer because of its location on an insulator, and an oxide layer 1 b, which is also referred to as a buried oxide . The process control is largely identical to the procedure described with reference to FIGS. 1 to 10 for a conventional semiconductor substrate, but the etching process for the second, deep trenches 14 on the oxide layer 1 b stops. The side wall of the trench can be doped, for example, by diffusion out of in situ doped polycrystalline silicon. The region 3 b highly doped by p⁺ diffusion lies between the p-doped well 3 and the electrically insulating material 15. Electrical contact can be made via the well 3 .

Even with this structure, the finishing can be done on known Way through finishing steps (back-end process) like that Formation of an intermediate oxide, for example BPSG, contact hole etching, and applying a metallization. Also the known method steps can be used here become.

The proposed method is self-adjusted second, deep isolation structure in a simple way reali siert. This is achieved in that the global Planarization necessary oxide etching silicon Substrate areas are exposed. In this exposed Deep trenches are etched into substrate areas. The rest Oxide also serves as a hard mask for the anisotrop  pe Silicon dry etching of the deep trenches. Also be the electrical properties of the active components in the Compared to conventional shallow trench isolation (STI) significantly improved.

In principle, the method can also be used with a conventional one Shallow trench isolation (STI) process can be applied.

Claims (13)

1. Method for producing an integrated electrical circuit,

• - In the area of a main surface of a substrate ( 1 ) first isolation trenches ( 7 a, 7 b, 7 c) who who isolate the adjacent active elements in the substrate,
• - in which an insulation material ( 9 ) is applied,
• - in which the insulation material ( 9 ) is etched away in at least one region ( 13 ) from at least one of the first isolation trenches ( 7 a, 7 b) to the substrate ( 1 ),
• - Thereafter in areas ( 13 ) in which the insulation material ( 9 ) has been etched away, second isolation trenches ( 14 ) are formed by selective etching away of the substrate ( 1 ), and
• - In which the second isolation trenches ( 14 ) are then filled with an electrically insulating material ( 15 ).

2. The method according to claim 1,

• - In which a dielectric layer ( 4 ) and a semiconductor layer ( 5 ) are applied to the main surface of the substrate ( 1 ),
• - In which the semiconductor layer ( 5 ) in the formation of the first isolation trenches ( 7 a, 7 b, 7 c) is structured in such a way that the structured semiconductor layer ( 5 ) comprises a plurality of subregions formed by the first isolation trenches ( 7 a, 7 b, 7 c) are separated from one another,
• - in which the structured semiconductor layer ( 5 ) is doped in areas in which MOS transistors are formed with source, a gate electrode, drain and with a channel,
• - In which the insulation material ( 9 ) is applied in a thickness which is so large that the gate electrodes of the MOS transistors are covered by the insulation material ( 9 ).

3. The method according to claim 2, characterized in that the thickness in which the insulation material ( 9 ) is applied is so large that the insulation trenches ( 7 a, 7 b, 7 c) in the region of the gate electrodes at least up to the height of Top edge of the semiconductor layer ( 5 ) are filled with the Isolationsmateri al. 4. The method according to any one of claims 2 or 3, characterized in that after the second isolation trenches ( 14 ) with the elec trically insulating material ( 15 ) have been filled and optionally planarized, an upper region ( 17 ) of the gate electrode is applied. 5. The method according to claim 4, characterized in that the upper region ( 17 ) of the gate electrode is structured together with the semiconductor layer ( 5 ). 6. The method according to any one of claims 1 to 5, characterized in that the second isolation trenches ( 14 ) are formed by first applying a mask ( 10 ) and then performing an etching process. 7. The method according to claim 6, characterized in that the mask ( 10 ) on a side flank of the insulation material ( 9 ) is aligned. 8. The method according to claim 7, characterized in that the distance ( 12 a) between the mask ( 10 ) and the side flank of the insulation material ( 9 ) substantially a distance ( 12 b) between two adjacent side flanks of the insulation material ( 9 ) corresponds. 9. The method according to any one of claims 7 or 8, characterized in that the distance ( 12 a) between the mask ( 10 ) and the side flank of the insulation material ( 9 ) carries 0.2 µm to 3 µm. 10. The method according to any one of claims 1 to 9, characterized in that after the second isolation trenches ( 14 ) with an electrically insulating material ( 15 ) have been filled, a planarization varnish ( 16 ) is deposited. 11. The method according to any one of claims 1 to 10, characterized in that the selective etching away of the substrate ( 1 ) until it follows until the second isolation trenches ( 14 ) extend to a doped layer located in the substrate ( 1 ). 12. The method according to any one of claims 1 to 10, characterized in that the selective etching away of the substrate ( 1 ) until it follows until the second isolation trenches ( 14 ) up to an insulating layer ( 1 b) located in the substrate ( 1 ) pass. 13. The method according to any one of claims 1 to 12, characterized in that the electrically insulating material ( 15 ) is applied in a thickness which is so large that there is a coherent surface which above the active areas ( 8 ) MOS transistors.