DE19751740B4 - Process for the production of an integrated circuit with different deep isolation trenches - Google Patents

Process for the production of an integrated circuit with different deep isolation trenches Download PDF

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Publication number
DE19751740B4
DE19751740B4 DE1997151740 DE19751740A DE19751740B4 DE 19751740 B4 DE19751740 B4 DE 19751740B4 DE 1997151740 DE1997151740 DE 1997151740 DE 19751740 A DE19751740 A DE 19751740A DE 19751740 B4 DE19751740 B4 DE 19751740B4
Authority
DE
Germany
Prior art keywords
production
integrated circuit
isolation trenches
deep isolation
different deep
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE1997151740
Other languages
German (de)
Other versions
DE19751740A1 (en
Inventor
Udo Schwalke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE1997151740 priority Critical patent/DE19751740B4/en
Publication of DE19751740A1 publication Critical patent/DE19751740A1/en
Application granted granted Critical
Publication of DE19751740B4 publication Critical patent/DE19751740B4/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
DE1997151740 1997-11-21 1997-11-21 Process for the production of an integrated circuit with different deep isolation trenches Expired - Fee Related DE19751740B4 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE1997151740 DE19751740B4 (en) 1997-11-21 1997-11-21 Process for the production of an integrated circuit with different deep isolation trenches

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE1997151740 DE19751740B4 (en) 1997-11-21 1997-11-21 Process for the production of an integrated circuit with different deep isolation trenches

Publications (2)

Publication Number Publication Date
DE19751740A1 DE19751740A1 (en) 1999-06-02
DE19751740B4 true DE19751740B4 (en) 2005-03-10

Family

ID=7849492

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1997151740 Expired - Fee Related DE19751740B4 (en) 1997-11-21 1997-11-21 Process for the production of an integrated circuit with different deep isolation trenches

Country Status (1)

Country Link
DE (1) DE19751740B4 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004022781A1 (en) * 2004-05-08 2005-12-01 X-Fab Semiconductor Foundries Ag SOI slices with MEMS structures and filled isolation trenches defined cross section

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5411913A (en) * 1994-04-29 1995-05-02 National Semiconductor Corporation Simple planarized trench isolation and field oxide formation using poly-silicon
US5504033A (en) * 1992-08-26 1996-04-02 Harris Corporation Method for forming recessed oxide isolation containing deep and shallow trenches
US5536675A (en) * 1993-12-30 1996-07-16 Intel Corporation Isolation structure formation for semiconductor circuit fabrication
US5683932A (en) * 1994-03-15 1997-11-04 National Semiconductor Corporation Method of fabricating a planarized trench and field oxide isolation structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5504033A (en) * 1992-08-26 1996-04-02 Harris Corporation Method for forming recessed oxide isolation containing deep and shallow trenches
US5536675A (en) * 1993-12-30 1996-07-16 Intel Corporation Isolation structure formation for semiconductor circuit fabrication
US5683932A (en) * 1994-03-15 1997-11-04 National Semiconductor Corporation Method of fabricating a planarized trench and field oxide isolation structure
US5411913A (en) * 1994-04-29 1995-05-02 National Semiconductor Corporation Simple planarized trench isolation and field oxide formation using poly-silicon

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
BRYANT, A. et al.: Characteristics of CMOS Device Isolation for the ULSI Age IEDM 1994, pp. 671-674 *
HAVEMANN, R.H. et al.: An 0.8 um 256 K BiCMOS Sram Technology, IEDM 1987, pp. 841-843 *
PARK, T. et al.: Self-Aligned LOCOS/Trench (SALOT) Combination Isolation Technology Planarized by Chemical Mechanical Polishing IEDM 1994, pp. 675- 678 *

Also Published As

Publication number Publication date
DE19751740A1 (en) 1999-06-02

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8127 New person/name/address of the applicant

Owner name: INFINEON TECHNOLOGIES AG, 81669 MUENCHEN, DE

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee