DE1947437C - Circuit arrangement for scanning and controlling the transmission of information between a memory system and input and output devices of data processing machines - Google Patents

Description

The invention relates to a circuit arrangement for scanning and controlling the transmission of information between a memory system and lines which are connected to input and output units of an electronic data processing system and which can transmit information at different speeds and different transmission modes via a transmission channel which comprises a high-speed memory, in which a first group of memory positions ι ο is present, which are assigned to the individual transmission lines for collecting information.

Similar circuit arrangements have already been used in the known telex switching systems. Here, a single-character memory is generally provided for each subscriber line, with which it is possible to effect the reception or transmission of the groups of pulses combined into teleprinting codes regardless of the transmission speed. The system or the memory can be designed in such a way that the storage takes place at a certain first speed and the extraction takes place at a second speed. So is z. Example, in German Auslegeschrift 1,275,088 has become known, such a circuit arrangement, which is characterized in that the lines each having a one-bit Speichcr are completed, the central memory for each line a, ^ ser dedicated memory cell of predetermined bit capacity aufwe 'oi and a device arranged between the one-bit memory and the memory cells can be interconnected in cyclic sequence at the same time with a one-bit memory and the associated memory cell. that this device temporarily takes over the first bit alone when a message is entered and later the next bit stored in the one-bit memory and any bits already stored in the memory cell, checked for their number and then in each case with each other for so long the memory cell is stored until it is filled, and then they are transferred together to the part of the central memory allocated to the relevant message and, when a message is issued, first a number of bits corresponding to the bit capacity of the memory cell from the zen-. occurred memory and later temporarily takes over all bits possibly still stored in the memory cell, checked for their number and then separately from one another the next bit to be output of the message in the one-bit memory and any remaining bits in the Storage cell stored until it is emptied. and that a computer takes over and processes the message header and the message end of the messages to be transmitted and the bits relating to the other control commands at the same time as the input or output of these bits.

However, this circuit arrangement has the disadvantage that the security of transmission is sufficient for telex memory switching systems not for data-processing machines where particularly high precision information monitoring is required.

In addition, the introductory document IBM TELE-Processing, Systems and its Application, IBM Form 74 913-1, June 1964, pp. 37 to 49, made known a programmed data transmission control unit that can transmit data at different speeds and different transmission modes over a transmission channel. For this purpose, the transmission channel is equipped with a high-speed memory in order to collect the bits that are transmitted from the assigned line in the memory locations assigned to the individual lines.

However, this programmable data transfer control unit has the disadvantage that it can only handle up to 40 half-duplex lines and it is not possible to replace the Control fields standing control information to use more lines. An extension of this programmed data transmission control unit would only be possible if the memory space and the logical network would expand significantly.

The invention is therefore based on the object of a circuit arrangement for scanning and for Control the transfer of information between a storage system and lines connected to input and output units of an electronic data processing system are connected to create the it makes it possible that when the number of lines to be operated is increased, only the corresponding lines Need to be exchanged control information in the memory, so that in particular the disadvantages the latter programmable data transfer control unit can be avoided.

The inventive solution to the problem is that in the high-speed memory there is a second group of memory positions containing the control information for defining all scanning features which contains lines which Ai sample operation depending on during a sample operation, which is subdivided into sample cycles is scanned by the transmission speed and the transmission mode and that at the beginning of the overall scan, a group control address register contains the address of the first control information records in the high-speed memory, which is used for the parallel transmission of the control information with a Group register stages is connected and that a sampling cycle has an elementary step during which There is access to the second memory position, which is followed by further elementary steps follow, during which the lines with common transmission modes and speeds are scanned.

The advantage of the circuit arrangement according to the invention is that, on the one hand, there is a very high degree of flexibility with regard to the possible transmission speeds of the lines and, on the other hand, a very large number of lines, e.g. B. up to 500 lines at a transmission speed of 50 bauds, can be controlled with little circuitry. In addition, when the circuit arrangement is modified, no circuit changes need to be made, since the change can be made solely by changing the group control words and line control words in the memory. This is achieved in particular by the fact that there is a group control address register in which the address of the first control information is entered at high speed and which is connected to a group of register levels for the parallel transmission of the control information, and the scan

I 947 437

cycle has an elementary step, during which There is access to the second memory position, which is immediately followed by further elementary steps, during which the lines are scanned with common transmission modes and speeds will.

Developments of the invention are in the subclaims marked.

Embodiments of the invention will now be described in more detail with reference to the drawings. It indicates

F i g. 1 schematically shows the general structure of an exemplary embodiment,

F i g. 2 the structure of a group control word, FIG. 3 the structure of a line control word,

F i g. 4 shows the composition of a sampling cycle in one embodiment;

F i g. 5 A is the segment subdivision of a scanning cycle,

FIG. 5B shows the structure of the segments shown in FIG. 5A to appear,

F i g. 6 the logical arrangement of the line scan control,

F i g. 7 the device for series-to-parallel conversion of characters and

F i g. 8 schematically the switching unit for the data transmission between the high-speed memory and the central unit

F i g. 1 shows the data transmission control unit 1, which mainly consists of the central unit 2 of a data processing system This central unit includes the characteristic elements, such as read-only memory, Main memory, selection channel and multiplex channel. The selection channel is connected to fast input-output units and can be shared with others Data processing systems connected with the aid of the adapter 4 for a channel-to-channel connection will. The multiplex channel is connected to less fast input-output units and controls the transmission channel 3 on one of its sub-channels.

The transmission channel (COC) controls the transmission circuit with the aid of adapter units S. Each of these adapter units controls a group of lines that work in different modes and at different speeds. Operation can be either synchronous with clock pulses or asynchronous with »start-stop« transmission. If the transmission lines are used over relatively long distances, they are always connected to the adapter units via modems 6.

The transmission channel comprises a high-speed memory HSS (FIG. 6), which enables the storage of data which come from the transmission lines or are placed on them. A queue register is used to temporarily store the data transferred from the buckle memory to the multiplex channel MPX.

The problem with the scanning process consists in receiving or sending data over different groups of lines which carry out the transmission in different operating modes and at different speeds. Two types of control words u stored in the high speed memory are used for this purpose. First, the group control word GCtV is used, which, for example, can read 80 bits in the memory and in one example in FIG. 2 is shown. The function of the GCW is to control the scanning operation of a group of lines with the same characteristics as will be described in more detail later. The GCW can be different, depending on whether the lines transmit in synchronous or asynchronous mode. If the lines transmit in synchronous mode, this is indicated by certain positions of the GC W which are in front of the actual message. In asynchronous operation these are

Positions not available, but a binary bit position indicates that the stop bit is 1, S times as long like the normal bit. . "

It can happen that the device has to carry out the transmissions on lines that end with a

Working speed that does not match all other lines. In this case, a so-called "line oscillator" LOSC allows generally in a known way to receive the information corresponding to the show speed · on the line and the transfer of this information to the memory in a matching speed Certain positions of the GCW show then this transfer, which with the WSC is working

First of all, it is assumed that there is only one type of line consisting of η lines that transmit at a rate of χ bits / sec. Because of the distortion occurring on the line, the line must be scanned several times during the transmission of a bit, and the number of these scanning operations N is used either as a clock cycle on the sending side or as a scanning cycle on the receiving side. Thus, the line must be scanned xJV times per second will.

The lines must therefore each -J ₀ - lake or

10 ⁶

^ are scanned. In other words, the

total sampling time of all lines is equal to 10 ⁶
- μβεα It is now assumed that t (μβεο)

is the scan time of each line at each step; d. H. the basic cycle time during which a line can send or receive as the line scan operation accesses the line control word in high-speed memory as shown in the explanation below. This time period or step t is given by a time base generator which controls all registers. While

an entire scan must therefore take ^ steps. When the number η of the lei-V to be scanned is dh

is smaller than V-, ie ^

then each line can be scanned xN times per second. In this case the scan proceeds as follows:

The first step is the access operation to the. Group control word GCW in the high-speed memory. The content of the GCW is used to define all of the scanning features as described below. After the first access step to the GCW , η lines are scanned in the following η steps, each scanning of a line corresponds to the access to the corresponding line control word LCW. This leaves m-1 "spaces" in which no line is scanned. These spaces are used to interrupt the process, as described below. It can happen that this number

of spaces is too large, ie that the capacity of the system is not used sufficiently (the number η of lines could be higher), or the Afc number of samples N pte bits and thus the accuracy of the transmission can be increased. s If in the above calculation it is assumed that

that the number - ~ - is less than the number

of the lines n. then this means that the number of scanning operations N per bit has been selected to be too large and that it must be reduced. Of course, a minimum number of scans per bit is required, thereby defining a maximum number of lines which, if exceeded, require more than one device to be used.

Up to now, only the case was considered in which lines with the same characteristics were used. The case will now be described in which different groups of lines with different characteristics are used. So z. B. some lines run in synchronous mode and others in asynchronous mode. On the other hand, lines define different groups that reach different adapters. In either case, the total sample becomes the smallest period in the chosen bet game. in which each line is scanned at least once, divided into several segments. A segment is part of the total air sampling. which comprises the necessary scanning steps between two successive line scanning operations where the lines have the highest scanning speeds. If z. B. there are two asynchronous line groups, of which one group must be scanned at one speed. which is twice as high as that of the other group, then the total scan is divided into two segments. The first group of lines _{to be scanned N 1} x, times per second. is scanned for each segment, ie twice during a total scan. The second line group is of course only sensed once *> during a total scan. These lines can be divided into halves over the two segments, or they can be collected over one segment, and the other segment comprises only the first learning group.

In short, the total scan is segmented so that the asynchronous lines are scanned JV ^ times per second {x _x is the number of bits per second of line L ₁ and N _{ the number of scan operations per bit). Things are completely different for the lines running in synchronous operation, which only require one scanning operation per bit. As a result alone, the entire scanning line of the lines running in synchronous operation must be divided into several segments SS.

When considering this subdivision into segments, a GCW is assigned to each line group that has the same characteristics within a segment and in a manner similar to that which referred to a &> line type. As already said, it can happen that a GCW controls only one TeH of the Leitge in a group which has several S

segment

are distributed. The following steps are bundled according to the scanning operation of the lines in the same group or a TeO of the group when the LCWs in the high-speed memory are addressed. Therefore, for each group or each part of a group of lines of a segment has only one GCW and a number of LCWs . It can happen that the eleventh number of steps in each segment flees is used.

As stated earlier, some lines need to be scanned multiple times during a whole scan, while others only need to be scanned once. Under this face, the liituflgsgfuppe is controlled by identical GCWs , which require repeated scanning. This arrangement can of course be implemented in two different ways. In the first case the same GCW is set to several different memory positions, and in the second case a memory position belonging to a GCW is queried several times during an overall scan. This second implementation requires the use of additional storage locations in main memory which contain words to control the GCWx. During the first step, the data in such a memory location indicates the address of the various GCWs . which are to be addressed later, and thus enable multiple access to the same GCW during an overall filling.

The distribution of the lines during a total expansion is based on the following examples emerged.

Example I.

SOO lines of the same class exceeded with a speed of 50 baud and, due to the line splitting, must be scanned IS times per bit, ie τ = 50 and N = 15 This results in scanning a line with _τ ' _ν = ^ s.

i.e. the total scan takes 1,335 ms. Assuming that a step is 1.875 then takes a total scan length \ l ^ ^m *

= 712 steps. As a total number of SOO lines was accepted, this number is sufficient. so that each line is scanned IS times per second can.

Fig. 4 next »step shows" sharing: A GCW occupied at the beginning of the total scan a step then prove SOOLCfTs the following 500 steps, each of erwihnten word s a Leiteng in übertnigungsprozea corresponds to the next 211 steps are spaces, for which no GCW or LCW int Schtteuspeicher HSS is available After step T "GCW" , the LCWs can also be set differently than in the selected example without changing the result with regard to the corresponding scanning of the lines.

If the addresses of the 500 lines are not in the same order as the corresponding GCWs, there will of course be interruptions in the order of the addresses.

Example 2

In this example different teaching classes are considered, namely:

100 SO-Baud-Lehungen, the iö »Start-Stop-Betneb running and requiring 21 samples per bit, 50 600 baud lines running in start-stop mode run and research 7 scans per Kt, and IO 4800-bit ^ ec-readings that run in synchronous operation and therefore require one scan per bit.

• 5708

The 5OBatid "L" kufigeti must be scanned

the 60Ö'Baud * lines so four times as often as the S

50 baud guidelines, and consequently the total ' sampling can be divided into four segments from the start, and the 600 baud lines are over each Segment and the 50 baud lines distributed only once ttbcr the entire scan. The one with 4800 bits Lines running in synchronous operation per second must, however, at least once per scan / cycle.

_{i.e. 4ftnn} s = 208.5 μ * can be sampled. The GE total scanning must therefore be divided into eight segments, each 119 µs long. In this case the 50 baud lines are only scanned once over the entire scan, the 600 baud lines are scanned every other segment, and the 4800 bit / s lines are scanned 8 times per total scan. Figures 5A and 5B show the distribution of the various steps that correspond to the GCWx and LCWs.

Fig. 5A shows the division of the total »5 palpation. If f = 1,875 μ $ the duration of a Sc 'rittes is. then includes the total scan

I ^ = 508 steps. These 508 steps need to be on

eight segments are distributed so that four 6-V-step segments alternate with four 64-step segments. The distribution of the steps mentioned is shown in FIG. 5B shown. The first segment comprises 63 steps. The first step is the GCW step. which controls the 10 lines with 4800 bits / s. Then there are the 10 GCWx (shown corresponding to these 10 lines, then the 600-baud lines. Which are controlled by a GCW , which is followed by 25 LCWs, which correspond to 25 lines below the 600-baud lines. The twelve 50- Baud lines can be set in such a way that a GCW comprising one step is followed by twelve steps with LCWx , which correspond to said lines. Thus, in the first segment 50 steps are occupied and 13 steps are free. In the following segment, for example, 13 If W- Step 3 sets the rren thirteen 50 baud lines, so that the 100 lines are distributed over the eight segments.This results in the following structure for the second segment: A step GCW controls the ten 4800 bits / s lines and then the corresponding ten LCW steps, a GCW step controls the 25 600 baud lines not distributed through the first segment, and then the corresponding 25 LCFF steps, a GCW controls the thirteen 50 baud lines and this line en corresponding thirteen LCW steps. This means that 51 steps are occupied and 13 steps are free in the second segment. This distribution is of course only used as an example. B. the 50 baud lines can also be distributed to every other segment, 4 h. 25 lines in every other segment. The same goes for the 600 baud lines. which can be distributed to one segment, ie 50 lines on one segment and (no line on the next segment. With other distributions the segments need of course not only comprise 63 or 64 steps, but can also comprise 80 or 47 steps, for example. Sometimes it may be desirable not to distribute a line group to each segment zn , since a step occupied by an OCW corresponds to every subgroup in a segment and it can be advantageous to use too many steps. The only rule to be observed is to be considered the fixed scanning speed by dividing the entire scanning into corresponding segments. The distribution of the lines to the segments depends on the number of lines distributed. The programmer can also determine two basic rules in the above example. I. The 600 baud lines must be scanned first tion must be divided into four segments or a multiple of 4. and 2. the lines operating in synchronous operation must then be scanned at a speed which results in more than one scan per bit, so that the total scanning must be divided into at least eight segments. In addition, the total scan can be divided into sixteen segments, thereby also using the steps provided for the GCWs.

The circuit arrangement for scanning the lines is described below with reference to FIGS. 2. 3 and 6 described. At the beginning of the overall scan, the group control address register (2t. Fig. 6) GCA R contains the address of the first GCW in the high-speed memory HSS. This GCW is retrieved in parallel from the high-speed file and on the in FIG. 6 shown register group 20. 22. 13. 24 given. When the GCIV is in the various registers, the first step is complete. F i g. Figure 2 shows that part 14 (from bit 31 to bit 40) contains the address of the first line or the data record adapter to be scanned first. This part 14 is via the line 28 in the in F i g. 6 data record adapter register (20) DSAR set. This register has access to the line to be scanned via line 34. From the in F i g. It can be seen from the GCW shown in FIG. 2 that the part 13 contains the address of the first LCW of the high-speed memory HSS , and this address is entered via the line 29 into the in FIG. 6 line address register (22) LAR shown is set. The register 22 then has access to the memory position which contains the first LCW , which corresponds to the first line to be scanned, which is determined by the content of the register 20. Part 11 contains the number of lines to be scanned or the number of lines LC> which is dependent on the GS W, and is given to the line number register (23) LCR , part 12 of the GCW contains the number of spaces and the line 31 is given to the register 24. The number of these spaces is only in the first GCW of the segment, since d ^; These steps can be used for an interruption at any point in time within this segment, as will emerge from the later description

In short, at the end of the first step, which corresponds to the first GCW in the segment, the number of lines to be scanned and the number of usable spaces are registered, and the position of the LCW, which corresponds to the first line to be scanned, is addressed and the first transmission line scanned- The address of the first line to be scanned is made up of the address of the adapter unit and the address of the line on this unit

209 626/312

During the dew step of the first GCW , the first line to be scanned has access to the corresponding LCW in the high-speed memory, and a data element is stored in the LC W and transmitted over the line. At the end of the ffstefi step of the LCW , the DSAR register 20-am is dialed further by a value so that the second line can be scanned. In the same way, the /.ΛΛ register 11 is advanced by one unit and forwards the address of the second LC W into the high-speed memory. Other · setts the LC Ä register 2.1 was switched back by one value. As already said, the content of these registers is changed under the control of a time base generator, the orund specification of which is step i $. The lines controlled by the first GC W continue to be scanned until the LCR controller reaches the value 0. At this point in time, the scanning control 27 advances the GC / 4 Ä register 21, which then points to the address of the second GCW of the first segment at high speed. The content of the GCW, ie the address of the first line to be scanned, of the corresponding LCW and the number of lines to be scanned is given to registers 20, 22 and 23 as above. It should be noted that the space register 24 is only loaded by the first GCW in the St. On the other hand, it can be switched back by one value at any point in time if a font is used that indicates an interruption and also shows <tn. that during the step there is access to the SchneTcpekher through the interrupt controller 55.

During the last GCW in the segment, register 25 is loaded via line 32 irrespective of the position of bit 9, which indicates the end of the segment. The aforementioned register 2 $ outputs a signal as the scanning controller 27. which says. that the empty spaces in the segment are to be reduced if the LCft-Rcgtster is at 0 3. If the LCÄ register

23 then is at 0 and the register 2S indicates the end of the φ segment, the / SCK let seer

24 switched back to 0. Its contents were the number of empty cineo eneen in the first GCW , minus the few interrupt operations used steps.

The return to 0 of the register 24 then indicates that the GOiÄ register must be increased by one. to get the address of the first GCW of the second segment za. During the scanning of each segment, this process then continues, so at the last GCW of the last segment, the register 26 is loaded with bit 7 of the GCW and thus the end of the total scan is indicated.This bit has the same function as bit 9 within the segment, but also states that the GCAR register must contain the address of the first GCW of the first segment winder so that a next full scan can begin.

Abs as described above, it is apparent that the same group can be addressed multiple of lines during a total scan, and additional Speieberpositionen can waden benatzt Dajt that the addresses of the to be addressed GC ^ s included, thereby enabling the addressing enter individual memory location. A specific, here ⁶ S not described exemplary embodiment of the invention comprises additional registers to which sent the content of the additional Speichnen will. In this exemplary embodiment, of course, a first step is assigned to the access to one of the additional memory positions in order to give the information contained therein to the corresponding registers. The following step is dedicated to accessing the first GCW identified in these registers and the process then continues as above.

The advantage of such an arrangement is that this arrangement allows the GCWs to be addressed in the high-speed memory HSS m of the type which is determined by the structure of the overall scan, and not in sequence, as is the case in the exemplary embodiment of the invention of PaIi.

in the description above were the circuits not explained in detail which address the scanning controller 27, since these consist of known circuits.

The individual steps involved in transmitting characters over a given line will be discussed below in connection with FIG. 7 Described.

First, assume that a transfer operation is to be performed. Bit 28 in the LCW of the line concerned is set to I (Fig. 3). which means that the data in the relevant memory position should be sent to the corresponding line. The character to be sent is in the memory part IS of the LCW. the buffer ADB. as shown in F1 g 3. According to the illustration in FIG. 7, the content of the ADB is set in parallel via line 39 into a shift register 38, which has an additional position directly under position I.

As already stated, a bit is only sent during a given number of scanning operations on this line before it is heard at regular intervals and thus determines the duration of the BH. This number NS occupies part 15 of the GCt / in F1 g. 2. Therefore, the content of register 38 does not change as long as the line does not have a view! is scanned by painting NS. During the subsequent scanning operations of the Leitaas »gt TeU 17 or SC of the LCW in FIGS. 3 and 7, the number of scanning operations carried out is displayed. With inflection aaf F i g. 7 will be scanning this! SC is continuously loaded into the register 40, but the line 41 returns the number to the part 17 of the LCW after the unit 42 has been advanced by the value 1. The sampling number SC is therefore incremented by 1 with each sampling operation. The output signal of the register 14 is also given to a comparator 43, which receives its other input signal from the part 15 of the GCW (Fig. 2) which indicates the number of sampling operations to be carried out the number of operations to be carried out, the comparator 43 sends a pulse via the initial scoring 45 to the shift register 46, which then shifts the content of the register 38 down by one position , shifted to position 0, the bit that was in position 2, position 1, etc. The output signal on line 45 of comparator 43 also prepares the timing 47 and thus envisages the transmission of the bit that art Position 0 in register 38

stood, via the line 48 and the output line 49, the bit in position 0 of the register 38 does not go through the gate circuit 50, which is only prepared when its input line Si carries a 1 pulse and thus indicates that a receive operation is in progress When the bit has been sent, the new contents of register 38 are passed on line 52 to part 18 (ABB) .

The operations described above continue in this way until the character of the LCW contained in part 18 has been completely sent. At the end

the character transmission is a one-bit, the g
When all the bits of the character have been transmitted over the line, the register 38 contains all zeros, which are preceded by the flag 1 in position 1. This arrangement is recognized by a system (nkht shown in the figure), which is the content of the transmission buffer TB . Fig . 3) or of the LCWiti part 18 of the LCW transmits, the content of the LCW was previously transferred to register 53, the so-called transmission buffer register TBR .

In connection with Table 1 and P i g. 7 described how a sign on the line is sent.

Table I.

0
0
0 Register 31 0
0
T
T
T
T
T 0
0
Ai
Ai
Ai
Ai
Ai 0
0
A ₄
A ₄
A ₄
A ₄
A ₄ 0
0
Ai
Ai
Ai
A ₃
Ai 2 1 bit 0
I.
0
0
0
0
0
0 0
T
Λ
0 0
Ai
T
T
T
T
T 0
A *
A _s
Ai
Ai
Ai
Ai 0
A ₃
A ₄
A ₄
A ₄
A ₄
A ₄ 0
A ₂
A ₃
A ₃
A ₃
Ai
A ₃ 2 i CB (TD 1 T - R.A.M A ₃ A ₂ 2 1 I. T 0
0
Ai
Ai
Ai
Ai
Ai (SI 1 T Ai A ₄ 4 2 1 Ai 0 0
0
i.
Αχ
Αχ
Αχ
Αχ 0 0 0
A ₁
A ₂
A ₁
A ₂
Ai
Ai 0
S.
Αχ
Αχ
Αχ
Αχ
Αχ 0 0 0
0 0 0
0 0 1
0 10
0 1 1
1 0 0
1 0 1 Αχ S. O O O O O O O 0 1 5 0 1 Ai A ₄ Ai A ₂ 0 0 I. A ₄ 0 Ai Ai 0 0 1 0

If it is assumed that the line is transmitting in the start-stop mode, the fact that the character begins with a start bit S , comprises 5 bits and ends with a stop, which is shown here as only one bit T for the sake of clarity further assume that five sampling operations are performed per bit.

At the end of a character there is an identifier bit 1. It is assumed that part TB of the LCW has been loaded by a method to be described later. The character in the TB is sent to the ADB-IeA of the LCW

In the following step, the character is loaded into register 38. During this step, the first bit, ie the start bit S, is sent in position 0 of the register 38 via the output line 49 onto the line. Since the bit must be sent after five scanning operations, the 0 in register 40 is equal to the display 5. At the end of this step the part 17 contains a 1, which means that the first sampling for the second bit takes place. During the following step, the content of the ADB and the register 38 remain unchanged since the gate circuit 47 is closed and is only prepared when the sampling number has reached the value 5 At the end of this step, register 40 is at 2 and is continued until it is at 5 and then bit A _{1 was} sent over the line during the next step). During this next step, that will Bit A _{1 is sent} over the line when the gate circuit 47 is open and the part 17 changes to 1, thus indicating the first sample of the following bit. This process continues until all characters have been sent and the identification number is recognized bits, followed by zeros, make it possible to send the following characters contained in part TB of the LCW to part ADB.

With further reference to FIG. 7 will be the various stages described during of the reception of times are run through and where Bit29 of the LCW (Fig. 3) is apf 1 and thus designates a receive operation. The character arriving on the line is received bit for bit. When receiving, a bit is only checked

when the scan number of the line has reached a number that is contained in part 16 of the GCW (Fig. 2) This so-called scan test corresponds to the scan operation during which the

incoming bits must be received. Therefore, a bit voo of the line is received when the comparator 43 indicates the sample number or the contents of the register 40 equals the sample check number of the GCW . Before the line is scanned, a flag bit 1 is set in the ADB-TeW of the LCW in such a way that bit 1 is pulled out of the last position when the entire character has been received. The next stage corresponds to the first scanning of the line; the content το of the ADB is transferred to the register 38 via the line 39.

If the scan number is equal to the scan check number, the first bit is loaded into the ADB-TcW and into the register 38 (the bit receiving unit is not shown in the figure).

While the register is being loaded, a shifter 46 causes the contents of register 38 to be shifted to the low positions. It should also be mentioned that the gate circuit 47 is closed during reception and that the input 54 is only energized by a one-bit during transmission. The register 34 is loaded until all characters have been sent. When the last bit is received from register 38, flag bit 1 takes position 0 in the register. This opens the gate circuit 50, provided that the other input 51 also has a one bit of the LCW , from which it can be seen that a receive operation is present. If the gate circuit 50 is open, then a one on line 56 causes the gate circuit 55 to open, and the character stored in register 38 is sent in parallel to part 19 or in TB or in LCW via bus 57. At the same time, the character is loaded into register 53 or TBR so that it can be stored in main memory.

With the help of Table 2 and F i g. 7 now becomes a device for receiving a start-stop character with five samples per bit, where SS = 3.

Table Π

Register 38 O
O
1
1
S.
S.
S.
S.
S. O
O
O
O
1
1
1
I.
1
S. oooooooooj - 0
0
0
0
0
0
0
0
0
0 3 2 1 bit ADB (18) O
1
1
1
S.
S.
S.
S.
S.
Αχ O
O
O
O
1
1
1
1
1
S. - [OOOOOOOOO OOOOOOOOO j O 3 2 O OOOOOOOOO CB 117) rs (19) O O O O 3 2 1 0 4 2 1 T
I. A ₅
O A ₄
0 A ₃
0 OOOOOOOOO, O OOOOOOOOO O ο ^! ooooooooo 1 O O O O! OOOOOOOOO
i O I OOOOOOOOO O 0 0 0
0 0 0
OO 1
O 1 O
O 1 1
1 OO
1 OI
OO 1
O 1 O
OI 1 T A, A ₄ O O O A ₁
0 Αχ
0 S.
O O Π A ₁ Αχ S. 1

The identifier bit "1" is first stored in the ADB part of the LCW , as already described. During the step associated with the first scan, this bit is loaded into register 38 in the same position. During the next step, which belongs to the second scan, the contents of ADB and register 38 are not changed. It only happens during the third scan that the first bit of the character, for example the start bit, is loaded into ADB and into register 38 instead of identification bit 1, which has been shifted by one position. The contents of ADB and register 38 are not modified until the third sampling of the second bit A ₁ , which was loaded into both ADB and register 38. The bits are still received and only if the identification bit "1" is in position 0 of register 38, that is, if the last bit T has been received and that the character has been transferred to position TB of LCW, as shown in Table 2 can be seen.

So far, a character that was to be sent via a line , bit fut bit, was transferred from the ADB part of the LCW via this line, and a second part, namely TB of the LCW _1, which acted as a buffer transfer memory, was loaded into the ADB part when this was free.

The following is now based on the P i g. 8 shows how a character is loaded into the positions of TB or into the associated register. If a line functions as a transmission line

6j yaws, then the character to be transmitted is transmitted from the positions of the TB to the positions of ADB in the LCW . If TB is empty, it becomes a bit. the so-called transmission buffer volt bit [TBF),

/ IO

which occupies position 23 in the LCW (FIG. 3), changed from I to 0. At this time, a request for the sign is made to the main memory in Fig. 8 to see causes the condition bit TBF = 0, the address of LCW in the request line, which is stored in register 22 (LAA) to the register 58 to transfer. The purpose of the register is that the requests from the main memory HSS are executed regardless of the speed with which the requests are made. It should be remembered that it can take up to 25 steps before a character request is completed. When a request has been made, the LCW (Fig. 3) sets bit 24 to 1, indicating that there is a service request. During the storage operation in register 58, a request is sent to the multiplex channel via output 59. If the line address stored in register 58 is in the first position, it is transferred to buffer registers 60 and 61. In the interests of clarity, it has been assumed that the circuit arrangement of the present invention works with a multiplex channel from the central processing unit with 8-bit groups or bytes. This also means that the registers have 8 positions or positions. However, this does not represent a restriction of the invention, since other bit configurations are also easily possible. Is z. B. Assuming that the address of the LCW occupies 10 binary digits (see FIG. 2), then the address must be in two buffer registers, namely registers 60 and 61 in FIG. 8 can be saved. This address is then transferred to the main memory of the central unit via line 65 and, on the other hand, entered in register 66. A character, which is then to be transmitted over the line of the corresponding LCW address, is then received by the main memory and the multiplex channel over the bus 67. Since this character has 10 binary digits, it is stored in buffer registers 62 and 63. At this point in time, the previously described interruption will occur. When the scanning of the lines is completed, a step for transferring the character in registers 62 and 63 to part TB of the LCW is occupied, the address of which is given via bus 68 by register 66. When the character has been transmitted, bit 23 or TBF of the LCW is set to 1 and bit 24 or SR to 0. Then this character can be transmitted bit by bit to the ADB part of the LCW via line 69.

If the line operates as a receive line, then the character is loaded bit by bit into the ADB part of the LCW and then into the TB part, as previously described. Then the character must be transferred to main memory. The reception process is similar to that of the transmission, but the address of the LCW, which comes from register 22 (LAR) , and the character which is in TB , is also put into register 58 via output line 70, a known type and a request to the multiplex channel is made via output line 59. Because, if this request is in the buffer registers and the address in registers 60 and 61 and the character in registers 62 and 73, the content of the register is transferred to the main memory register by register via the collecting channels 65 and 71. It starts with registers 60 and 61, which contain the address.
As can be seen from the foregoing, there may be an interruption when the lines are being scanned, delaying the scanning operation by one step. It can also be seen that there is an interruption when a character is written to an LCW of the fast memory

, o HSS must be stored. Another interruption occurs when a word has been completely stored in the high-speed memory HSS , e.g. B. an LCW that corresponds to another line. If it is now assumed that words

memory HSS have 40 binary digits, then these 40 bits are first given in five buffer registers 60, 61, 62, 63 and 64 byte door bytes via line 67 (FIG. 8). Therefore, there is an interrupt step which causes the contents of the five buffer registers to be transferred to the desired locations in the high-speed memory HSS . In fact, there is an interruption when there is access to the high-speed storage HSS in a location different from that which is required

Time is reached by the scanning process. In addition, other interruptions that have not been described can also be made. For example, an interrupt step occurs when words / u are to be taken from the high-speed memory HSS (e.g. an LCW or a GCW) for test purposes. At each interruption, the scanning process on the lines is stopped and a step is reserved for that interruption. During this step, the registers GCAR, DSAR, LAR and LCR shown in FIG. 6 are left unchanged and only the contents of the ISCR register are decremented by one, indicating that one of the spaces was used.

Claims (7)

Patent claims: 1. Circuit arrangement for scanning and controlling the transmission of information between a memory system and lines, dje are connected to input and output units of an electronic data processing system and the information can be transmitted at different speeds and different transmission modes via a transmission channel that includes a high-speed memory in which there is a first group of memory positions which are assigned to the individual transmission lines for collecting information, characterized in that a second group of memory positions is present in the high-speed memory (HSS) which contains control information (QCW) for defining all scanning features of the lines which while a scanning operation subdivided into scanning cycles as a function of the transmission speed and the transmission mode becomes and daO at the beginning of the total scan a group control address register (21) the address öS records the first control information (GCHO in the high-speed memory (HSS) , which is used for the parallel transmission of the control information (OCW) with a group of register levels (20, 22, 23 and 24) 209624/312 and that a scan cycle has an elementary step during the access to the second memory positions, which are immediately followed by further elementary steps, while whose lines are scanned with common transmission modes and speeds will. 2. Circuit arrangement according to claim 1, characterized in that the second group of memory positions contains control data and memory positions of the first group, the Scanning of the first group immediately follows access to the second group. 3. Circuit arrangement 'according to claim 2, characterized in that the access to memory positions a third group of additional steps are assigned to allow access to the control the second group, this access to the second group depending on the control information the third group is running. 4. Circuit arrangement according to claims 1 to 3, characterized in that one or several scanning steps for interruption to be used to store the data to be transferred via a line to the storage positions to get to the first group. 5. Circuit arrangement according to claims 1 to 4, characterized in that a scanning process takes place when none of the lines is in the transmit or receive status. 6. Circuit arrangement according to claims 1 to 4, characterized in that at the beginning of the total load a group control address register (21) contains the address of the first group control word [GCW) in the high-speed memory (HSS) and that this group control word is parallel to a register group (20, 22, 23 and 24) is given. 7. Circuit arrangement according to claims 1 to 6, characterized in that each memory position the second group contains the control information for a group of lines, which have both the same transmission speed and the same transmission mode and that it still contains the corresponding memory position in the first group. For this purpose 2 sheets of drawings