DE3928481C2 - Priority-oriented decentralized bus allocation system - Google Patents

Description

The invention relates to a bus allocation system according to the Preamble of claim 1.

A generic system is from IBM Tech. Dis. Bul. Vol. 16, No. 3, Aug. 1973, pp. 874 to 876. A generic bus allocation system is known from the contribution by G. Färber "A decentralized fair bus arbiter "in ELEKTRONIK 1980, issue 8, pages 60 to 68, in particular Section 1 "Allocation Procedure ". The functional problems in the implementation of a fair bus arbiter "are also shown in the Essay by G. Angel´ "Algorithm and Implementation a decentralized, fair and fault-tolerant bus arbiter in ELEKTONIK No. 9, 1981, pages 79 to 84. Um when there is a high volume of messages on the receiving line a digital local communication system with the logical structure of a loop messages high To be able to send priority immediately and otherwise Message packets largely sorted by priority To let it go through, it is from DE 34 13 144 A1 known, each message packet in addition to the priority indicator assign a request indicator. In incoming message packets of the same priority is the request bit from the station claiming the broadcast of the foreign message packet is set to "1". This should mean that the signal runtimes are otherwise too long can be mastered with large network expansion. On the other hand, according to EP 0 154 725 A2 Priority determination by issuing a selection start signal in ready-to-send data processing units, who want to access a multi-conductor arrangement causes to thereby receive in everyone Data processing unit the delivery of a reception identifier trigger. This becomes a priority assignment on traffic between two immediately one another  assigned units reduced.

A disadvantage of the known methods of bus access Awarding is in particular that this is relatively inflexible are because they are essentially based on priorities for the individual peripheral access to the bus Participants based. There is real flexibility also not achievable in that the individual Priorities assigned to participants, for example according to a target but actually then not yet established bus access variable may be an originally low priority one scheduled participants not practically completely from Exclude bus access. The traditional arbitration systems are also responsible for the interests of Practice often disadvantageous in that it usually does one special arbitrator module for querying the individual peripheral participants need that then the bus access control takes over. The use of special Circuit units for the implementation of higher-level and secondary tasks, however large space requirement on a circuit board is not only for this additional circuitry, but  also for numerous additional control lines in addition to the actual data bus of the bus system.

This is particularly disadvantageous when it comes to implementation a compact, powerful microcomputer concept various types - such as signal processors, special hardware circuits and / or analog and digital on output devices (such as sensors) and output devices (such as control circuits gen) - together with high data throughput using data block transfers have to work.

The invention is based on the knowledge of these circumstances based on training a bus allocation system of this type that despite the task-dependent variable bus access priority of the individual system participants with a relatively narrow system bus, So with as few control lines as possible parallel to the actual one Chen data bus, a quick and clear arbitration for the bus allocation right can be adjusted.

According to the invention, this object is essentially achieved by that the system bus and its participants according to the labeling part of claim 1 are designed.

According to this solution, the data bus is there as long as there is no information Transmission takes place, all participants simultaneously to the parallel Transmission of their current bus access priorities (if via bus access is currently required). Everyone Participant not only delivers (via at least one firmly assigned to him ordered management of the data bus) to everyone else - the entire Da tenbus querying - subscriber its own, current priority message; each participant also compares their own current priority with all other participant priorities, see above that each participant can determine for himself whether his access priority in the system bus is currently the highest or not.  

If not, the next arbitration cycle will be waited for the information currently to be initiated transmission immediately follows. However, if a participant is stuck proves that he has the highest priority, he proves for himself the bus access, which ends the arbitration and all other participants are denied access to the bus. Should be several Participants in the current arbitration cycle have the same information have dependent (software) priority, then the winner Participants the bus access, which is also the highest hardware priority rity. Every hardware priority is circuit-related (at for example via manually set switches), and in such a way that it only occurs once within the system. Thereby is only done with one participant even with the same software priorities basically allows bus access. The lines of the data bus from this for the duration of the subsequent informa tion transmission blocked for priority information. The information Transfer begins with tax information in the information about the other participants to be addressed, and Information about the processing to be carried out there and the length of the then transmitted data blocks. With output of all upcoming The subscriber switches information data blocks to the data bus, who won the bus access, the data bus again at the same time current priority messages of all on the system bus connected subscribers free, and the next following begins Arbitration cycle, i.e. the output of the priority messages all participants on the assigned data bus lines and the comparison of all priority messages with your own priority in each of the connected participants. If each participant currently receives a priority message of "none Bus access required ", a new one immediately closes such arbitration cycle, so that practically no absenteeism occur: As soon as only one participant needs bus access, receives he - if several participants want access to the bus at the same time, switch off all those who are stuck make sure that they do not currently have the highest bus access priority.  

Such a system is evidently extremely economical Lich the effort on lines in the system bus and in terms of required arbitration times. In particular, none will orderly control circuit for arbitration and bus allocation needed. The system is also very flexibly expandable, since the The number of connectable participants is limited only by how many data bus lines assigned to the respective subscriber available and, depending on the amount of information in the priority message, are required for priority encryption. The system is in its mode of action, regardless of the character of the participants (Processors or non-intelligent circuits) and it allows a bus request regardless of whether information in the Bus is to be fed in or retrieved from the bus and independently regardless of how many other participants the one who Bus access desires for the distribution or collection of its Wants to communicate information at the same time. Despite this a lot Functional options will only require a minimum of tax in addition to the actual data bus, as this one after the other other for arbitration and information transfer is used.

In order to further shorten the arbitration time, there is a data out swap expediently always with temporary storage in quick len memories (RAMs) in the individual participants, if a part not already defined as a fast hardware circuit sets is. As a result, the exchange of information does not depend on it gig, how quickly the inclusion or delivery of processor information is; while the peripheral processor is from the system bus reads information transferred into the buffer can be the next arbitration cycle is already running on the data bus.

So this powerful bus allocation process stands out also by high running speed. It basically requires only two clock cycles of the bus system: in the first cycle everyone gives Participant sends its current priority message over the data bus  to all other participants, and in the second bar every part recognizes for himself that he did not win the arbitration - otherwise, he accesses all other nodes from the bus closes - to its pending information to the associated Submit participants.

Additional alternatives and further training as well as further notes Male and advantages of the invention will become apparent from the other claims chen and from the description below one in the drawing below Restricted to the essentials, highly abstracted preferred implementation example for the inventive solution. It shows

Fig. 1 in the manner of a two-pin block diagram, the system bus for the staggered data communication between different participants connected to the bus and

Fig. 2 is a timing diagram for the sequence of priority assignment in the bus system acc. Fig. 1.

The system bus 101 outlined in the drawing essentially carries a data bus D of b bits in width for the block transmission of binary-coded information I, in particular of data blocks IB. To identify a transmitted information I as a data block IB, the system bus 101 additionally carries a strobe line, the potential of which changes its normal state during a data transmission, as described in more detail below. The current potential on a busy line Y indicates whether information I is currently being transmitted via the data bus D or whether the data bus D is free for the exchange of priority messages P between those connected to the system bus 101 Participants N who can be considered as the sender or receiver of data blocks IB. The synchronous control for the interaction of the subscriber N takes place via a clock or clock line T.

Depending on the functions of the participants N, in particular according to their They have to exchange meaning for the function of a system the information (to be submitted and to be recorded) I. priority values Pd. Information I thus has a higher one Priority value Pd if it is essential for the maintenance the system function, compared to information I that only serves a monitoring or notification purpose without immediate to intervene in the further course of the system function. If different bus participants N in traffic with others at the same time Transmit N information I via data bus D (deliver or want to record), the participant receives N first the bus access, the information required in comparison with the other pending access requests the highest priority value Pd has. In order to be able to assess this, it takes place before the transfer of information I via the data bus D an exchange of the respective Priority values Pd between the participants N. For this are everyone the subscriber N a number of a lines from the b lines of the data bus D permanently assigned, namely each of the participants N others Lines a. If the number n of participants N so over the data bus D of the number of lines b is supplied, that is to say the n subscribers N priority lines are assigned from data bus D, then the limit applies

a × n b.

An optimal utilization example is entered in FIG. 1, namely for a data bus width of b = 32; with n = 16 subscribers N, each a = 2 lines can be made available for the exchange of the priority messages P (2 × 16 = 32).

Since each of the two lines a can carry 1-bit information and the priority message P due to the assignment of a = 2 Lei lines has a width of 2 bits, the information is catch the priority message P four different binary-coded  Values, one of which is in a clock cycle via the data bus D can be transmitted to all participants N If in the following Clock cycle another value is transmitted, results from the Value sequence a two-digit priority information of the information range of 4 bits. The lowest value is expediently (0) defined as the highest priority because this is circuit moderately easiest to query; with the result that the one Subscriber N, who currently does not want any bus access, as a priority message P outputs the highest value (15).

Each of the participants Nn usually has a data source 102 (for example a transducer and / or a signal processor) or a data sink 103 (for example a signal processor and / or a digital-to-analog converter) which has a coupling circuit 104 with are connected to the system bus 101 . To reduce the bus occupancy times, a fast buffer memory (RAM) 105 can be provided in each node N, which stores the information I from or for the data bus D when the transmission from the data source 102 or into the data sink 103 would be too tedious (for example because it is a signal processor). The intermediate memory 105 is, however, unnecessary if the subscriber N has a fast input memory, such as in the case of the FIFO memory of an analog-digital converter or in the case of an input register in front of a digital-analog converter; or if a special circuit is implemented that enables quick access to immediate data exchange.

The essential function of the coupling circuit 104 is, depending on the current requirements, to provide access to the system bus 101 for the recording or delivery of information I. For this purpose, each bus request for outputting or for receiving information I is linked to a priority message P, which is currently generated in the respective subscriber N in accordance with its use, for example in the course of the extraction and processing of the information I. In the example shown, this is from the subscriber Ni to be delivered information Ii linked to the assigned priority message Pi, which is kept in a priority memory 106 (separated into two sequences by two bits d, d '). The actual information to be transmitted I is temporarily stored in an information register 107 .

If none of the subscribers N has current bus access, ie if neither information I nor priority messages P are currently being transmitted via the data bus D, then the open collector busy line Y (in the example shown, FIG. 2) carries high potential. As a result, in each of the subscribers N connected to the system bus 101 , the priority memory 6 is released for issuing the priority message P. This is done in two consecutive clock cycles by the bit sequence dd ', output one after the other on the assigned two lines a of the data bus D. Thus, each participant N issues his current priority message P on the assigned lines a of the data bus D, to which in each Participant N a priority query circuit 108 is connected. This one after the other takes the two bits d, d 'of the serial priority messages P of all subscribers N who simultaneously receive line pairs a via the associated line pairs, and it queries whether the priority message Pi thus reassembled by its own subscriber Ni has a higher degree of urgency has than the priority messages P of the other participants N. If this is not the case, that is, if a higher priority message P is received via the other line pairs a than is provided itself (Pi), the query circuit 108 blocks i via one Gate circuit 109 repeats the output of the priority message Pi from the priority memory 106 ; because obviously another participant N has a bus request to submit or record information I with a higher degree of urgency.

If a subscriber Ni receives a priority message Pi with the highest urgency currently present on data bus D, but another one of the subscribers N resembles a priority message P.  issues a high degree of urgency, then decides on the bus no longer only access the priority linked to information I. rity message P, but from the now balanced requirements The participant Ni is awarded the contract for the bus handle that the highest circuit-technically fixed devices PKi priority. The can be supplied from an identifier K which, for example, is a manual one baren coding switch. The only thing to make sure is that everyone Switch position occurs only once in the system, that is, each part Nn receives another identifier Kn, staggered according to the stipulations its importance in the context of the overall function of the system.

If the affected subscriber Ni has found out that he himself has the highest software priority (and possibly also the highest hardware priority in the case of a number of upcoming equal software priorities), the potential is triggered on the busy line Y via the query circuit 108 changed, symbolized in the example of FIG. 1 by reversing a flip-flop 110 . As a result, the output of priority messages P is blocked in all subscribers N (illustrated in FIG. 1 by driving the gate circuit 109 ), so that the data bus D is now available for the transmission of information I.

A block of control information ICi is output as first information I in that a gate circuit 111 behind a control memory 112 in the subscriber Ni, who has just gained the bus access, is activated. This control information contains above all with which or with which other subscriber (s) Nn this subscriber Ni is to connect for data exchange (delivery or recording of data blocks 1b). In the example outlined in FIG. 1, this is the case of the further subscriber Nn, who is only incompletely sketched in the drawing above (actually equipped just like the subscriber Ni). That communication subscriber Nn is individualized by its identifier Kn. In addition, the control information IC generated, for example, by the data source 102 contains, for example, information about how many cycles the transmission of the actual data block IB will take and how long it will be, as well as information about the reception-related treatment of this data block, for example with regard to intermediate storage and / or further processing in the receiving participant Na.

All participants n therefore go to receive the destination identifier Kn now transmitted via the data bus D if a gate 113 is released because the potential on the busy line Y has been switched over, while on the strobe line S the previous one Potential is pending (see Fig. 2). First, those lines a of the data bus D are evaluated which (now no longer a priority message but instead) carry the destination identifier Kn for the subsequent data block Ib. These can be the same lines a that could previously carry the priority message P, as long as the busy line Y was still high (see FIG. 2). A comparator 114 outputs an acknowledgment signal 115 in that, and only in that, subscriber Nn, in which the received request identifier matches its own identifier Kn. By transmitting several request identifiers Kn ', several subscribers Nn' can be addressed simultaneously via control information Ic.

The acknowledgment signal 115 expediently serves the feedback of the identifier Kn of each of the addressed subscribers Nn, so that a comparator 116 can be used to check whether all subscribers Nn that should be addressed by the current control information ICi have been reached. It is advantageous if these addressed subscribers Nn emit a defined signal sequence at the end of the acknowledgment signal 115 , for example high potential over a certain number of clock cycles and then transition to low potential. If this mark is also detected by the comparator 116 , it controls the potential previously present on the strobe line S via a changeover switch 117 (from FIG. 2 from high to low), and it simultaneously switches an output gate 118 for the now the data bus D to the addressed subscribers Nn data blocks IBi to be transmitted. This binary information on the data bus D is thus characterized as information data blocks IB in that (as in the illustrated example) the busy line Y is still pulled to low potential and the strobe line S is now additionally set to low potential. At the end of the data block transmission, both potentials are then raised again, namely by controlling the flip-flop 110 or the changeover switch 117 . This end information can be contained at the end of the last data block IB; or it is contained in the data block control information IBc, for example in the form of the length of the data blocks IBi following the control information ICi.

In the receiving subscribers Nn, the delivery of the response acknowledgment signal 115 causes the preparation of an enable circuit 119 , which then releases an input register 120 when the potential is switched to the strobe line S to receive the data blocks IBi which are then present on the data bus D.

If at the end of the transfer of data blocks IB the potential the busy line Y is switched back to high, starts with it the next of the arbitration processes described to determine which participant N is a bus request with the highest urgency degrees.

Claims (6)

1. Priority-oriented decentralized bus allocation system for a number (n) of participants (N) on a data bus (D) for transmission of priority messages (P) and information (I), with participants (N) individually at least one of the lines (a) of the data bus (D) is assigned to the transmission of priority messages (P) and the subscribers (N) with a query circuit ( 108 ) for comparing their current priority messages (P) with the priority messages (P) from the other subscribers (P) pending on the data bus (D). N) are equipped, whereupon the subscriber (N) whose priority message (P) currently pending on the data bus (D) currently has the highest degree of urgency, transmits his information (I) and then the data bus (D) again for receiving current priority messages (P ) enabled, characterized in that before the information (I) is transmitted, all send in successive system clock cycles willing subscribers (N) their priority message (P), which are complemented by unique subscriber-specific hardware priority identifiers (Pk) when several currently the same high-quality information-dependent software priority messages (Pd) are added, simultaneously transmit them via the data bus (D), whereupon the subscriber (N) with the currently highest degree of urgency of his priority message (P) blocks the output of further priority messages (P) on the data bus (D) and transmits his information (I) to the addressed subscribers (N) assigned fast recording memory ( 105 ) to then re-enable the data bus (D) to receive current priority messages (P) from all participants (N) interested in sending at the same time. 2. Bus allocation system according to claim 1, characterized in that each participant (N) on the associated line or lines (a) of the data bus (D) in successive clock cycles of the system bus ( 101 ) a bit serial priority message (Pd, Pd ') Issues. 3. Bus allocation system according to one of the preceding claims, characterized, that after completing the arbitration via the data bus (D) Informa tion (I) are transmitted, the first block tax information tion (IC) and then the actual data blocks (IB) include. 4. Bus allocation system according to one of the preceding claims, characterized in that the subscriber (N) who gains access to the system bus ( 101 ) on the basis of the currently highest priority (P), a pa rallel to the data bus (D) existing busy line (Y) until the end of the block transmission of information (I) on the data bus (D) switches over and then releases again for the line assignment of the data bus (D) to the individual participants (N) for the next arbitration cycle. 5. Bus allocation system according to one of the preceding claims, characterized in that the system bus ( 101 ) in addition to the data bus (D) leads a strobe line (S), which the participant (N), due to the highest priority (P) has gained the bus access, switches to identify the current transmission of actual information data blocks (IB) when a previous transmission of block control information (IC) via the data bus (D) has ended and the transmission of information data blocks (IB ) has not yet ended. 6. Bus allocation system according to one of the preceding claims, characterized in that each participant (N) is equipped with an acknowledgment transmitter ( 121 ) which on the line associated with it for arbitration (s) (a) of the data bus (D) has an acknowledgment signal ( 115 ) outputs if its subscriber identifier (K) is contained in a block control information (IB) as an address for data blocks to be delivered or to be retrieved (IB), which the subscriber (N) winning the bus access on the basis of highest priority (P) after winning outputs the current arbitration and before the actual information data block (IB) is transmitted to the data bus (D).