WO1996037849A1

WO1996037849A1 - Sequential polling/arbitration method using signal bisection and device therefor for multinode network

Info

Publication number: WO1996037849A1
Application number: PCT/KR1996/000077
Authority: WO
Inventors: Jin Young Cho
Original assignee: Jin Young Cho
Priority date: 1995-05-26
Filing date: 1996-05-25
Publication date: 1996-11-28
Also published as: AU5845896A; KR100242610B1; KR960043636A

Abstract

There are provided a sequential polling/arbitration method using signal bisection and a device therefor for rapidly and accurately identifying an information source having the highest priority when a plurality of service request signals are simultaneously generated, in a multinode communication network where a plurality of communication stations share a single common bus. The sequential polling/arbitration method using signal bisection for a multinode network having a plurality of stations with N-bit identifying addresses includes the steps of generating a polling/arbitration initializing signal indicating the start of contention for access to a common bus by every station requesting access, and logically operating each bit of the identifying addresses of all the stations participating in the common bus contention in a polling/arbitration initializing signal period, and comparing the logically operated address bits with common bus signal bits, wherein contention is canceled or continues based on the result of the comparison, so that a station having the highest priority is quickly identified among 2N stations by N comparisons at most. Here, each bit of an identifying address is sequentially compared with a corresponding bit of a common bus signal from MSB to LSB, and then the priority of each station is determined. Thus, a time for assigning bus access is reduced and a bus access assigning method becomes simple, compared with that of the prior art. As a result, the polling/arbitration method and device are effective in that high-level application protocol and operation are facilitated and real-time processing is possible on a multi-serial line.

Description

SEQUENTIAL POLLING/ARBITRATION METHOD USING SIGNAL BISECTION AND DEVICE THEREFOR FOR MULTINODE NETWORK

Technical Field

The present invention relates to a sequential polling/arbitration method using signal bisection and a device therefor for rapidly and accurately identifying an information source having the highest priority when a plurality of service request signals are simultaneously generated in a multinode communication network where a plurality of communication stations share a single common bus.

Background Art

Generally, a multinode network system employs a self-selecting distribution/arbitration method for rapidly identifying an information source and a method for solving the non-synchronous problem caused by a difference in transmission rates, to overcome problems associated with complex and irregular data lines.

Especially, to perform efficient communications among a plurality of stations, the most important thing is to ensure rapid and accurate identification of an information source and to prevent bus collisions resulting in bus contention.

For constructing a system having a plurality of stations, the plurality of stations are connected to a common resource by a common bus, or by a communication link.

In such a multinode network, arbitration for granting access to the resource is needed when several stations simultaneously request the common resource.

For the prior art arbitration, Centralized Parallel Arbitration, i.e. , Vectored

Interrupt, Daisy Chain, and Distributed Arbitration by Self-Selection have been used.

In Centralized Parallel Arbitration, a single arbiter copes with the requests from a plurality of stations for access to a resource using a batch process; in the Daisy Chain method, a plurality of systems are connected together by serial lines; and in Distributed Arbitration by Self-Selection, each station is provided with an arbiter, a station requesting access to a resource monitors a current resource state, and then arbitration is implemented by a predetermined algorithm, to thereby grant common resource access to the station. A common resource assigning privilege is determined by the algorithm used for the arbitration.

Here, the common resource assigning privilege involves fairness and priority. Fairness means granting every station equal access to a common resource, while priority means granting a station access to a common resource according to its priority level.

Centralized Parallel Arbitration, despite the advantage of high speed arbitration, is not suitable for long-distance communications due to complexity of physical lines and its limited expendability.

The Daisy Chain method also has a distinct drawback in that physical wiring is required and a priority level is determined by a wiring order, though stations can be expanded only with two to four lines without additional parallel lines.

Furthermore, serial methods such as Daisy Chain require additional control lines, are slow in speed, and employ analog methods, in many cases.

Disclosure of the Invention

To overcome the above problems, the object of the present invention is to provide a sequential polling/arbitration method using signal bisection and a device therefor for ensuring rapid and accurate identification of an information source and preventing common bus collisions inherent in contention for access to a common bus, to efficiently implement communications among a plurality of stations.

To achieve the above object, there is provided a sequential polling/ arbitration method using signal bisection for a multinode network having a plurality of stations with N-bit identifying addresses, comprising the steps of: (a) generating a polling/arbitration initializing signal indicating the start of contention for access to a common bus by every station requesting access; and (b) logically operating each bit of the identifying addresses of all stations participating in the common bus contention in a polling/arbitration initializing signal period and comparing the logically operated address bits with common bus signal bits, wherein contention is canceled or continues based on the result of the comparison, whereby a station having the highest priority is quickly identified among 2^N stations by N comparisons at most, resulting in rapid priority identification.

It is preferable that the sequential polling/arbitration method using signal bisection for a multinode network further comprises the step of granting priority to the first responding station using at least a single bit of the identifying address thereof before step (b).

It is preferable that step (a) further comprises the step of performing a logical OR operation with respect to the transmission bits of contending stations so hat the logical sum becomes a common bus signal which activates the common bus only with the logic state of " 1 " among the values of address bits, to prevent common bus collisions beforehand.

It is preferable that step (a) further comprises the step of performing a logical AND operation with respect to transmission bits of contending stations so that the result of the logical multiplication becomes a common bus signal which activates the common bus only with the logic state of "0" among the values of address bits, to prevent common bus collisions beforehand.

It is preferable that the priorities of the identifying addresses dynamically vary by changing transmission rates.

It is preferable that common bus access privilege is granted to a station having an identifying address of the highest priority, in step (b).

It is preferable that common bus access privilege is granted to a station having an identifying address of the lowest priority, in step (b).

It is preferable that the identifying addresses are sequentially compared from the most significant bit to the least significant bit in step (b).

It is preferable that the identifying addresses are sequentially compared from the least significant bit to the most significant bit in step (b).

There is provided a sequential polling/arbitration device using signal bisection for a multinode network, comprising: a serializing portion for receiving an identifying address and generating a serial bit stream based on a transmission clock signal; a modulating portion for receiving the serial bit stream and outputting a modulated pulse sequence through a predetermined modulation method; a bus interface portion for receiving one of the modulated pulse sequences according to the modulation method and a predetermined common bus access request and outputting a wired-logic operation value to a serial common bus; a comparison/determination portion for receiving one of the modulated pulse sequences and a common bus signal to identify contention priority, detect a common bus access request from another station, and then generating a signal for ascertaining existence of a contention; and a controlling portion for receiving the common bus request, the contention existence ascertaining signal, and a predetermined common bus access contention request, and for controlling the transmission clock signal to be continuously provided only during contention as well as generating a bus access signal after the contention, so that a bit stream acquiring a common bus access is output to the common bus when the bus access signal is generated.

It is preferable that the logic operation is a wired OR between a common bus and a station in the bus interface portion.

It is preferable that the logic operation is a wired AND between a common bus and a station in the bus interface portion.

It is preferable that the modulating portion modulates the serial bit stream using a Manchester encoding method.

It is preferable that the modulating portion modulates the serial bit stream using a duty cycle modulation method.

Brief Description of the Drawings

The above object and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:

FIGS. 1A and 1B are block diagrams of multinode networks to which the present invention is applied;

FIG. 2 is a flowchart of a sequential polling/arbitration method using signal bisection for a multinode network according to the present invention;

FIGS. 3 A and 3B are contention stage tables for explaining the sequential polling/arbitration method using signal bisection for a multinode network according to the present invention;

FIG. 4 is a contention tree diagram of the sequential polling/arbitration method using signal bisection for a multinode network according to the present invention;

FIG. 5 is a timing diagram representing common bus access contention among four stations in the sequential polling/arbitration method using signal bisection for a multinode network according to the present invention;

FIG. 6A is a contention operation timing diagram according to a Duty Cycle Modulation (DCM), in the sequential polling/arbitration method using signal bisection for a multinode network according to the present invention;

FIG. 6B illustrates DCM waveforms of FIG. 5;

FIG. 7 is a contention timing diagram according to the Manchester encoding method in the sequential polling/arbitration method using signal bisection for a multinode network according to the present invention;

FIG. 8 is a contention timing diagram according to a three-level modulation method in the sequential polling/arbitration method using signal bisection for a multinode network according to the present invention; and

FIG. 9 is a schematic diagram of a preferred embodiment of a sequential polling/arbitration device using signal bisection for a multinode network according to the present invention. Best mode for carrying out the Invention

A preferred embodiment of the present invention will be described in detail referring to the attached drawings.

FIGS. 1A and 1B are block diagrams of multinode communication networks to which the present invention is applied.

FIG. 1A illustrates a multinode network having a plurality of stations connected together in a wired OR gate configuration 1010A. In the figure, each station 1020A is physically connected to a common bus 1000, and a signal of the common bus 1000 and an output signal of each station are logically summed. Here, each station can activate the common bus only with a logic "1 ". The common bus 1000 is grounded through a resistor 1030 A.

FIG. 1B illustrates a multinode network having a plurality of stations connected together in a wired AND gate configuration 1010B. Each station 1020B is connected to the common bus 1000, and a signal of the common bus 1000 and an output signal of each station are logically multiplied. Here, each station can activate the common bus only with a logic "0". The common bus 1000 is powered via a resistor 1030B.

In the above multinode networks, a station acquiring a common bus access becomes a bus master, determines an intended communication object, and enables communications in a half duplex mode.

In the present invention, two types of multinode communication systems can be achieved, however in this embodiment the logical sums of transmission bits of stations participating in contention for access to a common bus become common bus signals which prevents common bus collisions during polling/arbitration.

FIG. 2 is a flowchart of a sequential polling/arbitration method using signal bisection for a multinode network according to the present invention.

The sequential polling/arbitration method using signal bisection for a multinode network according to the present invention is implemented by: determining the presence or absence of a common bus access request (step 2010), generating a synchronization pattern to allow fair contention for access to the common bus (step 2020), detecting the synchronization pattern (step 2030), determining the end point of the synchronization pattern (step 2040), outputting a "0" to a common bus signal for common bus initialization (step 2050), determining whether the common bus signal is activated during a standby time (step 2060), assigning the number of address bits in a loop counter (step 2070), logically summing the common bus signal and the most significant bit (MSB) of a station address (step 2080), comparing the MSB of the address of a corresponding station and a corresponding bit of the common bus signal to ascertain activation of the common bus (step 2090), decreasing a loop count by 1 (step 2100), determining whether the value of the loop count is 0 (step 2110), shifting an address bit of the corresponding station (step 2120), and gaining access to the common bus (step 2130).

In step 2010, it is determined whether there is a request for the common bus from a corresponding station .

If the corresponding station issued a request for the common bus, step 2020 is performed. If such a request is not found, step 2030 is performed.

In step 2020, stations requesting access to the common bus transmit synchronization patterns to the common bus to participate in contention. When step 2020 is completed, step 2030 is performed.

In step 2030 of determining whether a synchronization pattern is detected in the common bus signal, if no synchronization pattern is found, the procedure loops back to step 2010. If a synchronization pattern is found, step 2040 is performed.

In step 2040, the synchronization pattern is continuously examined until the falling edge of the last synchronization pulse is detected.

When it is determined that the synchronization pattern ends, step 2050 is performed.

In step 2050 where common bus initialization is performed, a corresponding station outputs a "0" onto the common bus to prevent activation thereof. Step 2060 is performed, following step 2050.

In step 2060, it is determined whether the common bus is activated during a standby time. If another station is activated, a corresponding bit of the common bus becomes " 1 ", and a corresponding station relinquishes its current contention for the common bus. If other stations are not activated and a corresponding bit of the common bus signal is "0", step 2070 is performed.

In step 2070, a loop counter is initially loaded with a value representative of the number of bits of the address of the corresponding station. Step 2080 of logically summing follows step 2070.

In step 2080, the MSB of the address of the corresponding station and a corresponding bit of the common bus signal are logically summed. After step 2080, step 2090 is performed.

In step 2090, the MSB of the corresponding station is compared with a corresponding bit of the common bus signal. If the MSB of the address of the corresponding station is smaller than a corresponding bit of the common bus signal, the contention of the corresponding station is canceled, because another station is activated earlier than the corresponding station. If the MSB of another station is equal to or larger than a corresponding bit of the common bus signal, the contention for the common bus is not relinquished, and step 2100 is performed.

In step 2100, the value of a bit count is decreased by "1", to sequentially determine a bit activation from the MSB to the least significant bit (LSB). Step 2110 follows step 2100.

In step 2110, each bit of the common bus signal is compared with each corresponding bit of the corresponding station address to determine whether the activation of the common bus signal is ascertained. If the loop count value is not "0", this implies that activation determination is not completed to the LSB. Then, step 2120 is performed.

In step 2120, the address bits are shifted to the left to allow comparison of the bit following the MSB. Then, step 2080 is performed.

In step 2110, if the value of a bit count is "0", this implies that activation comparison of every address bit of the corresponding station is completed. Subsequently, step 2130 is performed to grant exclusive access of the common bus to the corresponding station.

In addition, if there is a common bus request, a synchronization pattern is output. If no synchronization pattern is found, step 2010 is repeatedly performed, while whereas if a synchronization pattern is found, the end point of the synchronization pattern is detected, thus preventing the common bus from being activated during a standby time.

On the other hand, if the common bus is activated by another station during the standby time, the common bus contention of the corresponding station is relinquished. Otherwise, the number of address bits is assigned in the loop counter, that is, the number of repeated loopings is determined. Then, the common bus and the MSB of the address are logically summed. When the MSB is found to be in a non-activation condition past the standby time, it is determined whether the common bus is activated. If it is, the contention is relinquished, and the procedure branches to step 2010 to determine whether there is a common bus request. If it is not, the loop count is decreased by 1. Thus, unless the loop count value is "0", the identifying address is shifted toward MSB, and the procedure branches to step 2090. If the loop count value is "0", access to the common bus is gained. That is, a sequential address bit comparison continues and contention is canceled when a bit value of the common bus signal is larger than that of a corresponding station.

In other words, the identifying address bits are compared with the corresponding common bus signal bits, sequentially beginning from its MSB. If the bit value of the address in a given bit position is not equal to that of the common bus signal, then the station relinquishes its contention in the next comparison period.. Otherwise, the station remains in contention for the common bus till the LSB comparison. As described above, using the comparison method of the present invention, when all stations each having an n-bit identifying address are participated in contention, the number of competing candidates is decreased by half in each bit comparison stage. Thus, n comparisons are required to identify the identifying address of a station with the highest priority among 2n candidate stations.

FIGS. 3 A and 3B are tables of contention stages for sequential polling/arbitration using signal bisection for seeking access to the common bus in the case of 8-bit station addresses, in a sequential polling/arbitration method using signal bisection for a multinode communication network according to the present invention.

The present invention will be described, with reference to the contention stage tables of FIGS. 3A and 3B and the flowchart of FIG. 2 from step 2080 to step 2130.

Assuming that every station having an 8-bit address participates in common bus contention, 128 stations having "0s" as their MSBs are dropped out among 256 stations and the other 128 stations having "1s" as their MSBs remain in the contention, in stage 1.

Among the 128 participants, at most 64 stations having "0s" as the subsequent lower bits are excluded from the contention, and the other 64 stations continue their contentions, in stage 2. With repetition of such a method to the LSBs, only the station with the highest priority can gain access to the common bus.

As noted from FIGS. 3 A and 3B, the number of competing stations can be reduced by half depending on their priorities.

FIG. 4 is a tree diagram of a contention principle in a sequential polling/arbitration method using signal bisection in the case of a station with 4-bit station addresses. It is noted from the figure than the number of competing stations is reduced by half.

FIG. 5 is a timing diagram of the non-modulated address bit streams of four stations A-D with 8-bit identifying addresses at the same transmission rates, which seek access to the common bus, in the sequential polling/arbitration method using signal bisection for a multinode communication network according to the present invention.

In FIG. 5, reference numerals 501, 511, 521, and 531 denote the bit stream waveforms of the identifying addresses of the contending stations A-D, reference numerals 502, 512, 522, and 532 denote the waveforms indicative of a transmissible state, reference numerals 503, 513, 523, and 533 denote the bit stream waveforms of contending identifying addresses, reference numeral 550 denotes the waveform of a bit stream shown on the common bus 1000, reference numeral 560 denotes the waveform of a local clock in each station, and reference numeral 504 denotes an example of a data communication stream of a station gaining access to the common bus.

FIG. 5 is a contention timing diagram of four contending stations having the following binary values of identifying addresses:

Referring to FIG. 5, each station waits for its own bit time in a period 50 just after a contention initializing point 10. In a period 51, the MSBs of the contending stations compete with one another. Here, the MSB values of stations A, B, and C are "Is", while that of station D is "0". Thus, stations A, B, and C continue their contentions for the common bus, and station D having a lower priority level is excluded from the subsequent contention. In a period 52, the addresses of stations A(500), B(510), and C(520) are shifted to the left, and the respective second bits are subjected to comparison. Since the second bits of stations A, B, and C are "1", "1", and "0", respectively, stations A and B continue their contention and station C relinquishes its contention.

In a period 53, neither station A nor B are excluded from the contention, since their third bits are both "1s". In a period 54, their fourth bits are both "1s", thus keeping both stations in contention as in period 53. In a period 55, station A has "1 ", and station B has "0", resulting in station B dropping out of the contention. In periods 56-58, a signal having gone through such bit comparisons for determining proceed/yield finally gain exclusive access to the common bus.

Therefore, as shown in FIG. 5, the bit stream of a common bus signal 550 is entirely equal to that of station A during the polling/arbitration period. Hence, since station A gains common bus access, waveform 504 is loaded as the control command/data of station A on the common bus 1000.

FIG. 6A is a contention operation timing diagram of Duty Cycle Modulation of the identifying addresses as shown in FIG. 6B in case of the different transmission rates. For example, the bit streams of the identifying addresses of three contending stations are illustrated in FIG. 6A.

In the prior art, a signal having a waveform duty cycle of 50% is defined as "0" and a signal having a duty cycle of 66% is defined as "1", to perform modulation. However, in the present invention, transmission rates can be increased by changing a duty value for signal modulation, thus improving upon the prior art.

That is, a 33 % -duty signal such as a waveform 650 is defined as "0", and a 66% -duty signal such as a waveform 651 is defined as "1", to thereby modulate a signal. Thus, when modulating a signal defined as "1 ", the length of the modulated signal can be reduced by about 30%, thereby increasing data transmission rates.

In FIG. 6, reference numerals 611, 621, and 631 denote the waveforms of the identifying address bit streams of contending stations A', B', and C, reference numerals 612, 622, and 632 denote the waveforms indicative of a DCM- transmissible state, reference numerals 613, 623, and 633 denote the waveforms of the bit streams of contending identifying addresses, reference numeral 643 denotes the waveform of a DCM bit stream shown on the common bus 1000, reference numeral 644 denotes the waveform of a local clock extracted from waveform 643 in each station, and reference numeral 645 denotes the waveform of a binary address stream decoded from signal 643 shown on the common bus 1000.

Stations A'(610), B'(620), and C'(630) enter bus contention by synchronization patterns 40. For this purpose, the stations wait for the bit times of a period 50' which begins an end point 10 of the synchronization pulses. Then, the MSB is compared with a corresponding bus signal bit. The bit time varies since it is proportional to a transmission rate, as noted from widths 41 and 42. The above synchronization patterns are signals for synchronizing all stations in a polling/arbitration contention state so that the stations can participate in a fair competition. In the present embodiment, a synchronization signal which activates a bus longer than a bit time is not considered as a normal signal. Using this characteristic, every station can be synchronized with interrupt polling and can participate in contention, without specific binary patterns.

Using these characteristics, a system intending an interrupt can issue a realtime request on a serial line (via a medium) by transmitting a brake pulse to a channel, enabling interrupt request and polling/arbitration by using serial lines. Every station can participate in the polling/arbitration so long as its synchronization pattern is detected.

The standby time is a predetermined time, i.e., a bit time, for which every station does not activate the common bus to allow responses to be detected depending on speed differences after the synchronization pattern detection. Past its own bit time, the station activates the common bus by its identifying address.

Since transmission rates of stations A' and B' are equal, while that of station C' is relatively low, the MSBs of stations A' and B' appear on the common bus 1000 earlier than that of station C' in a contention period 51 ', thereby rejecting station C' in the contention. That is, station C' should relinquish its contention without outputting its MSB to the common bus.

Stations A'(610) and B'(620) having the same transmission rates compete with each other in a contention period 52'. Here, station B' has bit "0" and station A' has bit "1 ", that is, station A' has a higher priority, thus excluding station B' from the contention. In a contention period 53' and subsequent contention periods, station A' experiences the above procedure repeatedly until the LSB comparison, and then achieves a priority for an exclusive common bus access.

Accordingly, only the modulated signal bit stream 612 of station A' appears on the common bus 1000.

FIG. 7 is a contention timing diagram in a case using Manchester encoding. In the figure, stations A "(700), B"(710), C"(720), and D"(730) have the following addresses:

In FIG. 7, reference numerals 701, 711, 721, and 731 denote the waveforms of the identifying address bit streams of contending stations A", B", C", and D", reference numerals 702, 712, 722, and 732 denote the waveforms indicative of a DCM-transmissible state, reference numerals 703, 713, 723, and 733 denote the waveforms of the bit streams of contending identifying addresses, reference numerals 704, 714, 724, and 734 denote the waveforms of Manchester-modulation bit streams participating in the contention, reference numeral 751 denotes the waveform of a Manchester-modulation signal occurring on the common bus 1000, reference numeral 752 denotes the waveform of a local clock, reference numeral 753 denotes the waveform of a bit stream decoded from waveform 751 shown on the common bus 1000, and reference numeral 705 denotes the waveform of a command or data from a station gaining access to the common bus.

Each station waits for its own bit time in a period 50" just after a contention starting point 10. In a period 51", contention starts with the MSBs. Here, since the bit values of stations A", B", and C" are "1s", and that of station D" is "0", the first three stations continue their contention and the latter one having a lower priority relinquishes its contention. In a period 52", the identifying addresses of stations A", B", and C" are shifted to the left by one bit. Thus, the second bits are compared to one another. Since stations A", B", and C" have bit values of " 1 ", "1 ", and "0", respectively, stations A" and B" remain in contention, and station C" relinquishes its contention.

In a period 53", the third bit values of stations A" and B" competing with each other are both "Is", so there is no drop-out as described above. In a period 54", there is no drop-out either, since compared bits are both "Is".

In a period 55", station A" has a bit value "1", and station B" has a bit value "0", thus station B" is eliminated from the contention. In a period 56" and subsequent periods, a station having gone through the procedure to a final period 58", i.e., LSB period, obtains an exclusive access to the common bus. Therefore, the waveform of a common bus signal 751 coincides with Manchester-modulation waveform 704 of station A" completely, and then with waveform 705 of a Manchester-modulation bit stream of station A" gaining access to the common bus is loaded onto the common bus 1000.

FIG. 8 is a contention timing diagram in the case of a transmission of addresses and data modulated using a three-level modulation method.

In a system for performing the three-level modulation on addresses and data to be transmitted, a shifted DC-level, mixed waveform 860 including a clock, a synchronization signal, and power is sent to the common bus and each station extracts and divides these signals to be used for modulation and demodulation, so that all stations can share the clock and the synchronization signal.

In FIG. 8, reference numerals 805, 815, 825, and 835 denote the waveforms of three-level modulation addresses of stations gaining bus access, reference numeral 851 denotes the waveform of a three-level modulation signal occurring on the common bus 1000, reference numeral 852 denotes the waveform of a local clock extracted from waveform 851 occurring on the common bus 1000, and reference numeral 853 denotes the waveform of a bit stream decoded from waveform 851 occurring on the common bus 1000.

Bus access contention of FIG. 8 is implemented in the same manner as that described referring to FIG. 7, except for a method for modulating addresses and data.

FIG. 9 is a schematic diagram of an embodiment of a sequential polling/arbitration device using signal bisection, for a multinode network according to the present invention.

The sequential bisect polling/arbitration device for a multinode network according to the present invention includes a serializer 9010 for receiving and identifying addresses and serially generating a bit stream according to a transmission clock, a modulator 9020 for receiving the serial bit stream and outputting a modulated pulse sequence in a predetermined modulation method, an interface portion 9030 for outputting one of the received modulated pulse sequences and its own common bus request and outputting in the form of wired-ORs to a serial common bus, a comparing/determining portion 9040 for determining the presence or absence of a common bus request from another station, and a controlling portion 9050 for generating a bus access signal after clock control and contention end the processes of a corresponding station, and controlling a bus access.

The serializer 9010 is constituted of a free-sealer 90C, and a parallel-input and serial-output (PISO) shift register 90D of a length larger than an address length by one bit.

The free-sealer 90C receives the output of a programmable clock generator

90 A, dividing the output by a predetermined value, and outputting the divided value to the shift register 90D, the modulator 9020, and a counter 90N of the controlling portion 9050. Division by the predetermined value is for determining a predetermined duty cycle width within a bit time during modulation.

The MSB of the shift register 90D is set as "0" to obtain a standby time and an identifying address is stored in the subsequent bit positions.

The reason for sparing the standby time is to identify a contention signal from another station whose transmission rates are higher than those of the corresponding station.

The common bus interface portion 9030 includes an OR gate 90F and an output tristate buffer 90G, and activates the common bus only if the OR gate 90F applies a modulated waveform or a synchronization pulse generated from the corresponding station as a control input of the tristate buffer 90G.

The comparing/determining portion 9040 has a synchronization pulse detector 90H, a priority level comparing and determining AND gate 90 J, and a spike pulse killer 901.

The synchronization pulse detector 90H detects the end portion of a synchronization pulse on the common bus, and outputs the detected portion to the controlling portion 9050.

The AND gate 90J generates a contention cancelling pulse unless its own signal is normally transferred to the common bus, and outputs pulse generated during a signal transition period to the pulse killer 901.

The controlling portion 9050 is constituted of a shift counter 90N for counting the number of shifts, a contention enabling flipflop 90K, a common bus access receiving flipflop 90L, an AND gate 90M an OR gate 90P, and a synchronization pattern generator 90Q.

A contention request signal 9501 externally generated sets the common bus access receiving flipflop 90L via the OR gate 90P. The output of the common bus access receiving flipflop 90L is applied as an input of a port D of the contention enabling flipflop 90K, and sets the port D when a synchronization pulse is generated. Then, the reset of the free-sealer 90C and the shift counter 90N connected to the synchronization signal are released. Thus, a contention starts.

When the contention starts, the above described common bus access contention process is operated on an identifying address temporarily stored in the shift register 90D, from MSB to LSB sequentially. If the procedure is completed, an access privilege signal is generated to the AND gate 90M.

From the moment when this control privilege signal is secured, a corresponding station becomes a master of the common bus, thus gaining common bus access until its own access priority is unnecessary and thus relinquished or just before a synchronization pulse generated by a request from another station is identified.

In the above process, when contention fails, the contention enabling flipflop 90K is reset, in turn resetting and thus initializing the shift counter 90N and the free-sealer 90C.

In FIGS. 7-8, it is clear that the present invention can be implemented by wired- AND operations in the same manner for wired-OR as described above, and thus its detailed description is omitted.

In this operation, an identifying address is compared with a common bus signal, from MSB to LSB sequentially. If the bit value of the identifying address is different from that of the common bus signal, contention is canceled. If they are equal, contention continues until an LSB comparison. As a consequence, the present invention reduces the number of competitors by a half, and the identifying address of a station with the highest priority can be identified by n comparisons among 2ⁿ stations.

The above embodiments of the present invention are described in relation to contention among a predetermined number of stations. However, the present invention is not limited to those embodiments, and it is clear that many variations are possible within the scope and spirit of the present invention by anyone skilled in the art. Industrial Applicability

According to the present invention, each bit of an identifying address is compared with a corresponding bit of a common bus signal from MSB to LSB serially, and then the priority of each station is determined. Thus, a time for assigning a bus access is reduced and a bus access assigning method becomes simple, compared with the prior art. As a result, the present invention is effective in that high-level application protocol and operation are facilitated and real-time processing is enabled on a multi-serial line.

The present invention can be applied to a multicommunication system for transmitting multiple data wireless or fiber-optically, as well as a multinode network system having a plurality of stations connected by lines as described above.

Claims

What is claimed is:

1. A sequential polling/arbitration method using signal bisection for a multinode network having a plurality of stations with N-bit identifying addresses, comprising the steps of:

(a) generating a polling/arbitration initializing signal indicating the start of contention for access to a common bus by every station requesting access; and

(b) logically operating each bit of the identifying addresses of all stations participating in said common bus contention in a polling/arbitration initializing signal period and comparing said logically operated address bits with common bus signal bits, wherein contention is canceled or continues based on the result of said comparison, so that a station having the highest priority is quickly identified among 2^N stations by N comparisons at most, resulting in rapid priority identification.

2. A sequential polling/arbitration method using signal bisection for a multinode network as claimed in claim 1 , further comprising the step of granting priority to the first responding station using at least a single bit of the identifying address thereof, before said step (b).

3. A sequential polling/arbitration method using signal bisection for a multinode network as claimed in claim 1 , wherein said step (a) further comprises the step of logically summing transmission bits of contending stations so that the result of the logical sum becomes a common bus signal which activates said common bus only with the logic state of "1 " among the values of address bits, to prevent common bus collisions beforehand.

4. A sequential polling/arbitration method using signal bisection for a multinode network as claim 1 , wherein said step (a) further comprises the step of logically multiplying transmission bits of contending stations so that the result of the logical multiplication becomes a common bus signal which activates said common bus only with the logical state of "0" among the values of address bits, to prevent common bus collisions beforehand.

5. A sequential polling/arbitration method using signal bisection for a multinode network as claim 1, wherein the priorities of said identifying addresses dynamically vary by changing transmission rates.

6. A sequential polling/arbitration method using signal bisection for a multinode network as claim 1 , wherein common bus access privilege is granted to a station having an identifying address of the relatively higher priority, in said step (b).

7. A sequential polling/arbitration method using signal bisection for a multinode network as claim 1 , wherein common bus access privilege is granted to a station having an identifying address of the relatively lower priority, in said step (b).

8. A sequential polling/arbitration method using signal bisection for a multinode network as claim 1 , wherein said identifying addresses are sequentially compared from the most significant bit to the least significant bit in said step (b).

9. A sequential polling/arbitration method using signal bisection for a multinode network as claim 1, wherein said identifying addresses are sequentially compared from the least significant bit to the most significant bit in said step (b).

10. A sequential polling/arbitration device using signal bisection for a multinode network, comprising:

a serializing portion (9010) for receiving an identifying address and generating a serial bit stream based on a transmission clock signal;

a modulating portion (9020) for receiving said serial bit stream and outputting a modulated pulse sequence according to a predetermined modulation method;

a bus interface portion (9030) for receiving one of the modulated pulse sequences according to said modulation method and a predetermined common bus access request and outputting a wired-logic operation value to a serial common bus; a comparison and determination portion (9040) for receiving one of said modulated pulse sequences and a common bus signal to identify contention priority, detect a common bus access request from another station, and generate a signal for ascertaining existence of a contention; and

a controlling portion (9050) for receiving said common bus access request, said contention existence ascertaining signal, and a predetermined common bus access contention request, and for controlling said transmission clock signal to be continuously provided only during contention, and generating a bus access signal after the contention, so that a bit stream acquiring a common bus access is output to the common bus when said bus access signal is generated.

11. A sequential polling/arbitration device using signal bisection for a multinode network as claimed in claim 10, wherein said logic operation is a wired logical sum between a common bus and a station in said bus interface portion (9030).

12. A sequential polling/arbitration device using signal bisection for a multinode network as claimed in claim 10, wherein said logical operation is a wired logical multiplication between a common bus and a station in said bus interface portion (9030).

13. A sequential polling/arbitration device using signal bisection for a multinode network as claimed in claim 10, wherein said modulating portion (9020) modulates said serial bit stream using a Manchester encoding method.

14. A sequential polling/arbitration device using signal bisection for a multinode network as claimed in claim 10, wherein said modulating portion (9020) modulates said serial bit stream using a duty cycle modulation method.