GB2236459A - Priority-oriented bus allotment system - Google Patents

Priority-oriented bus allotment system Download PDF

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Publication number
GB2236459A
GB2236459A GB9017898A GB9017898A GB2236459A GB 2236459 A GB2236459 A GB 2236459A GB 9017898 A GB9017898 A GB 9017898A GB 9017898 A GB9017898 A GB 9017898A GB 2236459 A GB2236459 A GB 2236459A
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Prior art keywords
bus
priority
participant
participants
information
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GB9017898A
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GB2236459B (en )
GB9017898D0 (en )
Inventor
Gerhard Wergen
Herbert Muller
Peter Neumann
Hans-Peter Stein
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Diehl Stiftung and Co
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Diehl Stiftung and Co
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Abstract

A priority-oriented bus allotment system is designed with low circuitry expenditure for high flexibility and arbitration speed. For this, the lines a of the data bus D are initially fixedly associated with the individual bus participants N for the transmission of an instantaneous priority message P. In each participant N a check is made as to whether its own instantaneous bus access information-dependent priority P is of higher weight than that of all the simultaneously received priority messages P an from the other bus participants N. In this case, for the duration of the exchange of data blocks IB by way of the data bus D the issuance of priority messages P in all the participants N is blocked. Upon simultaneous presence of equally high variable (software) priority in several participants N a circuitrywise predetermined participant priority PK decides the bus access between these participants N. <IMAGE>

Description

E -4 ES G3 A PRIORITY-ORIENTED BUS ALLOTMENT SYSTEM This invention relates

to a bus allotment or allocation system for a number of participants of a 5 system bus.

A bus allotment system of this type is disclosed in the article by G. Farber "Ein dezentralisierter fairer Bus-Arbiter" ("A decentralised fairer bus arbiter") in ELEKTRONIK 1980, No. 8, pages 65 to 68, there in particular paragraph 1. "Zuteilungs-Verfahren" (Allotment method).

What tends to be disadvantageous with known methods of bus access allotment or allocation is more especially the fact that these methods are relatively inflexible, because they are based substantially on priority specifications for the individual peripheral participants accessing the bus. Also, in such methods, a genuine flexibility does not seem achievable in that the priorities associated with the individual participants, for example in accordance with a bus access which is sought after but which has not yet been achieved, can be variable, in order, in practice, not to preclude completely a participant originally assessed with low priority from the bus access. The conventional arbitration or selection systems tend to be, in addition to this, disadvantageous in practice insofar as they usually need a special arbitrator component (module) for the interrogation or call-up of the individual peripheral participants, which component then also undertakes the bus access control. The use of special circuitry or units for the performance of superordinated and secondarily-ordinated (subordinated) tasks causes, however, a large space requirement on a circuit board, not only for this additional circuitry expenditure, but also for numerous additional control lines besides the 2 actual data bus of the bus system.

This may have a particularly disadvantageous effect when, for the realisation of a compact, efficient microcomputer design concept, participants of the most varied type (such as more especially signal processors, special hardware circuits and/or analog and digital input equipment - for instance sensors - and output equipment for instance control circuits) with high data throughput have to co-operate by means of data-block transfers.

An aim of the present invention is to design a bus allotment system in such a way that, despite variable task-dependent bus access priority of the individual system participants, with a relatively narrow system bus, (thus with seemingly the least possible control lines parallel to the actual data bus) a rapid and seemingly unequivocal arbitration may be realised without the expenditure of additional control components or modules for the bus allotment.

According to the present invention there is provided a priority- oriented bus allotment or allocation system for a number of participants of a system bus which, in addition to a data bus for transmitting word- serial /bitparallel items of information, is equipped with control lines, characterised in that with each participant at least one of the lines of the data bus is associated individually for the transmission of its priority message to all the other participants, in that each participant is equipped with an interrogation circuit for the comparison of its priority message with the priority messages appearing simultaneously on the data bus, of all the other participants, and in that the participant whose priority message appearing on the data bus has the highest degree or urgency blocks the system bus for the acceptance of further priority messages and transmits an 3 item of information held ready, by way of the data bus, to selected other participants and then switches the data bus free again for the reception of the priority messages of all the participants.

In accordance with this solution, the data bus, so long as no information transfer is being effected, is available to all the participants simultaneously for the parallel transmission of their instantaneous busaccess priorities (if a bus acce ss is at all instantaneously desired). Each participant supplies not only (by way of at least one line of the data bus fixedly associated with it) its own instantaneous priority message to all the other participants - interrogating the entire data bus; each participant compares, in addition to this, its own instantaneous priority with all the other participant priorities, so that each participant can independently ascertain whether its access priority in the system bus is, instantaneously, the highest or not.

If this is not the case (i.e. the access priority of the particular participant is not the highest), the next arbitration cycle is awaited which follows directly on the information transfer instantaneously to be initiated.

If, however, a participant ascertains that it has the highest priority, it occupies by itself the bus access, so that the arbitration is initially concluded and bus access is forbidden to all the other participants. Should several participants in the instantaneous arbitration cycle have the same information-dependent priority, then that participant which has, moreover, the highest hardware priority acquires the bus access. Each hardware priority is fixedly predetermined circuitrywise (for example by means of manually settable switches), namely in such a way that it occurs only once within the system. In this way, even in the case of identical software priorities, the bus access is in actual fact 4 made possible only to one participant at one time. The lines of the data bus c-ire blocked by this now for the duration of the immediately following information transfer for priority Information. The information transfer begins with an item of control information, in which details regarding the other participants to be addressed are contained, as well as details regarding the processing to be effected there and the length of the data blocks transmitted thereupon. With the issuance of all the queuing information data blocks onto the data bus, the participant which has acquired the bus access switches the data bus free again for the simultaneous reception of priority messages from all the participants connected to the system bus, and there begins the next- following arbitration cycle, and thus the issuance of the priority messages of all the participants onto the lines of the data bus associated with them, and the comparison in each of the connected participants of all the priority messages with its own appearing priority. if, instantaneously, each participant issues a priority message of the content "no bus access necessary", there directly follows a new such arbitration cycle, so that in practice no lost times occur. As soon as only one participant needs the bus access, it receives it; if several participants simultaneously wish bus access, all those which ascertain that they instantaneously do not have the highest bus-access priority switch themselves off again at once.

Such a system is evidently extremely economical with respect to the expenditure on lines in the system bus and with respect to the necessary arbitration times. In particular, no superordinated control circuit is needed for the arbitration and bus allocation. The system is also very flexibly expandable, since the number of connectable participants is only limited by how many data-bus lines in association with the respective participant are available and, depending on the information scope of the priority message, are needed for the priority coding. The system in its mode of operation is also independent of the character of the participants (processors or non-intelligent circuits), and it allows a bus claim or access irrespective of whether an item of information is to be fed into the bus or called up out of the bus, and irrespective of the number of other participants that the participant which desires bus access for distribution or collecting-in of its items of information wants to communicate with. Despite these multiple function possibilities, only a minimum of control lines in addition to the actual data bus is needed, since this is made use of successively for the arbitration and for the information transmission.

In order to shorten the arbitration time further, a data exchange is advantageously effected always along with intermediate storage in fast stores (RAMs) in the individual participants, if a participant is not itself already designed as a rapid hardware circuit. In this way, the information exchange is not dependent upon how fast the reception or delivery of items of processor information is; whilst the peripheral processor reads-in the information taken over from the system bus into the intermediate store, the next arbitration cycle can already take its course by way of the data bus.

This efficient bus allotment method is thus distinguished also by high run-off or tracking speed. There is needed basically only two timing cycles of the bus system: In the first timing cycle each participant gives its actual priority message by way of the data bus to all the other participants, and in the second timing cycle each participant recognises by itself that it has not won the arbitration - otherwise it precludes all the other participant from the bus access, in order to 6 transmit its information to the associated participant/s.

Additional alternatives and f urther developments as well as further features and advantages of the present invention will become apparent from the claims and, also from the following description of a preferred embodiment of - a bus allotment or allocation system of the present invention which is now described, by way of example only, with reference to the accompanying simplified drawings in which:

FIGURE 1 shows, in the manner of a two-pole block wiring diagram, the system bus for priority-graded data communication between different participants connected to the bus; and FIGURE 2 shows a time diagram for the operating sequence of the priority association in the bus system in accordance with FIGURE 1.

The system bus 101 shown in FIGURE 1 of the drawings carries a data bus D substantially of b bit width for the block transfer of binary coded items of information I, in particular of data blocks IB. For the characterisation of a transferred item of information I as data block IB, the system bus 101 additionally carries a strobe line, the potential of which during a data transfer changes its normal state, as described in more detail below. The instantaneous potential on a busy line Y indicates precisely whether by way of the data bus D items of information I are being transferred or else whether the data bus D is free for the exchange of priority messages P between the participants N connected to the system bus 101, which participants can be transmitters or receivers of data blocks IB. The synchronous control for the collaboration of the participants N is effected by way of a clock or timing line T.

7 Depending on the functions of the participants, in particular depending on the importance thereof for the function of a system, the items of information I to be exchanged (to be delivered and to be received) have 5 different priority value Pd. Thus, an item of information I has a higher priority value Pd if it is essential for the maintenance of the system function, compared with an item of information I which serves only for a monitoring or notification or advice purpose, without directly intervening in the further course or pattern of the system function. If different bus participants N simultaneously in traffic or in waiting with other participants N wish to transmit items of information I by way of the data bus D, initially the participant N having an information requirement which, in comparison with the other access demands, has the highest priority value Pd, obtains the bus access. In order to be able to judge, there is effected prior to the transfer of items of information I, by way of the data bus D, an exchange of the respective priority values Pd between the participants N. For this fixedly associated with each of the participants N are a number of lines a from the lines b of the data bus D, namely with each of the participants N other lines a. If the number n of participants N is thus supplied by way of the data bus D to the line number b, if thus with the number n of participants N priority lines a from the data bus D are associated, then the limit a x n < b applies.

In FIGURE 1 an optimum example of utilisation is entered, namely for a data-bus width of b = 32; with n = 16 participants N, to each one 2 lines (a = 2) can be made available for the exchange of the priority messages 8 P (2 x 16 =32).

Since each of the two lines a can carry a 2-bit item of information and the priority message P (as a result of the association of a = 2 lines) has a width of 2 bits, the information scope of the priority message P amounts to-four different binarily-coded values, one of which can be transmitted in a timing cycle by way of the data bus D to all the participants. If, in the timing cycle following thereon, a different value is transmitted, there emerges from the value sequence a two-figure priority item of information of the information scope of 4 bits. Advantageously, the lowest value (0) is defined as the highest priority, because this can most easily be called up or interrogated in circuitrywise aspects; with the result that the participant N which instantaneously desires no bus access at all issues as priority message P the highest value (15).

Each of the participants Nn as a rule has available a data source 102 (for example a measuring transformer and/or a signal processor) or a data sink 103 (for example a signal processor and/or a digital/analog converter), which are connected by way of a coupling circuit 104 to the system bus 101. To reduce the bus occupancy times, in each participant N a fast intermediate store (RAM) 105 can be provided, which receives the item of information I from the (or for the) data bus D when the transfer from the data source 102 (or into the data sink 103) would become too protracted (for example because it is a matter of a signal processor). The intermediate store 105 is, however, superfluous when the participant N has available a fast input store, such as for instance with a FIFO store of an analog/digital converter or with an input register in front of a digital/analog converter; or if a special circuit is realised which makes possible rapid access for the direct 9 data exchange.

The essential function of the coupling circuit 104 consists in realising, depending on the instantaneous requirements, the access to the system bus 101 for the reception or delivery of items of information I. For this, each bus requirement or demand for the issuance (or for the reception) of items of information I is linked with a priority message P, which is produced in the respective participant N in accordance with its use, for example in the course of obtaining and processing items of information I. In the depicted exemplified instance, the item of information Ii to be delivered by the participant Ni is linked with the associated priority message Pi, which is held ready in a priority store 106 (in two sequences of two bits d, d'). The actual item of information I to be transmitted is stored interinediately in an information register 107.

If none of the participants N has instantaneous bus access, i.e. if thus by way of the data bus D neither items of information I nor priority messages P are being transmitted, then the open-collector busy-line Y (in the depicted exemplified instance, FIGURE 2) carries high potential. In this way, in each of the participants N connected to the system 101, the priority store 106 is free for the delivery of the priority message P. This is effected in two consecutive timing cycles by the bit, sequence d-dl, issued successively onto the associated two lines of the data bus D. Thus, each participant N gives its actual priority message P onto the lines a, associated with it, of the data bus D, to which in each participant N a priority call-up or interrogation circuit 108 is connected. Circuit 108 receives successively the two bits d, d 1 of the serial priority message P of all the participants N, which simultaneously arrive by way of the associated line pairs a, and it determines whether the thus again composed priority message Pi of its own participant Ni has a higher degree of urgency than the priority messages P of the other participants N. If this is not the case, i.e. if by way of the other line pairs a 5 a higher priority message P than possessed by participant Ni (i. e. a higher priority message than Pi) enters and is made available, the interrogation circuit 108i (by way of a gate circuit 109) blocks a repetition of the issuance of the priority message Pi from the priority store 106; this is because obviously another participant N has a bus requirement for the delivery or reception of items of information I with a higher degree of urgency in the queue of participants waiting to access the bus.

If a participant Ni does indeed carry a priority message Pi with the highest degree of urgency instantaneously existing on the data bus D, but another of the participants N issues a priority message P of the same high degree of urgency, than the bus access is no longer decided solely by the priority message P coupled with the item of information I, but from the now equally important requirement that participant Ni which has the highest equipment priority Pki (fixedly predetermined circuitrywise) receives the adjudication for the bus access. This can be supplied from an identification transmitter K, which may be for example, a manually adjustable coding switch. It is to be ensured that each switching position occurs only once in the system, thus that each participant Nn receives a different identification Rn, graded in accordance with its importance within the framework of the overall function of the system.

If the so concerned participant Ni has realised that it itself has the highest software priority (and possibly in addition to this also the highest hardware priority in the case of several equally-high software priorities), 11 then, triggered by way of the interrogation circuit 108, on the busy line Y the potential is changed (symbolised in the exemplified instance of FIGURE 1 by reversal of a flip-flop 110). In this way, in all the participants N 5 the issuance of priority messages P is blocked (illustrated in FIGURE 1 by control of the gate circuit 109), so that now the data bus D is available f or the transfer of items of information I.

As first item of information, I a block of items of control information ICi is issued, by a gate circuit 111, behind a control store 112 in the participant Ni which has just obtained the bus access, being switched through. This item of control information contains information regarding which participant(s) Nn this participant Ni is to enter into communication with for the data exchange (delivery or reception of data blocks Ib). In FIGURE 1, shown by way of example, let this be the further participant Nn, which is shown only incompletely in the drawing at the top (in actual fact it is equipped in the same way as the participant Ni). The communication (s) participant Nn is individualised by its identification Kn. Moreover, the item of control information IC generated, for example, by the data source 102 contains for example, details regarding the number of timing cycles, after which the transfer of the actual data block IB will occur and how long this will be, as well as details regarding the treatment on reception of this data block, for instance with respect to intermediate storage and/or further processing in the receiving participant Nc.

Thus, all the participants n go onto reception for the destination identification Kn now transmitted by way of the data bus D, if a gate 113 is controlled through, because the potential on the busy line Y has been changed over, whilst on the strobe line S the previous potential 12 still appears (see FIGURE 2). First those lines a of the data block D are evaluated which carry (now no longer a priority message) the destination identification Kn for the following data block Ib. These can be the same lines a which were previously able to carry the priority message P, so long as the busy line Y is still stood on high (see FIGURE 2) i.e. is still at high potential. A comparator 114 issues an acknowledgement signal 115 to participant Nn when, and only when, the received requirement identification corresponds with its own identification Kn. Thus, by transmitting several requirement identifications Kn', several participants Nn' can simultaneously be addressed by way of an item of control information Ix.

As acknowledgement signal 115 advantageously there is served the answerback (acknowledgement) of the identification Kn of each of the addressed participants Nn, so that by way of a comparator 116 it can be checked 20 whether all the participants Nn have been reached which - should have been addressed by the actual item of control information ICi. It is advantageous if these addressed participants Nn at the end of the acknowledgement signal 115 deliver a defined or specific signal sequence, for 25 example by way of a specific number of timing cycles; a high potential and then transition to low potential. Even if this marking Is detected by the comparator 116, it switches over by way of a change-over switch 117 the potential previously appearing on the strobe line S (in 30 accordance with FIGURE 2 from high to low), and it simultaneously switches an issuance gate 118 for the data blocks IBi, now to be transmitted by way of the data bus D to the addressed participants Nn. These items of binary information on the data bus are thus characterised 35 as information data blocks IB in that (as in the depicted exemplified instance) the busy line Y is still at low potential and now additionally the strobe line S is at 13 low potential. At the end of the data-block transfer then both potentials are again raised, namely by control of the flip-flop 110 or of the change- over switch 117. In this respect, this item of end information can be contained at the end of the last data block IB; or else it may be contained in the data-block control details 1Bc, for example in the form of the length of the data blocks IBi following on the item of control information Ici.

In the receiving participants Nn, the delivery of the address acknowledgement signal 115 brings about the preparation of a release circuit 119, which then frees (with change-over of the potential onto the strobe line S) an input register 120 for the acceptance of the data blocks IBi thereupon appearing on the data bus D.

If, at the end of the transfer of data blocks IB, the potential on the bus line Y is again switched to high, then starts the next one of the described arbitration cycles to ascertain which particpant N has a bus requirement with the highest degree of urgency.

It is to be understood that the scope of the present invention is not to be unduly limited by the particular choice of terminology and that a specific term may be replaced or supplemented by any reasonable equivalent or generic expression. Further it is to be understood that individual features, method or functions related to the bus or bus allotment (allocation) system might be individually patentably inventive. In particular, any disclosure in this specification of a range for a variable or parameter shall be taken to include a disclosure of any selectable or derivable sub-range within that range and shall be taken to include a disclosure of any value for the variable or parameter lying within or at an end of the range. The singular may

14

Claims (10)

  1. include the plural and vice versa where sensible. The present invention
    may be that defined in the characterising clause of Claim 1. It is to be understood that any word or phrase derived from the German language of the priority document may be replaced or supplemented by a different English meaning where appropriate.
    S CLAIMS 1. A priority-oriented bus allotment or allocation system for a number of participants of a system bus 5 which, in addition to a data bus for transmitting wordserial/bit-parallel items of information, is equipped with control lines, characterised in that with each participant at least one of the lines of the data bus is associated individually for the transmission of its priority message to all the other participants, in that each participant is equipped with an interrogation circuit for the comparison of its priority message with the priority messages appearing simultaneously on the data bus, of all the other participants, and in that the participant whose priority message appearing on the data bus has the highest degree or urgency blocks the system bus for the acceptance of further priority messages and transmits an item of information held ready, by way of the data bus, to selected other participants and then switches the data bus free again for the reception of the priority messages of all the participants.
  2. 2. A bus allotment system according to Claim 1, in which each participant issues an information-dependent software priority message onto the data bus and supplements this by a participant-specific (hardware) priority identification when it is instantaneously not the sole participant which delivers into the data bus thehighest instantaneously occurring priority message.
  3. 3. A bus allotment system according to Claim 1 or Claim 2, in which each participant issues onto the line or lines, associated with it, of the data bus, in consecutive timing cycles of the system bus, a bit-serial priority message.
  4. 4. A bus allotment system according to any one of the 16 preceding claims in which after conclusion of the arbitration by way of the data bus items of information are transmitted which contain initially items of block control information and then the actual data blocks.
  5. 5. A bus allotment system according to any one of the preceding claims, in which that participant which by virtue of the instantaneously highest priority acquires the access to the system bus switches over a busy line, existing parallel to the data bus, until the conclusion of the block transmission of items of information by way of the data bus and then frees same again for the linewise association of the data bus with the individual participants for the next arbitration cycle.
  6. 6. A bus allotment system according to any one of the preceding claims in which the system bus in addition to the data bus carries a strobe line, and that participant which by virtue of instantaneously highest priority has acquired the bus access switches over the strobe line for the identification of the instantaneous transmission of actual information data blocks when a preceding transmission of items of block control information by way of the data bus is concluded and so long as the transmission of information data blocks is not yet concluded.
  7. 7. A bus allotment system according to any one of the preceding claims, in which each participant is equipped with an acknowledgement transmitter which issues an acknowledgement signal onto the lines associated with it for the arbitration of the data bus, when its participant identification is contained in an Item of block control information as address for data blocks to be supplied or called up, which the participant acquiring the bus access by virtue of highest priority issues, after winning the arbitration and prior to transmission of the information 17 data block, onto the data bus.
  8. 8. A bus allotment system substantially as herein described with reference to the FIGURES of the 5 accompanying drawings.
  9. 9.. A priority data bus allocation arrangement for a number of participants of a bus system, characterised in that each participant is able to hold a variable item of information (priority message) concerning its own level of priority, at a particular point in time, for access to the data bus for information transfer or retrieval, and each participant is arranged to evaluate at a particular point in time, the order of priority for this information transfer or retrieval in comparison with the instantaneous priority levels of the other participants, this evaluation being carried out in such manner that should a particular participant determine that, for the time being, it carries information at the highest priority, the system bus is blocked for the acceptance of further priority messages from the participants until information transfer or retrieval is performed between said participant carrying information of the highest priority and the desired participant or participants in communication therewith via the data bus, said priority levels being related to the content and therefore to the urgency of the information to be transferred or retrieved, the blocking of the data bus to acceptance of priority messages being cleared on completion of said information transfer or retrieval.
  10. 10. An arrangement as claimed in Claim 9 in which each participant has an additional fixed, preset item of priority information (hardware priority) related to the inherent nature or importance of the participant itself, said hardware priority being taken into account to determine which participant has access to the bus should 18 two or more participants carry a priority message of identical and highest urgency, the participant then having the highest hardware priority being permitted access to the bus.
    Published 1991 atIhe Patent Ofilce. State House'. 66171 High Holborn. London WC1R4TP. Further copies Tmy be obtained from Sales Branch. Unit6, Nine Mile Point Cwrnfelinfach. Cross Keys. Newport. NPI 7HZ. Printed by Multiplex techniques lid. St Mary Cray. Kent.
GB9017898A 1989-08-29 1990-08-15 A priority-oriented bus allotment system Expired - Fee Related GB2236459B (en)

Priority Applications (1)

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DE19893928481 DE3928481C2 (en) 1989-08-29 1989-08-29 Preferential decentralized Busvergabesystem

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GB2236459A true true GB2236459A (en) 1991-04-03
GB2236459B GB2236459B (en) 1994-01-19

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FR (1) FR2651345B1 (en)
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8490107B2 (en) 2011-08-08 2013-07-16 Arm Limited Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5546587A (en) * 1991-05-30 1996-08-13 Tandem Computers Incorporated Decentralized bus arbitration system which continues to assert bus request signal to preclude other from asserting bus request signal until information transfer on the bus has been completed
DE19509960A1 (en) * 1994-03-24 1995-09-28 Keba Gmbh & Co Computer bus for data transmission with priority access control
WO1996037849A1 (en) * 1995-05-26 1996-11-28 Jin Young Cho Sequential polling/arbitration method using signal bisection and device therefor for multinode network
DE10258469B4 (en) * 2002-12-09 2013-10-02 Volkswagen Ag Method and apparatus for data transmission in a distributed system

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1411882A (en) * 1972-03-03 1975-10-29 Nixdorf Computer Ag Methods and apparatus for control of data processing systems
GB2114789A (en) * 1982-01-07 1983-08-24 Western Electric Co Shared facility allocation system
US4672536A (en) * 1983-03-29 1987-06-09 International Business Machines Corporation Arbitration method and device for allocating a shared resource in a data processing system
GB2216368A (en) * 1988-02-24 1989-10-04 Ardent Computer Corp Bus arbitration method and apparatus

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3009308A1 (en) * 1980-03-11 1981-10-01 Siemens Ag Method and arrangement for transmitting data signals
DE3241777A1 (en) * 1982-10-29 1984-05-03 Siemens Ag A method for controlling access of a common bus line on datenuebertragungseinrichtungen
DE3407870C1 (en) * 1984-03-02 1985-08-14 Nixdorf Computer Ag Method and circuit for introducing a Datenuebertragungsverbindung
DE3413144A1 (en) * 1984-04-07 1985-10-17 Licentia Gmbh Digital local communications system with the logical structure of a loop
GB2167628B (en) * 1984-04-19 1988-06-22 Rational Computer bus apparatus with distributed arbitration
US4901234A (en) * 1987-03-27 1990-02-13 International Business Machines Corporation Computer system having programmable DMA control

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1411882A (en) * 1972-03-03 1975-10-29 Nixdorf Computer Ag Methods and apparatus for control of data processing systems
GB2114789A (en) * 1982-01-07 1983-08-24 Western Electric Co Shared facility allocation system
US4672536A (en) * 1983-03-29 1987-06-09 International Business Machines Corporation Arbitration method and device for allocating a shared resource in a data processing system
GB2216368A (en) * 1988-02-24 1989-10-04 Ardent Computer Corp Bus arbitration method and apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8490107B2 (en) 2011-08-08 2013-07-16 Arm Limited Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels

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Publication number Publication date Type
GB2236459B (en) 1994-01-19 grant
FR2651345B1 (en) 1995-07-07 grant
DE3928481C2 (en) 1994-09-22 grant
DE3928481A1 (en) 1991-03-14 application
FR2651345A1 (en) 1991-03-01 application
GB9017898D0 (en) 1990-09-26 grant

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