DE1947437A1 - Circuit arrangement for data transmission between a memory system and input and output devices of data processing machines - Google Patents

Description

Böblingen / September 16, 1969 ru-sk

Applicant: International Business Machines

Corporation, Armonk, N.Y. i0504

Official file number: New registration

File number of the applicant: Docket PR 968 013

Circuit arrangement for data transmission between a memory system and input and output devices of data processing machines

The invention relates to a circuit arrangement for controlling the transmission of information between a memory system and lines that are connected to input and output units of a electronic data processing system are connected and the information at different speeds and different transmission mode transmitted or received can·

Similar circuit arrangements have already been used in the known telex switching systems. Here will generally a single-character memory provided per subscriber line, with which it is possible, regardless of the

FR 968

009815/1605

BATH ORIGINAL

Transmission speed the reception or the forwarding of the pulse groups combined to write code to effect. The system or the memory can be designed so that the storage with a certain first speed and the withdrawal takes place at a second speed. For example, in the German Auslegek Scripture 1 275 088 such a circuit arrangement is known which is characterized in that the lines are each terminated with a one-bit memory, the central one Memory for each line has a permanently assigned memory cell of predetermined bit capacity and one between means arranged in the one-bit memories and the memory cells in cyclic order simultaneously with a one-bit memory and the assigned memory cell. it is switchable that this device when entering a message initially the first bit alone and later that in each case next bit stored in one-bit memory and all given. temporarily if bits already stored in the memory cell takes over, checks for their number and then stores them together in the memory cell for as long as until it is filled, and then put them together in the relevant message allocated part of the central memory and when outputting a message initially one of the .Bit capacity of the memory cell corresponding number of bits from the central memory and later all if necessary bits still stored in the memory cell temporarily

009815/1605

takes over, checked for their number and then separated from each other the next bit of the message to be output in the one-bit memory and any remaining bits as long as each stores in the memory cell until it is emptied, and that a computer the message header and the end of the messages to be transmitted and the bits relating to the other control commands at the same time takes over and processes with the input or output of these bits.

However, this circuit arrangement has the disadvantage that the security of the transmission for teletype memory switching systems Sufficient, however, not for data processing machines, where the transmission of information has to be particularly precise arrives.

The invention is therefore based on the object of a circuit arrangement data processing for the transmission of information between a memory and input and output units To create machines capable of transmitting information both at different speeds and at different speeds Types of transmission are permitted with very high transmission accuracy and when the transmission speed is changed does not require any change in the circuit arrangement.

009815/1605 BAD OPHGINAt.

The solution to the problem according to the invention is that a high-speed memory has a large number of memory positions each associated with a transmission line is, and that there is a second group of memory locations which contain control information relating to the exchange or the transfer of information between the transmission lines and the first group of memory locations controls and that the second group of memory positions during a scanning operation in dependence is sampled by the transmission speed and / or the transmission mode.

The advantage of the circuit arrangement according to the invention is that once a very high flexibility with regard to the possible transmission speeds of the lines and, on the other hand, a very large number of lines, e.g. up to 500 lines at one transmission speed of 50Ba-uds, controlled with a small amount of circuitry can be. In addition, when the circuit arrangement is modified, no circuit changes need to be made to become, since the changes solely by changing the group control words and line control words in the memory can be made.

The invention will now be illustrated with reference to in the drawings Embodiments described in more detail.

009815/1605

Show it:

1 schematically shows the general structure of a system according to the invention;

2 shows the structure of a group control word; Fig. 5 shows the structure of a line control word;

4 shows the composition of a scanning cycle in one embodiment;

5A shows the segment subdivision of a scanning cycle;

Figure 5B shows the structure of the segments appearing in Figure 5A;

Fig. 6 shows the logical arrangement of the line scan control;

Fig. 7 the device for serial / parallel conversion of characters and

8 schematically the switching unit for the data transmission between the high-speed storage and the central unit,

009815/1605

BATH: ^

1 shows the data transmission control unit 1, which mainly consists of the central unit 2 of a data processing system. This central unit comprises the characteristic elements such as pest value memory, main memory, selection channel and multiplex channel. The selection channel is connected to fast input / output units and can be connected to other data processing systems with the aid of the adapter 4 for a channel-to-channel connection. The multiplexed channel is connected to less rapid input-output units, and controls the transmission channel 2 to a ₊ its subchannels.

The transmission channel COC controls the transmission circuit with the aid of adapter units 5. Each of these adapter units controls a group of lines operating in different modes and at different speeds work. Operation can be either synchronous with clock pulses or asynchronous with "start-stop" transmission. if the transmission lines used over relatively long distances they are always connected to the adapter units via iModems 6 connected.

The transmission channel includes a high-speed memory HSS, which enables the storage of data, which come from the transmission lines or onto them are given. A queue register is used for the temporary storage of data from the high-speed memory to the Multiplex channel MPX transmitted data.

009815/1605

BADORlGINAt

The following describes the scanning process that controls the subject of the invention. The problem is receiving or sending data over different groups of lines that support the Carry out transmission in different modes and at different speeds. To this end, two Types of Control Words Stored in the High Speed Palcher used. First the group control word GCW is used, which e.g. can occupy 80 bits in the memory and in one example is shown in Fig.2. The function of the GCW is to control the scanning operation of a group of lines with them Features as will be described in more detail later. The GCW can be different, depending on whether the lines are in synchronous operation or transmitted in asynchronous mode. If the lines transmit in synchronous mode, this is determined by certain positions of the GCW, which are in front of the actual message. These positions are not in asynchronous operation present, but a binary bit position indicates that the stop bit is 1.5 times as long as the normal bit.

It may happen that the device according to the invention has to carry out the transmissions on lines which operate at a speed which does not match all other lines. In this case, a so-called 'line oscillator' ¹ LOSC of a generally known type enables the information to be received according to the speed on the line and the transmission of this information

009815/1605 ORIGINAL BATHROOM

onto the memory at a suitable speed. Certain positions of the GCW then indicate this transmission, which with the LOSC works.

First it is assumed that there is only one line type out of n lines is available that transmit at a speed of χ bits / sec. Because of the occurring on the line Distortion must be scanned the line several times during the transmission of a bit and the number of these Sampling operations N is either as a clock cycle on the transmission line or used as a sampling cycle on the receiver side.

The line must therefore be scanned xN times per see. the

1 10 ⁶ ■

Lines must therefore each χN. sec or —rr- ^ sec . In other words, the total sampling time of all

10 ⁶
Lines is the same - «- JM-see. It is now assumed that t (** sec) is the scan time of each line at each step, ie the basic cycle time during which a line can transmit or receive, since the line scan operation corresponds to the access to the line control word in the high-speed memory, such as from the following explanation. This time segment or step t is given by a tent base generator that controls all registers.

₁₀ 6 During an entire scan, therefore, ■ steps'

XHTJ

take place. If the number η of the lines to be scanned

10 ⁶ 1O ⁶
is less than -ττττ, ie - ■ - = n + m, then each line can be scanned xN times per see. In this case the scan proceeds as follows:

009815/160 5

The first step is the group control word access operation GCW in quick storage. The content of the GCW is used to define all of the sampling characteristics as described below will. After the first access step to the GCW, η lines are scanned in the following η steps. Each scanning one Line corresponds to the access to the corresponding line control word LCW. This leaves m-1 "spaces" in which no line is scanned * These spaces are used to interrupt the process, as described below. It can happen that this number of empty steps is too large, i.e. that the capacity of the system is not used sufficiently becomes (the number η of lines could be higher) or the number of samples N per bit and thus the Transmission accuracy can be increased.

If it is assumed in the above calculation that the number rrwr is less than the number of lines n, then this means that the number of scanning operations N per bit has been chosen too large and that it has been reduced must become. A minimum number of scans per bit is of course required, and therefore a maximum number determined by lines, if exceeded, more than one device according to the invention must be used.

Up to now, only the case was considered in which lines with the same characteristics were used. Now becomes the case described, in which various management groups with

009815/1605 BAD ORIGt ^ ^ -, _0Λ *

different features can be used. For example, some Lines run in synchronous operation and others in asynchronous operation. On the other hand, lines define different groups, which different adapters achieve. In any case, the total scan, which in the example chosen is the smallest Period is divided into several segments in which each line is scanned at least once. A segment is

P a part of the total scan which comprises the necessary scanning steps between two successive line scanning operations where the lines have the highest scanning speeds. If, for example, there are two asynchronous line groups, of which one group has to be scanned at a speed which is twice as high as that of the other group , then the total scanning is divided into two segments. The first group of lines, which must be scanned Nx times per see, is scanned for each segment, ie

) twice during a total scan. The second group of leaders is of course sensed only once during a total scan. These lines can be split in half across the two segments or they can be collected over one segment and the other segment comprises only the first line group. .

In short, the total scan is divided into segments so that the lines running in asynchronous mode are scanned Nx times per see (X ₁ is the number of bits per see

FR 968 015 009815/16 05

BATH

Line L. and N. the number of scanning operations per bit). Things are completely different for the lines running in synchronous operation, which only require one scanning operation per bit. This alone means that the overall scanning of the lines running in synchronous operation must be divided into several segments.

Looking at this division into segments, a GCW is assigned to each management group that has the same characteristics within of a segment in a manner similar to that relating to a line type. As already said, it can happen that a GCW-only part of the lines controls in a group that is spread over several segments. The following steps are according to the scanning operation of the lines are bundled in the same group or part of the group when the LCWs are in the high-speed memory addressed. Therefore there is only one for each group or each part of a group of lines of a segment GCW and a number of LCWs available. There may be a number of steps in each segment that are not used.

As stated earlier, some lines need to be taken during an overall scan can be scanned several times, while others can only be scanned once. From this point of view, the leadership group controlled by identical GCWs that require repeated sampling. This arrangement can of course be applied realize two different ways. In the first case, the same GCW is placed in several different memory positions

009815/1605 SAt>

and in the second case, a memory position belonging to a GCW is queried several times during an overall scan. This second implementation requires the use of additional storage locations in main memory which contain words to control the GCWs. During the first step, the data in such a memory position indicates the address of the various GCWs to be addressed later, W , thus enabling multiple access to the same GCW during an overall scan.

The distribution of the lines during a total scan goes from the following examples.

1 «example

500 lines of the same class transmit at one speed of 50 baud and must be due to the line distortion Scanned 15 times per bit, i.e. χ = 50 and N = I5. From it

1 1 results in the scanning of a line with 307 = Y5o, i.e. the

Total scanning therefore takes 1.555 ms. If it is assumed that a step lasts 1.875 / * - s, then a total

1,335 mns
sampling 1, B75 m / s »712 steps. Since a total of lines have been assumed, this number is sufficient to allow each line to be scanned 15 times per lake.

FIG. K shows the following "step" distribution: A GCW occupies one step at the beginning of the total scan, then 500 LCWs occupy

009815/1605 BAD ORIQfNAt

the following 500 steps, where each of the words mentioned corresponds to a line in the transmission process. The next 211 steps are spaces for which there is no GCW or LCW in the Quick storage HSS is available. After the "GCW" step, the LCWs can also be set differently than in the selected example, without thereby changing the result with respect to the corresponding scanning of the lines.

Of course, if the addresses of the 500 lines are not in the same order as the corresponding GCV / 's
there are also breaks in the order of the addresses.

2nd example

This example shows different classes of lines
considered, namely:

100 50 baud lines that run in start-stop mode

and require 21 samples per bit.
50 600 baud lines that run in start-stop mode

and require 7 samples per bit and
10 4800 bit / sec lines that run in synchronous mode

and thereby at least one sample per bit

require.

The 50 baud lines must be scanned every s - 952 # 4 ^ s, the 600 baud lines all

0098.15 / 1605

= / A-s, i.e. four times as often as the 50 baud

Lines and hence the total scan must be divided into 4 segments from the start, and the 600 baud lines are over each segment and the 50 baud lines only once over the whole scan distributed. Those with 4,000 bits per see im Cables running synchronously must, however, at least

' ^{s Ä 2o8} ' 5

once per scanning cycle, i.e. TOÖ ^{s Ä 2o8} '5 / ^ s are _scanned . The total scan must therefore be divided into 8 segments, each 119 / ^ s long. In this case, the 50 baud lines are only scanned once over the entire scan, the 600 baud lines are scanned every other segment, and the 4800 bit / s lines are scanned 8 times per total scan. Figures 5A and 5B show the distribution of the various steps that correspond to the GCWs and LCWs. "

5A shows the division of the total scan. If t = »1 # 075 / ^ s is the duration of one step, then the total ^{scan comprises 1.075 = 5} ° ^{8 steps} * these 508 steps. must be distributed over 8 segments in such a way that four 62-step segments alternate with four 64-step segments. The distribution of the mentioned steps is shown in Fig. 5B. The first segment comprises 63 steps. The first step is the GCW step, which controls the 10 lines with 4800 bit / s. Then shown are the 10 GCWs that. These to lines correspond, then the 600 baud lines that go through a GCW

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controlled / followed by 25 LCWs corresponding to 25 lines below the 600 baud lines. The twelve 50 baud lines can be set so that a one-step GCW is followed by twelve steps with LCWs corresponding to said lines.

This means that 50 steps are occupied in the first segment and 1.55 steps are free. For example, I3 LCW circuits are set in the following segment, which correspond to thirteen additional 50 baud lines, so that the 100 lines are distributed over the 8 segments. This results in the following structure for the second segment: One step GCW controls the ten 4800 bits / s lines and then the corresponding ten LCW steps, one step GCW controls the 25 600 baud lines that are not distributed through the first segment , and then the corresponding 25 LCW steps, a GCW controls the 15 50 baud lines and the 13 LCW steps corresponding to these lines. Thus, in the second segment 5I steps are occupied and 13 steps are free. This distribution is only used as an example, for example, the 50 baud lines can also be distributed to every second segment, ie 25 lines in every second segment. The same is true for the 600 baud lines that can be distributed over one segment, ie 50 lines on one segment and no line on the next segment. In the case of other distributions, the segments need of course not only include 63 or Gh steps, but can also include 80 or, for example

009815/1605 BAD ORIQiMAL

Include 47 steps. Sometimes it may be desirable to have a · ■ Line group not to be distributed to each segment, as one Step occupied by a GCW corresponds to each subgroup in a segment and it may be advantageous not to many steps to use. The only rule to be observed here is to take into account the fixed scanning speeds, by dividing the total scan into appropriate segments. The distribution of the lines on the Segments depends on the number of lines to be distributed; it can also be specified by the programmer. Consequently two basic rules must be observed in the above example: 1.) The 600 baud lines must first be scanned so that the total scan must be subdivided into 4 segments or a multiple of 4, and 2.) must then be in synchronous mode working lines are scanned at one speed which results in more than one scan per bit, so that the Gesaratabtastung is divided into at least 8 segments must become. In addition, the total scan can be divided into 16 segments. be subdivided, whereby also those intended for the GCWs Steps are used.

The circuit arrangement for scanning the lines is described below with reference to FIGS. At the beginning of the overall scan, the group control address register (21) GCAR contains the address of the first GCW in the high-speed memory HSS. This GCW is created in parallel from the

009815/1605 BATH ORIGINAL.

. High speed memory is called up and on the in Fig. 6 Register group 20, 22, 2j5, 24 shown is given. If that GCW is in the various registers, the first step is finished. Fig. 2 shows that part 14 (from bit 31 to bit 40) contains the address of the first line or of the data record adapter to be scanned first. This part 14 is over the line 28 is set in the data record adapter register (20) DSAR shown in FIG. This register can be accessed via line 34 the line to be scanned. From the GCW shown in Figure 2 it can also be seen that part 13 is the address of the first LCW of the high-speed storage HSS contains and this The address is changed to that shown in FIG. 6 via line 29 Line address register (22) LAR set. The register 22 then has access to the memory position which contains the first LCW, which corresponds to the first line to be scanned, which is determined by the content of the register 20 · The part 11 contains the number of lines to be scanned or the number of lines LC, which is dependent on the GSW, and is accessed via the Line 30 shown in Fig. 6 to the line number register (2}) LCR given. Part 12 of the GCW contains the number of empty steps and is sent to register 24 via line 31. the The number of these spaces is only available in the first GCW of the segment, as these steps are for an interruption at any point in time can be used within this segment, such as from the later description emerges.

009815/1605

•. - 18 -

In short, at the end of the first step, the corresponds to the first GCW in the segment, registers the number of lines to be scanned and the number of usable spaces and the position of the LCW corresponding to the first line to be scanned is addressed and the first transmission line scanned. The address of the first line to be scanned is made up of the address of the adapter unit and the Address of the line on this unit.

During the steps following the step of the first GCW, the first line to be scanned has access to the appropriate one LCW in the high-speed memory, and a data item is stored in the LCW or transmitted over the line. At the end of the first step of the LCW, the DSAR register becomes 20 µm advanced a value, whereby the second line can be scanned. In the same way, the LAR register 22 advanced by one unit and forwards the address of the second LCW into the high-speed memory. on the other hand the LCR register 2J was switched back one value. As already said, the content of these registers is changed under the control of a time base generator, its basic time unit the step is. The lines controlled by the first GCW continue to be scanned until the LCR register has the value 0 achieved. At this point in time, the scanning controller 27 switches the GCAR register 21, which then accesses the address of the second GCW of the first segment in the high-speed memory shows. The content of the GCW, i.e. the address of the

009815/1605

BATH

The first line to be scanned, the corresponding LCW and the number of lines to be scanned is added to the above Register 20, - 22 and 2 ^ given. It should be noted that the Space register 24 is only loaded by the first GCW in the segment. On the other hand, it can increase by one value at any time are switched back when a step is used which indicates an interruption and also indicates that during of the step is access to the high-speed memory by the interrupt register 55.

During the last GCW in the segment, register 25 on line J> 2. loaded with the position of bit 9 indicating the end of the segment. The above-mentioned register 25 outputs a signal to the scanning control 27, which says' that the spaces in the segment are to be reduced if the LCR register is 0. If the LCR register 23 is then 0 and the register 25 is indicates the end of the segment, the ISCR empty step register 24 is switched back to 0. Its content would correspond to the number of empty steps.

those in the first GCW, minus those for interrupt operations used steps.

The return to 0 of the register 24 then indicates that the GCAR register must be increased by 1 in order to obtain the address of the first GCW of the second segment. This process then continues while each segment is being scanned. At the last GCW of the last segment, register 26

009815/1605

loaded with bit 7 of the GCW and thereby the end of the total scan displayed. This bit has the same function as the bit within the segment, but also means that the GCAR register must contain the address of the first GCW of the first segment again, so that a next full scan can begin.

From the above description it can be seen that the same group of lines is addressed multiple times during an overall scan and that additional memory locations can be used which contain the addresses of the GCWs to be addressed included, thereby addressing a single memory location is made possible. A specific embodiment of the invention not described here includes additional ones Register to which the content of the additional memory positions is sent. In this exemplary embodiment a first step is of course assigned to access to one of the additional memory locations in order to save the to enter the information contained in the corresponding register. The next step is to access the first GCW which is designated in these registers, and the process then continues as above.

The advantage of such an arrangement is that this The arrangement allows the GCWs to be addressed in the high-speed memory HSS in the manner specified by the structure of the Total scan is determined, and not in sequence,

009815/1605

- 21 as is the case in the exemplary embodiment of the invention.

In the above description, the circuits were not explained in detail, which address the scanning control 27, since these consist of known circuits.

The individual in the transmission of characters via a The steps involved in the given line are described below in connection with FIG.

First, assume that a transfer operation is performed shall be. Bit 28 in the LCW of the line concerned is set to 1 (Fig.j5)> which means that the data in the memory position concerned are transferred to the corresponding line should be sent. The character to be sent is in the memory part 18 of the LCW, the buffer ADB, as shown in FIG is. According to the illustration in FIG. 7, the content of the ADB is transferred in parallel via line 29 to a shift register 58 set, which has an additional position immediately behind position 1.

As stated earlier, one bit is sent over the line only during a given number of scanning operations This line is sent, which are carried out at regular intervals and thus determine the duration of the bit. This number NS occupies part 15 of the GCW in Fig.2. Therefore changes'

009815/1605

the content of the register 38 does not exist as long as the line is not sampled a number of times NS. During subsequent scanning operations of the line, part 17 shows or SC of the LCW in FIGS. 3 and 7 shows the number of times carried out Scanning operations. With reference to Fig.7, this sample number becomes SC is continuously loaded into register 40, which is over line 41 returns the number to part 17 of the LCW, after the unit 42 has been advanced by the value 1. The sampling number SC therefore increases by 1 at every sampling operation forwarded. The output of register 14 becomes also given to a comparator 43, which is his other Input signal from part 15 of the GCW (Fig.2) receives the Indicates the number of scanning operations to be performed. When the number of samples is equal to the number of operations to be performed the comparator 43 sends over the output line 45 a pulse to the shift register 46, which then shifts the content of register 38 down one position. At the same time, the number of samples is reset to 1, and the bit that was in position 1 is reset to position shifted, the bit that was in position 2 to position 1, and so on. The output signal on line 45 of the Comparator 43 prepares the time gate circuit 47 in the same way and thus enables the bit that is in position 0 in the Register 38 was on line 48 and the output line 49. The bit in position 0 of register 38 does not go through gate circuit 50, which only prepares when its input line 5I has a 1 pulse

009815/1605

and thus indicates that a receive operation is in progress. When the bit has been sent, the new content of the register 38 is given over the line 52 to part 18 (ABB).

The operations described above continue in this way until the character of the LCW contained in part 18 is completely sent has been. At the end of the character transmission there is an Eirerbit, the so-called flag bit. When all the bits of the character have been transmitted over the line, register 38 will contain louder Zeros preceded by flag 1 in position 1. This arrangement is recognized by a system (in the Figure not shown), the content of the transfer buffer TB (see Fig.?) Or the LCW in part 18 of the LCW transmits. The content of the LCW was previously stored in register 53 * the so-called transfer buffer register TBR.

In connection with Table I and FIG. 7 describes how to send a character over the line.

009815/1605 bath

TABLE I.

REGISTER 33

I T

ADB (18)

C B (17)

T B 19

CD CD (O OO

cn ο cn

O
O
1
I » O
O
T
M. O
O
^A 5
ti O
O
Il O
O
^A 3
If 2 1 0 O
1
O
Il 0
T
1
Il i i! I! I. 0
^A 5
T
M. 0
^A 4
^A 5
ti 0
^A 3
^A 4
f | 0
^A 2
^A 3
If j 2 1 ! 4 2 1 1 T ^A 5 ^A 4 ^A 3 ^A 2 2 1 - ti
1 Il
T Il
^A 5 I *
^A 4 Il
^A 3 If
O. ft
1 If
T If
^A 5 Il
^A 4 Il
^A 3 O 1 T ^A 5 ^A 4 O
O
^A 2
If
If
tr
^A 2 α
O
^A 1
ti
H
Il
^A 1 S. 0 0 1 T ^A S ^A 4 O
^A 1
^A 2 0
S.
^A 1
■ 1 0 0 0
0 0 0
0 0 1
0 10
0 1 1
10 0
1 0 1 ^A 1 S. ^A 3 ^A 2 ^A 1 Il
^A 2 rl
^A 1 0 0 1 O O 1 T ^A 5 0 0 0 1 ^A 5 ^A 4 ^A 3 ^A 2 ^A 4 ^A 3 ^A 2 0 0 1 ^A 3 ^A 2 O
O
Q
If
Il
Il
O O O

Assuming that the line is in "start" -stop operation transmits, this means that the character begins with a start bit S, comprises 5 bits and ends with a stop bit, which is the For the sake of clarity, it is shown here as just one bit T. It is further assumed that 5 sampling operations per bit be performed.

At the end of a character there is an identifier bit 1. It is assumed that part TB of the LCW is replaced by a later procedure to be described has been loaded. The character in the TB is sent to the ADB part of the LCW.

In the following step the character is loaded into the register J> 8. During this step, the first bit, that is to say the start bit S, in position 0 of the register J> Q is sent via the output line 49 onto the line. Since the bit has to be sent after 5 scanning operations, the 0 in register 4o is equal to the display 5. At the end of this step, part 17 contains a 1, which means that the first scanning takes place for the second bit. Stay during the following step the content of the ADB and the register J> 8 unchanged, since the gate circuit 47 is closed and is only prepared when the sample number has reached the value 5. At the end of this step, the register 40 is at 2 and is switched on until it reaches 5 and then bit A ₁ can be sent over the line during the next step.

009 815/1605

• - 26 -

Step, the A- bit is sent over the line when the Gate circuit 47 is open, and the part 17 changes look 1 and thus indicates the first scan of the following sit. This process continues until all characters have been sent, and the recognition of the identifier bit, followed by zeros, enables the following contained in part TB of the LCW Send characters to the part ADB.

With continued reference to Pig.7, the various Described stages which are passed through during the reception of characters and where bit 29 of the LCW (Fig. 3) is set to 1 and thus denotes a receive operation. ■ The character arriving on the line is received bit for bit. At the Reception. A bit is only checked if the number of samples of the line has reached a number that is specified in part 16 of the GCW (Fig. 2) is included. This so-called scanning test corresponds to the scanning operation, during which the incoming bit on the line must be received. Hence one bit gets off the line received when the comparator 43 indicates the sample number or the contents of register 40 equals the GCW's scan check number. A flag bit is used before the line is scanned 1 in the ADB part of the LCW is set to a position such that bit 1 is pulled out of the last position when the whole sign has been received. The next stage corresponds to the first scan of the line, the contents of the ADB is transferred to register 38 via line 39 »

009815/1605

If the sample number is equal to the sample check number, the first is Bit loaded into the ADB part as well as into register j58 (the bit ' Receiving unit is not shown in the figure).

While the register is being loaded, a shifter causes 46 that the contents of the register j $ 8 to the low Positions is moved. It should also be mentioned that gate circuit & 7 is closed during reception and that the input 54 only with a transmission by a one-bit is excited. Register 34 is loaded as long as until all characters are sent. When the last bit is received from register 58, flag bit 1 takes the position 0 in the register. This opens the gate circuit 50, provided that the other input 5I also has an E ins bit des LCW has, from which it can be seen that there is a receive operation. If the gate circuit 50 is open, then it causes a one Line 56 the opening of the gate circuit 55 and the sign, which is stored in register 38 is written in parallel to the part 19, or in TB or in LCW via the bus 57. At the same time, the character is written to register 53, or TBR loaded so that it can be stored in main memory.

With the help of Table 2 and Pig.7 a device for Receipt of a start-stop character with 5 scanning operations described per bit, where SS = J5

009815/1605

TABLE II

REGISTER 38

ADB (1ß)

C B (17)

4 2 1

T B (1G)

0 0 0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0 1 0 1 0 0 1 0 1 0

0 1 1

^A 5

A,

FR 968 013

009815/1605

The flag "1" is first stored in the ADB part of the LCW, as already described. During the step associated with the first scan, this bit is loaded into register 38 in the same position. During the next step, which belongs to the second scan, the contents of ADB and register 38 are not changed. It only happens during the third scan that the first bit of the character, for example the start bit, is loaded into ADB and into register 58 instead of identification bit 1, which has been shifted by one position. The contents of ADB and register 38 are not modified until the third sample of the second bit A ^ which has been loaded into both ADB and register J> 8. The bits are still received and only when the identification bit "1" is in position θ of register 38, ie when the last bit T has been received and that the character has been transferred to position TB of LCW, as shown in Table 2 is seen.

Previously, a character that was to be sent over a line was Transferred bit by bit from the ADB part of the LCW via this line and a second part, TB of the LCW, which acted as a buffer transfer memory, was loaded into the part ADB when this was free.

In the following it is shown with reference to FIG. 8 how a character is loaded into the positions of tB or into the associated register .

009815/1605

If a line acts as a transmission line, then will transfer the character to be transmitted from the positions of the TB to the positions of ADB in the LCW. If TB is empty, will one bit, the so-called transmission buffer full bit (TBP), which takes position 2j5 in the LCW (Fig. 3), changed from 1 to 0. At this point, a request is made for the characters to main memory. As can be seen in Fig.8, caused the condition bit TBF = 0 the address of LCW in the request line, which is stored in register 22 (LAA) is to be transferred to register 58. The purpose of the register is to process requests from main memory HSS run regardless of the speed with which the requests are generated. It should be remembered that up to 25 steps pass before a character request is completed. When a request has been carried out, bit 24 of the LCW (Fig. 5) is set to 1, which means that " shows that there is a service request. While After the memory operation in register 58, a request is sent to the multiplex channel via output 59. If the Line address stored in register 58 in the first position is located, it is transferred to the buffer registers 60 and 61. In the interests of clarity, it was assumed that the circuit arrangement according to the invention cooperates with a multiplex channel from the central unit with 8-bit groups or bytes. This also means that the registers have 8 digits or positions. However, this is not a limitation of the invention, because there are also other bit

009815/1 60S

other configurations possible. Will ζ .- ^. accepted, that the address of the LCVi occupies 10 binary digits (see Fig. 2) ', then the address must be in two buffer registers, namely the registers 60 and 61 in Fig. 8 are stored. Then this address becomes the main memory of the central unit over the line 65 and entered in the register 66 on the other hand. A character that is then to be transmitted over the line of the corresponding LCW address is then transferred from the main memory and the multiplex channel via the bus 67 received. Since this character has 10 binary digits, it is in the buffer registers 62 and 65 saved. At this point in time, the previously described interruption will occur. Will the Scanning of the lines is completed, then a step for transmitting the Sign in the Rogistern62 and 63 partly occupied TB of the LCW, whose address is given via the bus 68 through the register 66. When the character has been transmitted, the bit 2 ^ or TBF of the LCW is set to 1 and the bit 2 ^ or SR to 0. Then this character can be over the line 69 bit for bit can be transferred into the ADB part of the LCW.

If the line works as a receive line, then will the character is loaded bit by bit into the ADB part of the LCW and then into the TB part, as described above. Then must the character can be transferred to main memory. The process of receiving is similar to that of transmission, except for the

009815/1605 BAO ORiOtNAL

194743?

Address of the LCW, which comes from register 22 (LAR), and that The character that is in TB is also displayed on output line 70 entered into register 58. In a known manner, a request becomes a multiplex channel via the output line 59 given. Then, when this request is in the buffer registers and the address in registers 60 and 61 and the character in registers 62 and 73, the contents of the registers are transferred to main memory registers via buses 65 and 71 Register given. It starts with registers 60 and 61, which contain the address

As can be seen from the above, there may be an interruption when the lines are scanned, causing a delay results in the scanning operation by one step. It can also be seen that there is an interruption when a character is stored in an LCW of the high-speed memory HSS must become. Another interruption occurs when a word has been completely stored in the high-speed memory HSS, E.g. an LCW that corresponds to another line. If it is now assumed that V / orte in the high-speed memory HSS 40 binary digits, then these 40 bits are first in 5 buffer registers 60, 61, 62, 63 and 64 byte for byte over the Line 67 (Fig. 8) given. Therefore there is an interruption step before, which causes that the contents of the 5 buffer registers in the desired locations of the high-speed memory HSS be transmitted. In fact, there is an interruption

Docket FR 968 013 0 0 9 815/1605

BADORtQtNAt

if there is access to the high-speed storage HSS, namely in a Body that differs from that required at the time Time is reached by the scanning process. In addition, other interruptions can also be made that have not been described. For example, an interrupt step occurs when words are removed from the fast store for test purposes HSS (e.g. an LCW or a GCW). With each interruption the scanning process on the lines is set and a step is reserved for this interruption. During this step the registers GCAR, DSAR, LAR and LCR, which are shown in Fig. 6, are left unchanged and only the content of the ISCR register is decreased by one, indicating that one of the empty steps would be used,

Docket FR 968 013 0098 15 / 160S

Claims (1)

Godfather's sayings 1. Circuitry for controlling the transmission of Information between a storage system and lines connected to input and output units of a electronic data processing system are connected and the information at different speeds and can transmit or receive different transmission modes, characterized in that, that a high speed memory (HSS) has a group of memory locations, each of which is assigned to a transmission line, and that a second group of memory positions is present, the Contains control information (GCW) that controls the exchange or transfer of information between the Transmission lines and the first group of memory positions controls and that the second group of memory positions during a scanning operation depending on the transmission speed and / or the transmission mode is scanned. 2. Circuit arrangement according to claim 1, characterized in that an elementary step during the scanning cycle, while- 009815/1605 .... FR 968 012 "v - - -..; there is access to the second memory positions, immediately followed by further elementary steps during which the lines are scanned with ingenious transmission modes and speeds. 3 «circuit arrangement according to claims 1 and 2, thereby characterized in that the second group of memory positions, control data and memory positions of the first Group, the scan of the first group immediately following the access to the second group. k. Circuit arrangement according to Claim 3, characterized in that additional steps are assigned to the access to memory positions of a third group which control the access to the second group, this access to the second group being carried out as a function of the control information of the third group. 5. Circuit arrangement according to claims 1 to 4, characterized characterized in that one or more scanning steps for Interrupt can be used to store the data to be transferred over a line in the memory positions to get to the first group. 6. Circuit arrangement according to claims 1 to 5, characterized marked; that scanning takes place when 009815/1605 Fn qf, 8 01 "5 BAD ORfGtNAt none of the lines in transmit or receive status is. 7. Circuit arrangement according to claims 1 to 5, characterized in that a at the beginning of the overall scanning Group control address register (21) the address of the first group control word (GCW) in the high-speed memory (HSS) and that this group control word is given in parallel to a register group (20, 22, 23 and 24). 8. Circuit arrangement according to claims 1 to 7, characterized in that each memory position in the second Group contains the control information for a group of lines that both have the same transmission speed as well as have the same transfer mode and that they still have the corresponding memory position in the first group contains. Docket FR 968 013 0098 157 1605 BAD ORfGINAt