DE1221278B - Phase-pulled oscillator for use in regenerative amplifiers for PCM transmission systems - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. GL:

H03k

German KL: 21 al - 36/12

Number: 1221278

File number: St 22463 VIII a / 21 al

Filing date: July 28, 1964

Opening day: July 21, 1966

The invention relates to an oscillator for use in regenerative amplifiers for PCM transmission systems, phase drawn by randomly arriving periodic signals.

The expression "randomly arriving periodic signals" refers to signals that not always present and the z. B. formed by periodic signal trains separated by times during which there is no signal or by signals of constant duration, which in digital form (PCM, delta modulation, etc.). With a PCM system, the Transferring information in time sequence in the form of numbers expressed in a binary code, where a fixed time period or time slot is assigned to each code signal. In general the number 1 is represented by the transmission of a pulse that has a form factor of 0.5, and a digit 0 in that no signal is transmitted.

When transmitting, the timing signals that set the times are used by the various digits are assigned, generated by a very stable clock. During the transfer, the Communication signals are subjected to attenuations of amplitudes and phase distortions, so that it is necessary is to regenerate them in amplifiers. The amplifiers contain a simplified local one Clock that z. B. is synchronized by the message signals. It is known as a local Clock to use a phase-drawn oscillator. *

It is also known that a phase-locked loop acts like a band-pass filter that is automatically applied adjusts the frequency of the incoming signals. It suppresses the phase fluctuations (jitter) and forms a frequency gate that follows the carrier frequency when these slow changes or is subject to Doppler changes.

The invention is based on the object of creating a phase-drawn oscillator for use in regenerative boosters for PCM transmission systems. This is achieved according to the invention in that the input signal and a locally generated clock signal are compared in a phase discriminator and then passed through a low-pass filter which emits a signal whose amplitude is proportional to the mean phase difference between the two signals, and that this signal and a A signal representing the mean value of the clock signals is applied to an integrating differential amplifier, the output signal of which is the frequency of the phase-pulled oscillator for use
in regenerative boosters for
PCM transmission systems

Applicant:

ίο Standard Elektrik Lorenz Aktiengesellschaft,
Stuttgart-Zuffenhausen, Hellmuth-Hirth-Str. 42

Named as inventor:
Jacques Vartanian, Paris

Claimed priority:

France 8 August 1963 (944121)

Clock signal generating oscillator controls, and that a frequency synchronization arrangement is provided that works when a desynchronization is determined in a manner known per se is, and at its one output a signal of the duration of the desynchronization pulse and on its other output emits a continuous signal in such a way that when a predetermined Phase deviation no longer phase-drawn oscillator from a cut-off frequency up to other limit frequency controllable and phase-adjustable again when the received frequency is reached will.

The invention will now be based on the exemplary embodiments shown in the drawings explained in more detail. It shows

F i g. 1 is a general block diagram of a phase-drawn oscillator according to the invention;

2 shows the frequency-voltage characteristic of the oscillator 100,

Fig. 3 different signal diagrams,

4 shows the circuit of the phase discriminator 110,

F i g. 5 is a graph showing the total time of the signals as a function of the phase relationship in the phase discriminator indicates

F i g. 6 another option for training the phase discriminator,

7 shows a first possible embodiment for a Low pass filter,

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F i g. 8 a second possibility for implementing a low-pass filter and

F i g. 9 shows a more detailed circuit of the differential integrating amplifier and the frequency synchronization circuit.

In Fig. 1, a phase-pulled oscillator according to the invention is shown, which is an oscillator or clock 100, a phase discriminator 110, the low-pass filters 120 ^ 4 and 1205, the integrating Differential amplifier 130 and frequency synchronization circuit 150.

For the following description it is assumed that the input signals applied to the first input 11 of the phase discriminator 110 are pulse code modulation signals. Some of these message signals are shown at 11a in the form of negative, square-wave pulses with an amplitude V and a shape factor of 0.5. These signals have already been regenerated in a known manner, but they are still subject to phase jitter and slow changes. The signals emitted by the clock 100 'are shown under 12 a as negative, square-wave pulses with a shape factor of 0.5 and are applied to the second input of the phase discriminator and to the low-pass filter 120B.

The phase discriminator 110 emits signals at its output 13, the duration of which is proportional to the Phase angle between the message signals and the clock signals. These signals are sent to the Low-pass filter 120.4 applied, which emits a signal with negative polarity at its output 14 a, whose amplitude M indicates the mean value of the phase shift.

"The low-pass filter 1205 is identical to the filter 120 Λ and emits a negative signal with the amplitude M ₀ at its output 14 b , which represents the mean value of the clock signal. As will be described below, the amplitude of the signal 14 α also fluctuates in relation to the number of message signals received during an average period The discriminator can output a signal of amplitude M ₀ if no message signal is received during an average period or if the two signals are 90 ° out of phase.

If message signals are received and if the phase deviation is not 90 °, then the amplitude M of the signal 14 a is greater or less than M ₀ according to the sign of the phase angle between the two signals. Signals M and M ₀ are applied to differential amplifier 131, which has two outputs, labeled R and Q. If M ~> M ₀ , then a positive signal appears at output R , and if M <.M ₀ , then a negative signal appears at output Q. Each of these two signals can go up to the maximum amplitude V in absolute value. These R and Q outputs are connected to integration circuit 132 which has an integration capacitor followed by an amplifier with high input resistance.

It is assumed that this amplifier has a voltage gain of 1 for simplicity of description. It follows that the circuit 132 emits a voltage at its output S which represents the time integral of the differential voltage (M - M ₀ ) and has an amplitude between - V and + V. This voltage is applied to the control input of the clock generator 100 via the line 16 and controls the frequency of the signals 12c.
In FIG. 2, the frequency / of the oscillator 100 is shown in a curve over the amplitude VS of the signal applied to the input. The frequencies / 1 and / 2 are those that are emitted when the integration capacitor

ίο is charged with + V or - V volts. If at one point in time the pulse train cells 12 and 12a have the same frequency f , one can see from FIG. 2 that the voltage at point S has the amplitude V. If these two signals still have a phase shift of 90 °, then M = M ₀ , and at the outputs !? and Q of the differential amplifier 131 no output appears. The system is then set and the signals are locked in phase. However, if by slowly changing the mean value of the phase angle between the signals moves slowly from 90 °, a voltage appears at one of the outputs R or Q and the value of the voltage at point S is changed in such a direction as to compensate for this phase shift will.

If there is a disturbance in the compared signals, e.g. B. an interruption of the signal 11a, the frequency of these signals when restarted can be completely different from the frequency at the time of the interruption, or the integration capacitor can be discharged during the interruption and causes a frequency shift of the clock 100. In both cases, the frequencies differ of the two signals by a value called the beat frequency. The output signal of the discriminator 110 is then, as will be explained further below, a signal which contains an alternating component which is superimposed on _{the direct current component of the value M 0.}

The lowest frequency of this superposition is the beat frequency. If the beat frequency is greater than the cutoff frequency of the low-pass filter 12QA, then one obtains M = M ₀ and the differential amplifier outputs no correction voltage to the integrator 132. The phase feedback loop can therefore not work if a certain value of the beat frequency is exceeded.

In order to avoid this disadvantage, the circuit described includes a frequency synchronization arrangement 150 which operates when a desynchronization is detected. It is assumed that the system for determining desynchronization, which is known per se and is therefore not described, emits a desynchronization signal when the oscillator is no longer out of phase. This signal is applied to input 19 of circuit 150. This signal 19 causes the frequency synchronization circuit to work, which outputs a continuous signal at its output 14b and a signal at its output 18 for the duration of the desynchronization pulse. The polarity of pulse 18 is such that the charge on the integration capacitor in circuit 132 is brought to + V. This brings the frequency of the oscillator to the value J _x (FIG. 2). On the other hand, the polarity and the amplitude of the signal which is emitted from the circuit 150 via its output 14 b corresponds to a negative one

Signal that occurs at output Q. When this voltage is applied to the integration capacitor charged to the potential + V by the signal 18, its charge is brought to the value - V , so that the oscillator covers a frequency range from J ₁ to J ₂ . As long as the beat frequency has a high value, the amplitude of the signal at the terminal 14a of the amplifier 130 is close to the value M ₀ , as already described above. On the other hand, this voltage increases in the vicinity of the synchronism, and it will be explained further below with reference to FIG. 9 it is described that the amplitude can exceed a certain value V-Vd , above which a positive signal occurs at the output R of the amplifier 131. This transmitted via the line 17 signal is used to suppress B present at the output signal 14 of the circle 150 so that this circuit is again in the initial state and the phase pull circuit operates again, as described earlier.

The above in connection with FIGS. The arrangement described in FIGS. 1 and 2 forms a system with two Feedback loops. The first of these loops ensures the phase relationship and the second the Frequency synchronization.

In the phase-locked loop, the error signal is formed by a signal that is proportional to the mean value of the phase angle between the input and the clock signals and the signal for the frequency correction, which is applied to the clock generator, is the time integral of the error signal. The amplitude of this signal fluctuates around the value of the voltage VS in accordance with the sign and the amplitude of the error signal. As is known, the higher the gain in the phase locked loop, the shorter the time to correct the phase of the oscillator. This is also the reason why, in practice, the gain of the amplifier with high input resistance in circuit 132 is selected to be higher than 1.

The elements that make up the phase-locked oscillator according to the invention will now be described form. The oscillator 100 is a symmetrical multivibrator of known type in which the two Bases are biased by the voltage VS, which is applied to the input 16, that the frequency changes according to this voltage.

Before the phase discriminator 110 is described, the duration of the clock and message signals should also be described more precisely than defined in connection with FIG. 1. It was for the sake of it For the sake of simplicity, assume that these signals have a shape factor of 0.5. However, this value can can hardly be observed in practice because of the phase jitter, and the phase discriminator is therefore constructed in such a way that it emits the error signals, regardless of the form factor of the signals applied.

In FIG. 3 shows some signals which are present in the phase discriminator UO during a period of three frame periods of duration T. These periods are denoted by T ₁ , T ₂ and T _3. A message signal received in time slot T ₂ is shown under 3.1, and the clock signals emitted by oscillator 100 during time slots T ₁ , T ₂ and T ₃ are shown under 3.2. All of these signals have negative polarity and an amplitude V. Their duration is designated A ₀ for the input signals and A ₁ for the clock signals. One can further derive: B ₀ = TA ₀ and B ₁ = T- A ₁ .

The phase angle between the two signals is φ and is denoted as a fraction of the time T. In order to avoid ambiguity about its sign, it is always measured in the positive sense and gives the time delay between the leading edge of the clock signal and the leading edge

ίο of the message signal.

In Fig. 4 shows the phase discriminator 110, which contains the AND circuits U1, 112, the inverters 113, 114 and the OR circuit 115. In the drawing, an AND circle is symbolically represented as a circle, an OR circle by a circle with the number 1 and an inverter by a square. If C is a message signal of duration A ₀ , which is present at input 11, H is a clock signal of duration A ₁ , which is present at input 12

is applied, and D is the signal that appears at output 13, then it can be seen that the circuit 110 is performing the following logical operation:

D = (CScTI) W (CScH).

This logical operation can be expressed in a simple manner in that the discriminator Only emits signals when only one of the signals is present.

30 "In Fig. 3 under 3.3 the output signal 13 is shown, which is obtained when the phase angle between the clock signal and the message signal is as it corresponds to diagram 3.2. It can be seen that the discriminator during the time slots T ₁ and T ₃ emits a single signal during which there is no message signal and that the duration of this signal is ^. On the other hand, it emits two signals during the time slot T ₂ during which a message signal is present, and it can be seen that the total duration of these two signals

amounts to. The phase angle shown in 3.2 is smaller than T / 2. In the diagram of the clock signals shown under 3.4, the phase angle is greater than T / 2, and one obtains for the duration of this output signal during the time slot T ₂ :

If one now calculates DT for all phase angles between 0 and T, one finds that the total duration of the output signals is constant for some values of the phase angles.

In FIG. 5 shows the curve D _T = f (φ) , and it can be seen that this curve is represented by four straight line elements and that for phase angles between 0 and A ₀ -A ₁ and between B ₁ and A ₀ the value of D _T is constant. But when

the two signals are of equal length and have a shape factor of 0.5, then these phase angle zones in which D _{T is} constant disappear, and the curve has the shape of an isosceles triangle with a maximum value of D _T corresponding to T.

Cp ₁ and φ ₂ denote the phase angles at which the output signal of the discriminator, if a message signal is present, corresponds to the output

signal is the same, if there is no signal then receives man

φ ₁ - A ₀ Ii, \ L ·)

φ ₂ = ₁ + Τ-Α Α _0/2. (2)

These relationships hold for A ₀ <C 2A ₁ .
The signals in FIG. 3 represent a special case caused by the two inequalities

A ₀ + A ₁ > T and A ₀ > A ₁

is fixed. Looking at the other three possible combinations, it can be seen that they give curves of the same shape as that in FIG. 3. It can be seen that each of these curves intersects the line of the ordinate A ₁ at two points if

and that under these conditions the values for φ _± and φ ₂ are given by equations (1) and (2), respectively. It can be seen that these phase angles are those at which the leading or trailing edge of the clock pulse coincides with the center of the message signal.

In FIG. 6 shows another embodiment for the phase discriminator circuit, which contains AND circuits 116, 117, inverters 118, 119 and OR circuit 126. This Discriminator works according to the logical function

D = (C &#) V (C & Ή).

It can be seen that this discriminator has the same properties as the one used in Fig. 4 is shown.

The low pass filters 120 ^ 4 and 1205 are identical and of the AC type. Fig. 7 ″ represents a first possible implementation represents such a filter, which consists of the resistor 121 and the capacitor 122. Another possible embodiment for such a filter is shown in FIG. 8. This consists of resistors 123, 124 and a capacitor 125.

In FIG. 9, there is shown a detailed circuit diagram of the differential amplifier 131 and integration circuit 132 which make up the integrating differential amplifier shown in FIG. 1 was designated 130. The amplifier 131 contains two differential amplifiers with complementary symmetry, which contain the transistors 133, 134 and 135, 136 and which are referred to below as the left amplifier or the right amplifier. The signals with the amplitude M and M ₀ appearing on the output lines 14a and 14 & of the low-pass filters are applied to the input terminals which have the same reference numerals. Since the transistors operate in B mode, when looking at the figure, one sees that the first of these amplifiers is conductive at M <> M ₀ and that the second is conductive at M <.M _0. In the case of the amplifier on the left, the load of the transistor 134 contains the resistor 137 and the control circuit of the coupling transistor 141 in a common emitter configuration. This control circuit contains a base series resistor 139. The right amplifier is similarly connected (resistors 138 to 140) and controls the coupling transistor 142. The collectors R and Q of these coupling transistors are connected to the circuit 132, the load resistors 143 and 144, the integration capacitor 145, the discharge resistor 149, the diode 168 and. the high input resistance amplifier consisting of transistors 146, 147 and resistor 148 includes. Since coupling transistors 141 and 142 are biased for B operation, the voltage applied to capacitor 145 (point S ') is either + V or - V, depending on whether the differential voltage MM _{0 is} positive or negative . For the sake of simplicity it is assumed that

ίο that the charge on capacitor 145 is linear. Then the potential of the point S 'represents the time integral of the voltage MM ₀ , the limits of this voltage Hegen at + V and - V.
When looking at FIG. 1 it has been found that the gain of the amplifier is greater than 1, and since it is fed with voltages between + V and - V , its output is also limited between these two values. The lines 17 and 18 are connected to the lines shown in FIG. 1 have the same reference numerals, and the resistor 149 is used as a discharge resistor for the capacitor 145, the capacitance of which can be very large.

The mode of operation of the error signals in circuits 110, 120, 4, 1205, 131 and 132 will now be more precise considered.

In describing the FIG. 3 and 5 it has been found that the duration D _{T of} the signals emitted by the discriminator 110 during a time slot fluctuates from (A ₀ -A ₁ ) to (B ₀ + B ^) when a message signal is present, and that the duration corresponds to the value A _{corresponds to 1} when there is no such signal.

. V, the discriminator 110 and illustrated in Figure 4 are also signals having the amplitude - -. As shown in Figure 1 under lla and 12a shown, the input and clock signals have erne amplitude V ab. The mean value in a time slot T of an output signal of duration D _T is then V · D _T / T in the absolute value. These signals are on

the low-pass filter 120 ^ 4 is applied, which emits an output signal 14 α, the amplitude of which represents the mean value of the input signal over η successive time slots. You get so

1. a signal of amplitude M ₀ = - V · AJT, if no message signal is present at input 11 during the η time slots,

2. a signal of amplitude

M ₁ '= -V- (2φ + A ₁ -A ₀ ) IT

or
M ₁ "= -V ■ (2T -2φ + A ₀ - A ₁ ) ZT,

if η message signals are received during the η time slots and if the phase angle φ is such that the operating point in one of the parts of the curve according to FIG. 5 has a positive or negative slope.

In general, H ₁ denotes the number of time slots in which a digit 1 is applied to input terminal 11, and n ₀ denotes the number of time slots in which a digit 0 is received (n = n ₀ + H ₁ ), then the mean value of the output of the filter is 120 ^

M = (n ₀ M ₀ + U ₁ M ₁ ) In .

ίο

This signal M is applied to the input 14 a of the amplifier 131, which receives the signal M ₀ at the input 14 b , which is emitted directly from the low-pass filter 120 B.

Let us now consider the expression A = M- M ₀ , which represents the result of the operation carried out by the differential amplifier in terms of both amplitude and sign. You get

Δ = (KM ₀ + H ₁ M ₁ ] Zn) -M ₀ = [U ₁ In) (M ₁ - M ₀ ).

(3)

Regardless of the value of U ₁ , the error Δ becomes zero for M ₁ = M ₀ , ie for the values of the phase angles <p _x and φ ₂ , which are given by equations (1) and (2), which are used during the consideration of the discriminator 110 were set up.

However, if M ₁ = M ₀ , then the amplitude and the sign of this error signal represent the amplitudes and the sign of the difference between the signals 11a and 12a in relation to these values ^ ₁ and φ. _ζ . When considering equation (3) it can also be seen that the amplitude of the error signal is proportional to the mean message density. When looking at FIG. 1 it has already been determined that the loop gain is high, and this gain is determined in such a way that a working error signal is obtained for a minimum value of U ₁ (n _± = 1).

The error signal A, that is the signal which appears at one of the outputs R or Q of the differential amplifier 131 (Figs. 1 and 9), is applied to the integrator 132, in which it the value of the potential at point S in such one direction changes that the signal cancels.

At Δ = 0, the Signalella and 12a are phase-drawn with a phase angle φ ₁ or <p ₂ .

Corresponding to the change in the frequency of the oscillator with respect to the voltage VS (FIG. 2), only one of these phase angles corresponds to a stable operating point. If one has the in FIG. 2, and the signals 12 and 13 have a negative polarity, the stable operating point corresponds to the phase angle φ _ν

In FIG. 5 shows that the total duration D ₇ of the signal emitted by the discriminator 110 as a function of the phase angle between the signals 11a and 12a is between 0 and T. If the two signals are not in a fixed phase relationship, the abscissa also represents the time axis on which the beat period between the two signals is measured.

As one can see from FIG. 5 recognizes, the output signal from the discriminator 110 is always of the same polarity, so that it appears like an alternating signal which is superimposed on _{a direct current component of the value M 0.} The line of the lowest frequency of this alternating signal is at the beat frequency.

This frequency increases when the signals migrate from the synchronism, and when it becomes greater than the limit frequency of the filter 120 v4, only the direct current component with the amplitude M ₀ and A = O is transmitted. The integration capacitor 145 now no longer receives a correction voltage, so that the frequency of the oscillator 100 can no longer follow the frequency migration. It is therefore necessary to provide a frequency synchronization arrangement 150 in addition to the phase coupling loop, the current flow of which is also shown in FIG. 9 and which is switched by a signal which characterizes the desynchronization.

The synchronization detection circuit does not belong to the invention and can refer to various Way to be built. It can be seen, however, that the signal at the output 13 of the discriminator 110 represents the beat frequency between the signals and that this information is used can to derive the desynchronization signal.

In the exemplary embodiment there is a positive pulse

on the basis of -V volts with an amplitude of two V and a sufficient duration to fully charge the integration capacitor 145 (FIG. 9) via the resistor 149 as a desynchronization signal.

To simplify the illustration, it is assumed in the drawing that it is generated by a changeover contact 170 which is normally in the position α . In this way a voltage - V is applied to line 18, and when this changeover switch is in position b for the duration of a desynchronization pulse, a voltage + V is applied to this line.

The frequency synchronization circuit is through

a flip-flop circuit is formed which contains the pnp transistors 151,152, the collector resistors 153,154, the feed bridges 155, 156 and 157 for the transistor 151, and 158, 159 and 160 for the transistor 152, the feedback diodes 163, 164, the decoupling diodes 165, 166 for the control circuit and contains the decoupling diode 167 for the output circuit. The decoupling diode 167 can, as in FIG Figure shown, only a single diode, or several identical diodes are connected in series. The capacitors 161 and 162, which are parallel to the resistors 156 and 159, respectively, are used, as it is well known to shorten the storage time of the transistors working through saturation.

The mode of operation of such a flip-flop circuit is generally known and should therefore not be used to be discribed.

When a signal with a positive polarity on one of the input terminals 17 or 18 of the flip-flop circuit is applied, the corresponding transistor is turned with a collector voltage of - V volts and the other transistor is saturated. When the oscillator is pulled in phase, transistor 141 is blocked or saturated corresponding to the sign of the error voltage A, so that transistor 151 is blocked and transistor 152 is saturated. Under these conditions, no current flows through the diode 167, the anode of which is at a potential of −V and is therefore more negative than the potential at the cathode (signal M ₀ = V _{− A 1} ] T). The diode 166 is blocked when the switch 170 is in position A.

On the other hand, the diode 165 is conductive when the transistor 141 of the amplifier 131 is conductive or when the potential at the point S 'is sufficiently positive that the base voltage of the transistor 151 becomes more positive. However, this does not result in any disadvantages, since this transistor must be blocked.

When the positive desynchronization pulse is on

the line 18 is applied, it makes the diode 168 conductive and causes the charging of the in-

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integration capacitor 145 to the value + V through the resistor 149, so that the frequency of the oscillator 100 (Fig. 1 and 2) is brought to the value Z ₁ . This signal also makes the diode 166 conductive and controls the change in the state of the flip-flop 150. The transistor 152 is blocked and the transistor 151 is saturated with a collector voltage of e _x volts, when e _x denotes the saturation voltage of this transistor. Since the signal at input 14 δ has a value M ₀ which is more negative than - e _v , the decoupling element 167 becomes conductive, and this input is brought to a negative potential of amplitude Vd-e _x + me ₂ when e _{2 is} the voltage drop in a diode and m represents the number of diodes making up this element 167. This value can, as it were, be brought into the ordinate of the curve in FIG. 5 by converting it into an equivalent duration TIVVd.

Since the signal present at the input 14 α has an amplitude

M ₀ = -VA ₁ IT

when the oscillator is desynchronized, it can be seen that the right amplifier in circle 131 is conducting and that point S is brought to the potential - V. This voltage applied to the integration capacitors charged to the voltage + V volts therefore brings the charge to the value - FVoIt, so that the oscillator 100 (FIG. 1) sweeps _{the frequency range from Z 1} to Z _2.

As already stated above, the amplitude of the signal at the input 14a differs only slightly from the value M ₀ as long as the beat frequency is high.

On the other hand, if the beat frequency becomes sufficiently small that it can pass through the low-pass filter 120 ^ 4 is transmitted, the signal at the starting point 14a fluctuates between the values

(-VIT) (A ₀ -A ₁ ) and (-VIT) (B ₀ + BJ. '

If one has now chosen η so that
(VIT) (A ₀ -A ₁

is, then the left amplifier of the circuit 131 is conductive, and at the output R appears a positive signal. This signal controls a change of state in the flip-flop 150 via the diode 165, in which the transistor 151 is now blocked and the transistor is saturated. You can see that the original state now exists again. The diode 167 is blocked and the input 14 & receives the signal M ₀ .

Claims (1)

Claim: Phase-pulled oscillator for use in regenerative amplifiers for PCM transmission systems, characterized in that the input signal (lla) and a locally generated clock signal (12 a) are compared in a phase discriminator (110) and then passed through a low-pass filter (120A) , which emits a signal (14 a), the amplitude (M) of which is proportional to the mean phase difference between the two signals (11a, 12a), and that this signal (14 a) and a signal (14 b) representing the mean value of the clock signals of the amplitude (M ₀ ) is applied to an integrating differential amplifier (130), the output signal (S, 16) of which controls the frequency of the oscillator (100) generating the clock signal, and that a frequency synchronization arrangement (150) is provided which operates when a desynchronization is determined in a manner known per se, and at its one output (18) a signal of the duration of the desynchronization pulse and at its other Output (14 b) emits a continuous signal in such a way that the oscillator (100), which is no longer phase-drawn when a predetermined phase deviation is exceeded, can be controlled from one cutoff frequency (Z ₁ ) to the other cutoff frequency (Z ₂ ) and can be phase-regulated again when the received frequency is reached . 1 sheet of drawings 609 590/3 «7.66 © Bundesdruckerei Berlin