DE1190232B - Adder for binary encoded decimal digits - Google Patents

Description

Adder for binary encrypted decimal digits The invention relates to an accumulating adder for binary encrypted decimal digits with the following Decimal digit correction, in which the one summand digit in an accumulator register, z. B. from bistable multivibrators, is included and the binary digits of the second Summand number staggered over time or spatially parallel input channels supplied will.

There are already accumulating adders known, the binary add encrypted decimal digits in parallel. Under accumulating is supposed to be be understood that the one summand is contained in a register and the second summand is added into this register. These known adding units are structured in such a way that when adding two binary summand digits and of the carryover from the previous position resulting summand digits and the binary Transfers to the next higher binary digit through a logical linking network are formed. Furthermore, the Correction of possible pseudo-decimals that were generated when adding binary encoded Decimal digits is necessary.

The summand digits thus formed by means of logical linking networks are entered in the accumulator register by a clock pulse. These adders are therefore used to achieve the short computing time they require however, a considerable amount of logical connection elements. Through this, that many logical linking elements are connected in series, arise due to the settling time of these elements, considerable runtimes for the Binary digits representing pulses. The clock pulses must therefore have the appropriate have a time interval from each other.

It is also an adder for binary coded decimal numbers known that works without logical linking networks, but in which the to adding operand is entered in series.

The object of the invention is to provide an accumulating adder for binary encrypted decimal digits with subsequent decimal digit correction using low expenditure on logical linking elements for the formation of the decimal Carries and for the correction of pseudo-decimals without series connections of logical To create linking elements for the formation of the binary sums and carries no logical linking networks required.

According to the invention the object is achieved in that a first group of operand digits staggered in time via spatially parallel channels (with the direct Encryption especially the digits with the weights 1 and 4) and then one second group of operand digits (binary digits with weights 2 and 8) at the same time is entered via parallel channels and that is exactly the same as the operand digits the correction value in groups in chronological order via parallel channels to the adder is fed.

The invention is explained below with reference to the drawing. It shows Fig. 1 shows an embodiment according to the invention designed for directly encrypted decimal numbers Adder and F i g. 2 the pulse time image for the control units used in the adder and counts.

The in Fig. 1 shown adder consists of four trigger-switched bistable multivibrators 1 ... 4. These are only shown symbolically and can be used in a known manner, for. B. consist of two mutually fed back transistor amplifiers. A trigger is understood to be a bistable multivibrator that has inputs that act on both systems, so that a switchover to the opposite stable position takes place with each pulse.

The outputs of the flip-flops are designated with bi, b2, b4, b $, b4 and b $, as far as they are required, whereby the indices 1, 2, 4, 8 indicate the weights of the corresponding binary digits. The four flip-flops 1 ... 4 have inputs 5 ... 8, which are connected to the outputs of AND circuits 9 ... 12.

The AND circuits are also shown only symbolically and can be constructed in a known manner as diode networks. The input channels a1 ... a8, on which the summand digits to be added are fed in parallel, are connected to the flip-flops 9 ... 12. An input h2 is also connected to the AND circuit 9 , inputs h3 are connected to the AND circuits 10 and 12 , and an input h4 is connected to the AND circuit 11.

The output bi of the trigger stage 1 is led to a second input 13 of the trigger stage 2, the output b2 of the trigger stage 2 to an input 14 of the trigger stage 3 and the output b4 of the trigger stage 3 to an input 15 of the trigger stage 4 . An OR circuit 16 is via the lines 17 and 18 with the outputs b4 and 62 of the flip-flops 3 and 2, an AND circuit 19 is with the output of the OR circuit 16, the output b8 of the flip-flop 4 and the output of a AND circuit 20, an AND circuit 21 is connected to the output b8 of the flip-flop 4, the output b4 of the flip-flop 3, the channel a4 and the output of the AND circuit 20, and an AND circuit 22 is connected to the output b8 of the Flip-flop 4, the channel a. and the output of the AND circuit 20 .

The outputs of the AND circuits 19, 21 and 22 are connected to the right input of a bistable multivibrator 23, the outputs Kr and Kr control the AND circuits 20 and 24 , to which a line labeled hl is also led. The output of the AND circuit 24 is fed to the left input of the flip-flop 23 . The output Kr of the flip-flop 23 is also connected to the inputs 25 ... 28 of the AND = circuits 9 ... 12.

The flip-flop 2 has a further input 29 which is connected to the output of an AND circuit 30 which is controlled via two lines h3 and Kr. In this illustration, b1 . . . b $ at the same time the encrypted decimal digit in the accumulator register, a1 ... a8 mean the decimal digit to be added, hl . . . h4 are the control and counting pulses used, the timing of which is shown in FIG. 2, and Kr is a control amount indicating that the correction of a pseudo-decimal is to be made.

The accumulation in the accumulator register is done in the following way. The augend b1, b2, b4, b8 is in the accumulator register, and the addend a1, a2, a4, a8 is fed in parallel to the AND circuits 9 ... 12 via the four channels labeled in the same way and in three time-shifted clocks , which are designated with h2, h3 and h4, in the flip-flops 1.. . 4 entered.

The pulse h2 switches the lowest bit of the addend tetrad, the pulse h3 the second and fourth and the pulse h4 the third bit in the accumulator register by z. B at a1 = L the flip-flop 1 is switched to the opposite position.

If the flip-flop 1 contains an L in the course of the accumulation sequence, this is triggered to 0 by the conjunction a1 - h2 (AND circuit 9), and a switching edge from L to 0 occurs at output bi, which is transmitted via line 13 to the Toggle stage 2 switches to the opposite position. If b2 were L in this case, the carry would propagate to flip-flop 3 and then possibly (with b4 = L) to flip-flop 4. During this time, no information can reach the flip-flops via inputs 6, 7, 8, since the Binary information arriving via channels a2, a4 and a $ can be switched with pulses that appear later.

The pulse h3 appearing one cycle time after the pulse h2 (see also Fig. 2) leads the bits a2 and a $ into the accumulator register and triggers the associated flip-flop if a2 = L or a $ = L. Due to the structure of the decimal 8421 encryption, a2 and a8 cannot have the value L at the same time (this would correspond to a pseudo-decimal LOLO, for example). With some of the other binary decimal encryptions, this advantage of introducing two bits at the same time does not apply. The bit with weight 4, which comes in via channel a4, is again fed to flip-flop 3 one cycle later with the third pulse h4 (FIG. 2).

Arises from the addition of the tetrad a8. . . a1 to the tetrad b. . . . If there is a pseudo-decimal or an overflow (carry over to the next tetrad), the value -f-6 must be corrected for direct encryption. The correction decision is made by switching on the flip-flop 23. The switching on of the flip-flop 23 takes place with the pulse hl appearing one cycle time after h4. An occurring pseudo-decimal is indicated by the network b. - (b, v b2) - hl (AND circuit 19 OR circuit 16) taken into account.

In the event of an overflow, the conjunction-disjunction sequence switches b $ - (b4 - a4 v a8) - hl (AND circuits 21 and 22). The conjunction b8 - a8 (AND circuit 22) marks the cases 8-I-8, 8-I-9, 9 + 8, 9 + 9, because if b8 = 0 and a8 = L are present at pulse time hl This is a sign that b $ was triggered from L to 0 with h3, i.e. that both summands contained an L in the highest digit. The conjunction b $ .'54 - a4 (AND circuit 21) switches on the correction decision flip-flop 23 in cases a = 7, b = 9 (7-f-9). All four toggle stages 1 ... 4 are set to 0 during the addition process, and an L is present at a4. In the case of 9-i-6, the flip-flop 3 would contain an L at the end, and the condition b4 = L would not be fulfilled. There is no carry over, but the correction due to the occurrence of a pseudo-decimal. The case a = 9, b = 7 (7 -! - 9) is contained in the conjunction b8 - a8. The correction process itself takes place asynchronously (dragging) in that, if a correction is necessary, the pulse feed for a four-cycle group (cycles h2, h3, h4, hl) is blocked. For the latter purpose, the control variable Kr is fed to the AND circuits 9 ... 12.

The correction process is carried out by trigger pulses on the multivibrators 2 and 3, which, however, do not arrive at the same time because of the possible transfers to be allowed to.

First, the flip-flop 2 is triggered with the pulse h3 supplied from the clock center by the conjunction Kr - h3 (AND circuit 30). The flip-flop 23 is switched off again by the pulse hl. The switch-off edge of Kr triggers the flip-flop 3 and thus feeds the value 4 to the input of the correction value -f-6, which is subdivided into -I-2 and -f-4.

Claims (5)

Claims: I. Accumulating adder for binary encrypted ones Decimal digits with subsequent decimal digit correction, in which the one addend digit in an accumulator register, e.g. B. from bistable flip-flops, is included and the binary digits of the second summand digit staggered in time over spatially parallel ones Input channels be fed so that the immediate pass the carryover from each flip-flop of the accumulator register to the next without Interposition of logical or delaying switching elements takes place, thereby characterized in that a first group of operand digits staggered over time Spatially parallel channels (with direct encryption especially the digits with the weights 1 and 4) and then a second group of operand digits (binary digits with weights 2 and 8) is entered simultaneously via parallel channels and that just like the operand digits, the correction value is also in groups in chronological order is fed to the adder via parallel channels. 2. Arrangement according to claim 1, characterized in that when using direct binary decimal encryption with the binary digit weights 1, 2, 4, 8 the pulse groups for entering the necessary Correction value of z. B. -f-6 refers to two pulses with the valences -h 4 and +2, which are fed to the adder on two different channels at different times will reduce. 3. Arrangement according to claim 1, characterized in that at Correction need a flip-flop (23) is switched on, which does the addition the next summand digit is blocked until the process of correction addition is finished. 4. Arrangement according to claim 1, characterized in that the accumulator register has additional counter inputs that use this register as a normal dual counter let work. 5. Arrangement according to claim 3, characterized in that the correction decision in the direct encryption is carried out by a network (b4vb2) - b.va4-b8-54va8-b8, which forms the logical expression (b4 v b2), the conjunction (b4 v b2) - b8 take the pseudo-decimal digit and the other two conjunctions into account. References considered: U.S. Patent No. 2,947,479; "Automatic Digital Computers", Methuen & Co., Ltd., London, 1956, pp. 232-233; "Arithmetic Operations in Digital Computers", D. van Nostrand Comp. Inc., New York, 1955, pp. 82, pp. 107 to 110; "Digital computing systems", Springer Verlag, Berlin, 1961, pp. 42-43.