DE1133163B - Logische Verknuepfungsschaltung - Google Patents

Logische Verknuepfungsschaltung

Info

Publication number
DE1133163B
DE1133163B DET19445A DET0019445A DE1133163B DE 1133163 B DE1133163 B DE 1133163B DE T19445 A DET19445 A DE T19445A DE T0019445 A DET0019445 A DE T0019445A DE 1133163 B DE1133163 B DE 1133163B
Authority
DE
Germany
Prior art keywords
inputs
threshold
inhibition
excitation
circuit according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DET19445A
Other languages
German (de)
English (en)
Inventor
Erhard Czok
Salomon Klaczko-Ryndzium
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefunken Patentverwertungs GmbH
Original Assignee
Telefunken Patentverwertungs GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to NL272700D priority Critical patent/NL272700A/xx
Application filed by Telefunken Patentverwertungs GmbH filed Critical Telefunken Patentverwertungs GmbH
Priority to DET19445A priority patent/DE1133163B/de
Priority to FR877830A priority patent/FR1361308A/fr
Priority to US158436A priority patent/US3278755A/en
Priority to GB45609/61A priority patent/GB1002575A/en
Publication of DE1133163B publication Critical patent/DE1133163B/de
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/5013—Half or full adders, i.e. basic adder cells for one denomination using algebraic addition of the input signals, e.g. Kirchhoff adders
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/0813—Threshold logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/084—Diode-transistor logic
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4818—Threshold devices
    • G06F2207/4822—Majority gates

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Computational Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Mathematical Optimization (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Data Mining & Analysis (AREA)
  • Molecular Biology (AREA)
  • Software Systems (AREA)
  • General Health & Medical Sciences (AREA)
  • Algebra (AREA)
  • Evolutionary Computation (AREA)
  • Computational Linguistics (AREA)
  • Artificial Intelligence (AREA)
  • Neurology (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)
DET19445A 1960-12-20 1960-12-20 Logische Verknuepfungsschaltung Pending DE1133163B (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
NL272700D NL272700A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1960-12-20
DET19445A DE1133163B (de) 1960-12-20 1960-12-20 Logische Verknuepfungsschaltung
FR877830A FR1361308A (fr) 1960-12-20 1961-11-03 Montage logique permettant de réaliser de nombreuses interconnexions logiques
US158436A US3278755A (en) 1960-12-20 1961-12-11 Logic gate with regular and restraining inputs
GB45609/61A GB1002575A (en) 1960-12-20 1961-12-20 Logical circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DET19445A DE1133163B (de) 1960-12-20 1960-12-20 Logische Verknuepfungsschaltung

Publications (1)

Publication Number Publication Date
DE1133163B true DE1133163B (de) 1962-07-12

Family

ID=7549322

Family Applications (1)

Application Number Title Priority Date Filing Date
DET19445A Pending DE1133163B (de) 1960-12-20 1960-12-20 Logische Verknuepfungsschaltung

Country Status (4)

Country Link
US (1) US3278755A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE1133163B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB1002575A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
NL (1) NL272700A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1295648B (de) * 1964-04-03 1969-05-22 Saint Gobain Elektronischer Schaltkreis zur Durchfuehrung logischer Funktionen
DE2627574A1 (de) * 1975-06-30 1977-01-13 Signetics Corp Integrierte mehrpegel-injektionslogik

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3423728A (en) * 1963-11-29 1969-01-21 Avco Corp Decoding arrangement with magnetic inhibitor means for providing a failsafe command signal
US3814951A (en) * 1972-11-15 1974-06-04 Bell Telephone Labor Inc Multiple function logic circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1026996B (de) * 1954-02-26 1958-03-27 Ibm Deutschland Binaerer Additionskreis mit Transistoren

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2843837A (en) * 1955-12-08 1958-07-15 Thaler Samuel Digital comparison gate
US3050642A (en) * 1959-08-03 1962-08-21 Collins Radio Co Combined squelch circuit and amplifier
US3155841A (en) * 1959-10-28 1964-11-03 Nippon Electric Co Logical nu out of m code check circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1026996B (de) * 1954-02-26 1958-03-27 Ibm Deutschland Binaerer Additionskreis mit Transistoren

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1295648B (de) * 1964-04-03 1969-05-22 Saint Gobain Elektronischer Schaltkreis zur Durchfuehrung logischer Funktionen
DE2627574A1 (de) * 1975-06-30 1977-01-13 Signetics Corp Integrierte mehrpegel-injektionslogik

Also Published As

Publication number Publication date
NL272700A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB1002575A (en) 1965-08-25
US3278755A (en) 1966-10-11

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