DE112019007166T5 - Rectifier circuit, DC power supply combination circuit and full-wave rectifier circuit - Google Patents

Abstract

By connecting an input terminal (Vi) to a drain terminal of a P-channel MOSFET (QMp), connecting an output terminal (Vout) to a source terminal, and turning off the P-channel MOSFET (QMp), a reverse current is generated from the output terminal ( Vout) to the input connection (Vi) prevented. A PNP transistor (Q1) and a PNP transistor (Q2) sense reverse current and turn off the P-channel MOSFET (QMp). A PNP transistor (Q3) and an NPN transistor (Q4) are a current boosting circuit for charging and discharging a gate of the P-channel MOSFET (QMp) and improves the transient response of the P-channel MOSFET (QMp).

Description

Technical area

This invention relates to a rectifier circuit, a DC power supply combination circuit and a full-wave rectifier circuit.

General state of the art

If the outputs of several DC voltage supplies are combined for the purpose of a backup voltage supply or the like and connected to a load, a reverse current blocking circuit is connected between the DC voltage supplies and the load, which uses a MOSFET (metal-oxide-semiconductor field-effect transistor) to prevent it comes to a reverse current from one of the plurality of DC power supplies to another of the DC power supplies (see Patent Document 1).

Prior art documents

Patent documents

Patent Document 1, Japanese Patent Laid-Open No. S62-12332

Summary of the invention

Object of the present invention

The reverse current blocking circuit of Patent Document 1 has a bipolar transistor to turn off the MOSFET when reverse current occurs. The problem with this reverse current blocking circuit is that the reverse current cannot be blocked as long as the potential difference between input and output is not constantly at or above the voltage between the base and emitter of the bipolar transistor (usually around 0.7 V).

The invention was made with this problem in mind, and its object is to block reverse current, even if the potential difference between input and output is extremely low compared to the prior art (for example 0.7 V) (for example 200 mV).

Means for solving the task

A rectifier circuit according to the invention comprises a P-channel MOSFET element, a first PNP bipolar transistor element, a second PNP bipolar transistor element, a third transistor element and a fourth transistor element with opposite polarity, a first resistor, a second resistor, a third resistor, a fourth resistor , an input terminal and an output terminal, wherein a connection point between a drain terminal of the P-channel MOSFET element and one terminal of the first resistor is connected to the input terminal, the first PNP bipolar transistor element forms an equivalent diode element, an anode terminal of the equivalent diode element and another terminal of the first resistor are connected and a cathode terminal of the equivalent diode element, a base terminal of the second PNP bipolar transistor element and one terminal of the second resistor are connected, a connection point between hen another connection of the second resistor, one connection of the third resistor and a first connection of the third transistor element are connected to ground, another connection of the third resistor, a collector connection of the second PNP bipolar transistor element, a third connection of the third transistor element, a third Terminal of the fourth transistor element and one terminal of the fourth resistor are connected, a second terminal of the third transistor element, a second terminal of the fourth transistor element, another terminal of the fourth resistor and a gate terminal of the P-channel MOSFET element are connected and a connection point between an emitter connection of the second PNP bipolar transistor element, a source connection of the P-channel MOSFET element and a first connection of the fourth transistor element are connected to the output connection.

Effect of the invention

According to the invention, reverse current can be blocked even if the potential difference between input and output is extremely low compared to the prior art.

Figure list

• 1 ein Schaltbild, das ein Konfigurationsbeispiel einer Gleichrichterschaltung IDP gemäß einer ersten Ausführungsform veranschaulicht;
• 2A und 2B Beispiele eines PNP-Transistors Q1, der als ein äquivalentes Diodenelement konfiguriert ist;
• 3 eine erläuternde Ansicht des Betriebs der Gleichrichterschaltung IDP der ersten Ausführungsform bei einem Potenzialanstieg aufgrund eines externen Faktors;
• 4 eine erläuternde Ansicht einer Gate-Kapazität eines P-Kanal-MOSFET QMp;
• 5 eine Ansicht, die ein Abwandlungsbeispiel von Stromverstärkungsschaltungen der ersten Ausführungsform veranschaulicht;
• 6 ein Schaltbild, das ein Konfigurationsbeispiel einer Gleichrichterschaltung IDN gemäß einer zweiten Ausführungsform veranschaulicht;
• 7A und 7B Beispiele eines NPN-Transistors Q11, der als ein äquivalentes Diodenelement konfiguriert ist;
• 8 eine erläuternde Ansicht des Betriebs der Gleichrichterschaltung IDN der zweiten Ausführungsform bei einem Potenzialanstieg aufgrund eines externen Faktors;
• 9 eine erläuternde Ansicht einer Gate-Kapazität eines N-Kanal-MOSFET QMn;
• 10 eine Ansicht, die ein Abwandlungsbeispiel von Stromverstärkungsschaltungen der zweiten Ausführungsform veranschaulicht;
• 11 eine Ansicht, die ein Schaltbeispiel einer Spannungsversorgung Vcc der zweiten Ausführungsform veranschaulicht;
• 12 ein Schaltbild, das ein Konfigurationsbeispiel einer Gleichrichterschaltung IDP gemäß einer dritten Ausführungsform veranschaulicht;
• 13 eine erläuternde Ansicht des Betriebs der Gleichrichterschaltung IDP der dritten Ausführungsform für den Fall, dass eine Z-Diode DZ vorhanden ist;
• 14 ein Schaltbild, das ein Konfigurationsbeispiel einer Gleichrichterschaltung IDN gemäß einer vierten Ausführungsform veranschaulicht;
• 15 eine erläuternde Ansicht des Betriebs der Gleichrichterschaltung IDN der vierten Ausführungsform für den Fall, dass eine Z-Diode DZ vorhanden ist;
• 16 ein Schaltbild, das ein Konfigurationsbeispiel einer Gleichspannungsversorgungskombinationsschaltung 1 gemäß einer fünften Ausführungsform veranschaulicht;
• 17 ein Schaltbild, das ein Konfigurationsbeispiel einer Vollwellengleichrichterschaltung 2 gemäß einer sechsten Ausführungsform veranschaulicht; und
• 18 ein Schaltbild, das ein Konfigurationsbeispiel einer Vollwellengleichrichterschaltung 3 gemäß einer siebten Ausführungsform veranschaulicht.

Show it:

• 1 a circuit diagram showing a configuration example of a rectifier circuit IDP illustrated according to a first embodiment;
• 2A and 2 B Examples of a PNP transistor Q1 configured as an equivalent diode element;
• 3 Fig. 3 is an explanatory view of the operation of the rectifier circuit IDP the first embodiment in the event of a potential increase due to an external factor;
• 4th Fig. 8 is an explanatory view of a gate capacitance of a P-channel MOSFET QMp ;
• 5 Fig. 10 is a view illustrating a modification example of current amplifying circuits of the first embodiment;
• 6th a circuit diagram showing a configuration example of a rectifier circuit IDN illustrated according to a second embodiment;
• 7A and 7B Examples of an NPN transistor Q11 configured as an equivalent diode element;
• 8th Fig. 3 is an explanatory view of the operation of the rectifier circuit IDN the second embodiment in the event of a potential increase due to an external factor;
• 9 Fig. 8 is an explanatory view of a gate capacitance of an N-channel MOSFET QMn ;
• 10 Fig. 10 is a view illustrating a modification example of current amplifying circuits of the second embodiment;
• 11 a view showing a circuit example of a power supply Vcc the second embodiment illustrated;
• 12th a circuit diagram showing a configuration example of a rectifier circuit IDP illustrated according to a third embodiment;
• 13th Fig. 3 is an explanatory view of the operation of the rectifier circuit IDP the third embodiment in the event that a Zener diode Double room is available;
• 14th a circuit diagram showing a configuration example of a rectifier circuit IDN illustrated according to a fourth embodiment;
• 15th Fig. 3 is an explanatory view of the operation of the rectifier circuit IDN the fourth embodiment for the case that a Zener diode Double room is available;
• 16 Fig. 3 is a circuit diagram showing a configuration example of a DC power supply combination circuit 1 illustrated according to a fifth embodiment;
• 17th Fig. 4 is a circuit diagram showing a configuration example of a full-wave rectifier circuit 2 illustrated according to a sixth embodiment; and
• 18th Fig. 4 is a circuit diagram showing a configuration example of a full-wave rectifier circuit 3 illustrated according to a seventh embodiment.

Embodiment of the invention

In the following, embodiments of the invention are described for a detailed description of the invention with reference to the accompanying figures.

First embodiment

1 Fig. 13 is a circuit diagram showing a configuration example of a rectifier circuit IDP illustrated according to a first embodiment. The rectifier circuit IDP comprises a P-channel MOSFET QMp , a PNP transistor Q1 , a PNP transistor Q2 , a PNP transistor Q3 , an NPN transistor Q4 , a resistor R1 , a resistor R2 , a resistor R3 and a resistor R4 .

The rectifier circuit IDP serves to use the P-channel MOSFET QMp the flow of reverse current from an output port Vout to an input port Vi to block. In the case of the P-channel MOSFET QMp is an enhancement type P-channel MOSFET device. A mass GND is a potential related to the potential of the input terminal Vi is lower by at least a potential Vth between the gate and source at which the P-channel MOSFET QMp can turn on. The size ratio of the potentials is thus GND <Vi + Vth.

The PNP transistor Q1 corresponds to the first PNP bipolar transistor element and the PNP transistor Q2 corresponds to the second PNP bipolar transistor element. The PNP transistor Q1 and the PNP transistor Q2 are used to detect the potential difference between the input connection Vi and the output connector Vout the rectifier circuit IDP .

The PNP transistor Q3 corresponds to the third transistor element and is a PNP bipolar transistor element. The NPN transistor Q4 corresponds to the fourth transistor element with opposite polarity to the third transistor and is an NPN bipolar transistor element. At the PNP transistor Q3 and the NPN transistor Q4 the collector connection corresponds to the first connection, the emitter connection corresponds to the second connection and the base connection corresponds to the third connection. The PNP transistor Q3 and the NPN transistor Q4 are current amplifying circuits for charging and discharging a gate of the P-channel MOSFET QMp . In the steady state, flows between the collector and emitter of the PNP transistor Q3 and between the collector and emitter of the NPN transistor Q4 no electricity. When there is a voltage fluctuation at the input terminal Vi or at the output connector Vout , i.e. in a transient state in which the gate potential of the P-channel MOSFET QMp changed, flows between the collector and emitter of the PNP transistor Q3 and between the collector and emitter of the NPN transistor Q4 Current and the gate capacitance of the P-channel MOSFET QMp is subject to rapid charging and discharging.

As in 1 shown is a connection point between the drain terminal of the P-channel MOSFET QMp and one connection of the resistor R1 with the input connector Vi connected.

In 1 are the base connection and the collector connection of the PNP transistor Q1 shorted, and this PNP transistor Q1 is designed as an equivalent diode element. 2A and 2 B show examples of the PNP transistor Q1 , which is designed as an equivalent diode element. As in 1 and 2A shown corresponds to the PNP transistor Q1 the emitter connection corresponds to the anode connection (A) of the equivalent diode element, and the connection point between the base connection and the collector connection corresponds to the cathode connection (K) of the equivalent diode element. In this example, the emitter connection is the PNP transistor Q1 with the other connection of the resistor R1 connected. The connection point between the base connection and the collector connection of the PNP transistor Q1 is to the base connection of the PNP transistor Q2 and one connection of the resistor R2 connected.

In the example from 2 B corresponds to the collector connection of the PNP transistor Q1 the anode connection (A) of the equivalent diode element, and with this collector connection is the other connection of the resistor R1 connected. The base connection of the PNP transistor Q2 corresponds to the cathode connection (K) of the equivalent diode element, and with this base connection are the base connection of the PNP transistor Q2 and one terminal of the resistor R2 connected. The emitter connection of the PNP transistor Q1 is open.

In 1 is the connection point between the other terminal of the resistor R2 , one connection of the resistor R3 and the collector terminal of the PNP transistor Q3 with the crowd GND connected. The other terminal of the resistor R3 , the collector connection of the PNP transistor Q2 , the base connection of the PNP transistor Q3 , the base connection of the NPN transistor Q4 and one terminal of the resistor R4 are connected. The emitter connection of the PNP transistor Q3 , the emitter connection of the NPN transistor Q4 , the other terminal of the resistor R4 and the gate of the P-channel MOSFET QMp are connected. The connection point between the emitter terminal of the PNP transistor Q2 , the source connection of the P-channel MOSFET QMp and the collector connection of the NPN transistor Q4 is with the output connector Vout connected.

Next is the steady state of the rectifier circuit IDP described.

$$\therefore V_{out}=\frac{V_i-\delta +\frac{R_1}{R_2}{V}_{BE}}{1+R_1/R_2}$$

$$V_f=V_i-V_{out}=\frac{\frac{R_1}{R_2}\left(V_i-V_{BE}\right)+\delta }{1+R_1/R_2}$$

$$\frac{R_1}{R_2}\left(V_i-V_{BE}\right)+\delta$$

In the steady state of the rectifier circuit IDP is a difference between the voltage V _BE between the base and emitter of the PNP transistor Q2 , the voltage between the base and emitter of the PNP transistor Q1 and the voltage between the base and emitter of the PNP transistor Q2 δ> 0, and the voltage between the base and emitter of the PNP transistor Q1 is V _BE + δ. A DC leakage current at the gate of the P-channel MOSFET QMp , a base current of the PNP transistor Q1 and a base current of the PNP transistor Q2 are ignored. The resistance value of the resistor R2 is positive. Since in this case the emitter-side current and the collector-side current of the PNP transistor Q1 are the same result for the potential of the output connection Vout and the potential difference (i.e., the forward voltage) Vf between the input terminal Vi and the output connector Vout the relationships of equations (1) and (2) below.
$$\frac{V_i-\left(V_{Out}+\delta \right)}{{\mathrm{R.}}_1}=\frac{V_{Out}-V_{\mathrm{B.}\mathrm{E.}}}{{\mathrm{R.}}_2}$$

$$\therefore V_{Out}=\frac{V_i-\delta +\frac{{\mathrm{R.}}_1}{{\mathrm{R.}}_2}{V}_{\mathrm{B.}\mathrm{E.}}}{1+{\mathrm{R.}}_1/{\mathrm{R.}}_2}$$

$$V_f=V_i-V_{Out}=\frac{\frac{{\mathrm{R.}}_1}{{\mathrm{R.}}_2}\left(V_i-V_{\mathrm{B.}\mathrm{E.}}\right)+\mathrm{<figure-callout\; id="1"\; label="\delta "\; filenames="DE112019007166T5\_0011.png,DE112019007166T5\_0015.png"\; state="\{\{state\}\}">\delta </figure-callout>}}{1+{\mathrm{R.}}_1/{\mathrm{R.}}_2}$$

$$\frac{{\mathrm{R.}}_1}{{\mathrm{R.}}_2}\left(V_i-V_{\mathrm{B.}\mathrm{E.}}\right)+\delta$$

If for the purpose of reducing the power consumption of the rectifier circuit IDP the saturation voltage on the P-channel MOSFET QMp (Product of the on-resistance of the P-channel MOSFET QMp and the current flowing between drain and source) is controlled to the smallest possible value, i.e. if the forward voltage Vf is to be expressed with equation (2), the forward voltage Vf in equation (2) must be greater than the minimum saturation voltage of the P-channel MOSFET QMp being. This condition is described below. For example, if in equation (2) the resistance value of the resistor R1 compared to the resistance value of the resistor R2 is very small and, moreover, the difference δ is sufficiently small, a forward voltage Vf can be achieved which is lower than the forward voltage of a conventional diode element (about 0.7 V).

In equation (2), become the resistance value of the resistor R1 set to 0 and the difference δ to 0 are the potential of the Input connector Vi and the potential of the output terminal Vout same. Therefore, the forward voltage is Vf and the saturation voltage of the P-channel MOSFET QMp theoretically 0 V.

In the case of a negative difference δ (<0) in equation (3), which is the factor of equation (2), however, there is virtually a negative forward voltage Vf. In this case, the voltage at the output terminal increases Vout at | Vf | except for the voltage of the input terminal Vi settling to a reverse current from the output terminal Vout to the input port Vi , making the function of the rectifier circuit IDP is affected. Even if for the PNP transistor Q1 and the PNP transistor Q2 Similar PNP bipolar transistor elements are used, it can be due to individual deviations and differences in the respective ambient temperature of the PNP transistor Q1 and PNP transistor Q2 and the like happen that δ <0. To ensure that δ> 0 and to prevent reverse current, either the resistance value of the resistor must be R1 greater than 0 and equation (3) set to a positive value, or as a connection method for the PNP transistor Q1 must instead of the procedure 2A this in 2 B methods shown can be used.

When the PNP transistor Q1 as in 2A is connected, the voltage between the anode connection (A) and the cathode connection (K) is equal to the voltage V _BE between the base and emitter of the PNP transistor Q2 , since the base current is 1 / H _{FE of} the collector current. HFE is the current amplification rate.

On the other hand, if the PNP transistor Q1 as in 2 B connected, all the current flows between the collector and the base, and the voltage gradient is large. The voltage between the anode connection (A) and the cathode connection (K) is thus stronger than in the case of 2A . Therefore δ> 0 results. The dielectric strength between collector and base is generally higher than the dielectric strength between emitter and base, which is why the connection method is made 2 B has a higher dielectric strength against surge voltages and the like, which the input terminal Vi can overlay.

Next, referring to FIG 3 and 4th the operation of the rectifier circuit IDP in the event that described with the input connector Vi a DC power supply and to the output terminal Vout a consumer is connected. 3 Fig. 13 is an explanatory view of the operation of the rectifier circuit IDP of the first embodiment in the event of a potential increase due to an external factor. It describes the change in the load current and the gate potential of the P-channel MOSFET QMp over time when in a steady state in which the output voltage at the output terminal Vout E0 is and a load current flows I0 and the gate potential of the P-channel MOSFET QMp V0 is, from the outside, a forced voltage E1 to the output terminal Vout higher than (Vi-Vf). The external factor in the following is one with the output port Vout connected external power supply.

4th Fig. 13 is an explanatory view of the gate capacitance of the P-channel MOSFET QMp . At the drain, gate and source connections of the P-channel MOSFET QMp there are electrical capacitances Cgd, Cgs, Cds. The gate capacitance Ciss of the P-channel MOSFET QMp is (Cgd + Cgs).

In 3 there is no voltage E1 from the external voltage supply at the output terminal up to a point in time t0 Vout on and the rectifier circuit IDP is in the steady state above.

If at time t0 the voltage at the input terminal Vi and the potential of the crowd GND are constant, then the potential is at the connection point at which the base connection and the collector connection of the PNP transistor Q1 are short-circuited, constant provided the base current of the PNP transistor Q2 is ignored. When the voltage E1 to the output terminal Vout is applied, the voltage between the base and emitter of the PNP transistor increases Q2 and the PNP transistor Q2 becomes more conductive, whereby the potential at the P point (see 1 ), which is the connection point between the collector terminal of the PNP transistor Q2 and the other terminal of the resistor R3 acts, is raised. Since, however, on the P-channel MOSFET QMp as in 4th shown the gate capacitance Ciss (= Cgd + Cgs) is charged by the potential difference between P-point and drain or by the potential difference between P-point and source, the gate potential of the P-channel MOSFET QMp cannot be lifted immediately.

When the PNP transistor Q2 turns on and the P-point-side potential around the voltage V _BE between the base and emitter of the NPN transistor Q4 higher than the gate potential of the P-channel MOSFET QMp becomes, that is, when the potential difference between the two ends of the resistor R4 the voltage V _BE between the base and emitter of the NPN transistor Q4 increases, the NPN transistor switches Q4 on (ON). By turning on the NPN transistor Q4 forming a current boosting circuit at time t0 is an abrupt discharge of the Charge on the gate of the P-channel MOSFET QMp possible. In the course of discharging the charge on the gate of the P-channel MOSFET QMp the potential of the gate increases. The time span from time t0 to time t1 is in 3 an amplification period of the discharge by the current amplification circuit.

Since at time t1 the charge on the gate of the P-channel MOSFET QMp has been discharged, the potential difference between the two ends of the resistor will drop R4 below the voltage V _BE between the base and emitter of the NPN transistor Q4 which is why the NPN transistor Q4 switches off (OFF). From time t1, the gate of the P-channel MOSFET is slowly discharged QMp about the resistance R4 , and at time t2 the P-channel MOSFET switches QMp out. The gate potential at the time the P-channel MOSFET is switched off QMp is in 3 indicated as V1. The time span from time t1 to time t2 in 3 is the non-amplification period.

During the time span from time t0 to time t2, that is, the time of the settling of the P-channel MOSFET QMp from switch-on to switch-off depends on the gate potential of the P-channel MOSFET QMp to a reverse current from the output port Vout to the input port Vi .

If at time t4 the voltage E1 of the external voltage supply is no longer at the output connection Vout is applied, the voltage between the base and emitter of the PNP transistor decreases Q2 , which is why the PNP transistor Q2 weaker conductors. From the point in time t4, the potential of the P point falls due to the resistance R3 . However, since at time t4 the gate capacitance of the P-channel MOSFET QMp is discharged, it is not possible to use the gate potential of the P-channel MOSFET QMp to lower immediately, i.e. to complete the charging of the gate capacitance.

When the PNP transistor Q2 turns off and the P-point-side potential around the voltage V _BE between the base and emitter of the PNP transistor Q3 lower than the gate potential of the P-channel MOSFET QMp becomes, that is, when the potential difference between the two ends of the resistor R4 the voltage V _BE between the base and emitter of the PNP transistor Q3 increases, the PNP transistor switches Q3 one. By turning on the PNP transistor Q3 forming a current amplifying circuit, at time t4, there is an abrupt charge of the gate capacitance of the P-channel MOSFET QMp possible. In the process of charging the charge on the gate of the P-channel MOSFET QMp the potential of the gate decreases. The time span from time t4 to time t5 in 3 is a boosting period of charging by the current boosting circuit.

Since at time t5 the charge on the gate of the P-channel MOSFET QMp charged, the potential difference between the two ends of the resistor will drop R4 below the voltage V _BE between the base and emitter of the PNP transistor Q3 which is why the PNP transistor Q3 turns off. From the point in time t5, cause the resistance R3 and the resistance R4 a slow charge of the gate capacitance of the P-channel MOSFET QMp , and if at time t6 the gate potential of the P-channel MOSFET QMp When V0 is reached, the P-channel MOSFET switches QMp completely one. The time span from time t5 to time t6 in 3 is the non-amplification period.

Next, description will be made of the case that the rectifier circuit IDP the current amplification circuits of the PNP transistor Q3 and the NPN transistor Q4 are not present. In 3 are the gate potential of the P-channel MOSFET QMp and the consumer current in the event that the current amplification circuits are not present, shown with a dash-dot line.

When the voltage E1 of the external power supply at the output terminal Vout is applied, is the increase in potential at the gate of the P-channel MOSFET QMp compared to the presence of the current amplification circuits in the absence of the current amplification circuits. While reverse current flows in the time interval Ta between time t0 and time t2 when the current amplification circuits are present, the reverse current flows for a longer time interval Tb without the current amplification circuits, namely from time t0 to time t3. When the current boosting circuits are not in the rectifier circuit IDP are present, the duration of the flow of reverse current is thus lengthened, hence the possibility of damage to the one connected to the input port Vi connected power supply exists.

When there is no more voltage E1 at the output connection Vout is applied, the potential gradient at the gate is P-channel MOSFET QMp compared to the presence of the current amplification circuit in the absence of the current amplification circuits. The time required for the recovery of the consumer current is therefore the time span Tc from time t4 to time t6 with the presence of the power amplification circuit, while without the power amplification circuits the longer time span Td results from time t4 to time t7, which is why there is more time until the P is fully switched on -Channel MOSFET QMp passes and thus the loss of the rectifier circuit IDP increases.

When the rectifier circuit IDP for a consumer with an extremely low Power consumption is used and thus also the power consumption of the rectifier circuit IDP itself must be very low, can be considered as the resistance R2 a resistor with an excessively low resistance value cannot be used, and the current amplifying circuits are therefore useful. A consumer with an extremely low power consumption is, for example, a microcontroller in the idle state or temporarily interrupted state. When the resistance value of the resistor R2 is high, this limits the base current of the PNP transistor Q2 and also around the current amplification rate of the PNP transistor Q2 increased collector current. When the voltage E1 at the output terminal Vout is applied, is thus
through the PNP transistor Q2 the gate of the P-channel MOSFET QMp shorted to the source terminal, and the discharge of the charge on the gate solely through the PNP transistor Q2 takes time. On the other hand, when the current amplifying circuits are provided, the collector current of the PNP transistor becomes Q2 as the base current of the NPN transistor Q4 fed, which is why the to the current amplification rate of the NPN transistor Q4 increased current between the collector and emitter of the NPN transistor Q4 can flow. Therefore it is possible to reduce the charge on the gate of the P-channel MOSFET QMp to discharge quickly and the P-channel MOSFET QMp off so that the time for reverse current to flow can be shortened.

As discussed above, can be considered a resistance R3 do not use a resistor with an excessively low resistance value when using the rectifier circuit IDP is used for a consumer with an extremely low power consumption and thus also the power consumption of the rectifier circuit IDP itself must be very low. After removing the voltage E1 from the output terminal Vout therefore decreases the charging of the charge on the gate of the P-channel MOSFET QMp alone with the resistance R3 Time to complete. On the other hand, when the current amplifying circuits are present, the one in the resistor becomes R3 flowing current as the base current of the PNP transistor Q3 fed, which is why the to the current amplification rate of the PNP transistor Q3 increased current between the collector and emitter of the PNP transistor Q3 can flow. Therefore it is possible to adjust the gate capacitance of the P-channel MOSFET QMp Quickly charge and the P-channel MOSFET QMp turn on, which is why the time for the recovery of the output terminal Vout output consumer current can be shortened.

As described above, the rectifier circuit includes IDP of the first embodiment, the P-channel MOSFET QMp , the PNP transistor Q1 , the PNP transistor Q2 , the PNP transistor Q3 and the NPN transistor Q4 with opposing polarity, the resistance R1 , the resistance R2 , the resistance R3 , the resistance R4 , the input connector Vi and the output connector Vout . This configuration enables the rectifier circuit IDP the potential difference between the input terminal Vi and the output connector Vout can be set to an extremely low value (for example, 200 mV) compared to the forward voltage of a diode element (about 0.4 V to 0.7 V). In the rectifier circuit IPD, when an electromotive force is applied to the output terminal Vout connected and the potential of the output connection Vout higher than the potential of the input terminal Vi the reverse current can be compared to the absence of that through the PNP transistor Q3 and the NPN transistor Q4 formed amplification circuits are quickly blocked. In the case of the rectifier circuit IPD, the power supply to the consumer can also begin quickly after the electromotive force has been removed.

In the 1 The current amplification circuits of the first embodiment shown are formed by bipolar transistor elements, but can also be formed by MOSFET elements. 5 Fig. 13 is a view illustrating a modification example of the current amplifying circuits of the first embodiment. Off in the current amplification circuits 5 is used as the third transistor element instead of the PNP transistor Q3 a P-channel MOSFET Q3p used. As the fourth transistor element is used in place of the NPN transistor Q4 an N-channel MOSFET Q4n used. In the case of the P-channel MOSFET Q3p and the N-channel MOSFET Q4n the drain connection corresponds to the first connection, the source connection corresponds to the second connection and the gate connection corresponds to the third connection.

If in 5 the P point potential higher than the source potential of the N-channel MOSFET by the gate-source threshold potential Q4n is, the N-channel MOSFET switches Q4n one. When the N-Channel MOSFET Q4n turns on, the gate and source of the P-channel MOSFET become QMp shorted. When the P-point potential is lower than the source potential of the P-channel MOSFET by the gate-source threshold potential Q3p the P-channel MOSFET turns on Q3p one. When the P-Channel MOSFET Q3p turns on, the gate terminal and the ground become GND of the P-channel MOSFET QMp shorted.

Even if the Current amplification circuits through the P-channel MOSFET Q3p and the N-channel MOSFET Q4n are formed, thus results in the same mode of action as in the formation by the PNP transistor Q3 and the NPN transistor Q4 . When the current amplification circuits through the P-channel MOSFET Q3p and the N-channel MOSFET Q4n are formed whose on-resistance is low, there is also the possibility of the settling time of the P-channel MOSFET QMp to shorten further.

Second embodiment

6th Fig. 13 is a circuit diagram showing a configuration example of a rectifier circuit IDN illustrated according to a second embodiment. The rectifier circuit IDN comprises a P-channel MOSFET QMp , an NPN transistor Q11 , an NPN transistor Q12 , an NPN transistor Q13 , a PNP transistor Q14 , a resistor R1 , a resistor R2 , a resistor R3 and a resistor R4 .

The rectifier circuit IDN serves to use the N-channel MOSFET QMn the flow of reverse current from an output port Vout to an input port Vi to block. In the case of the N-channel MOSFET QMn is an enhancement type N-channel MOSFET device. A power supply Vcc is a potential related to the potential of the input terminal Vi is at least one potential Vth higher between gate and source, at which the N-channel MOSFET QMn can turn on. The size ratio of the potentials is thus Vcc> Vi + Vth.

The NPN transistor Q11 corresponds to the first NPN bipolar transistor element and the NPN transistor Q12 corresponds to the second NPN bipolar transistor element. The NPN transistor Q11 and the NPN transistor Q12 are used to detect the potential difference between the input connection Vi and the output connector Vout the rectifier circuit IDN .

The NPN transistor Q13 corresponds to the third transistor element and is an NPN bipolar transistor element. The PNP transistor Q14 corresponds to the fourth transistor element with opposite polarity to the third transistor element and is a PNP bipolar transistor element. With the NPN transistor Q13 and the PNP transistor Q14 the collector connection corresponds to the first connection, the emitter connection corresponds to the second connection and the base connection corresponds to the third connection. The NPN transistor Q13 and the PNP transistor Q14 are current amplifying circuits for charging and discharging a gate of the N-channel MOSFET QMn . In the steady state, flows between the collector and emitter of the NPN transistor Q13 and between the collector and emitter of the PNP transistor Q14 no electricity. When there is a voltage fluctuation at the input terminal Vi or at the output connector Vout , i.e. in a transient state in which the gate potential of the N-channel MOSFET QMn changed, flows between the collector and emitter of the NPN transistor Q13 and between the collector and emitter of the PNP transistor Q14 Current and the gate capacitance of the N-channel MOSFET QMn is subject to rapid charging and discharging.

As in 6th shown is a connection point between the source terminal of the N-channel MOSFET QMn and the emitter connection of the NPN transistor Q12 with the input connector Vi connected.

In 6th are the base connection and the collector connection of the NPN transistor Q11 shorted, and this NPN transistor Q11 is configured as an equivalent diode element. 7A and 7B show examples of the NPN transistor Q11 configured as an equivalent diode element. As in 6th and 7A shown corresponds to the NPN transistor Q11 the emitter connection corresponds to the cathode connection (K) of the equivalent diode element, and the connection point between the base connection and the collector connection corresponds to the anode connection (A) of the equivalent diode element. In this example, the emitter connection is the NPN transistor Q11 with one connection of the resistor R1 connected. The connection point between the base connection and the collector connection of the NPN transistor Q11 is to the base connection of the NPN transistor Q12 and one connection of the resistor R2 connected.

In the example from 7B corresponds to the collector connection of the NPN transistor Q11 the cathode connection (K) of the equivalent diode element, and with this collector connection is one connection of the resistor R1 connected. The base connection of the NPN transistor Q11 corresponds to the anode connection (A) of the equivalent diode element, and with this base connection are the base connection of the NPN transistor Q12 and one terminal of the resistor R2 connected. The emitter connection of the NPN transistor Q11 is open.

In 6th is a connection point between the other terminal of the resistor R2 , one connection of the resistor R3 and the collector connection of the NPN transistor Q13 with the power supply Vcc connected that has a higher potential than the input voltage of the input terminal Vi having. The other terminal of the resistor R3 , the collector connection of the NPN transistor Q12 , the base connection of the NPN transistor Q13 , the base connection of the PNP transistor Q14 and one terminal of the resistor R4 are connected. The emitter connection of the NPN transistor Q13 , the emitter connection of the PNP transistor Q14 , the other port of the Resistance R4 and the gate connection of the N-channel MOSFET QMn are connected. A connection point between the drain connection of the N-channel MOSFET QMn and the other terminal of the resistor R1 is with the output connector Vout connected.

Next is the steady state of the rectifier circuit IDN described.

In the steady state of the rectifier circuit IDN is a difference between the voltage V _BE between the base and emitter of the NPN transistor Q12 , the voltage between the base and emitter of the NPN transistor Q11 and the voltage between the base and emitter of the NPN transistor Q12 δ> 0, and the voltage between the base and emitter of the NPN transistor Q11 is V _BE + δ. A DC leakage current at the gate of the N-channel MOSFET QMn , a base current of the NPN transistor Q11 and a base current of the NPN transistor Q12 are ignored. The potential of the power supply Vcc is higher than the potential of the input terminal Vi . The resistance value of the resistor R2 is positive. Since in this case the emitter-side current and the collector-side current of the NPN transistor Q11 are the same result for the potential of the output connection Vout and the potential difference (i.e., the forward voltage) Vf between the input terminal Vi and the output connector Vout the relationships of equations (4) and (5) below.

$$\begin{array}{l}\frac{V_i-\delta -V_{Out}}{{\mathrm{R.}}_1}=\frac{V_{cc}-\left(V_i-V_{\mathrm{B.}\mathrm{E.}}\right)}{{\mathrm{R.}}_2}\\ \therefore V_{Out}=\left(1+{\mathrm{R.}}_1/{\mathrm{R.}}_2\right)V_i-\delta -\left({\mathrm{R.}}_1/{\mathrm{R.}}_2\right)\left(V_{cc}-V_{\mathrm{B.}\mathrm{E.}}\right)\end{array}$$

$$V_f=V_i-V_{Out}=\delta +\left({\mathrm{R.}}_1/{\mathrm{R.}}_2\right)\left(V_{cc}-V_i-V_{\mathrm{B.}\mathrm{E.}}\right)$$

$$\delta +\left({\mathrm{R.}}_1/{\mathrm{R.}}_2\right)\left(V_{cc}-V_i-V_{\mathrm{B.}\mathrm{E.}}\right)$$

If for the purpose of reducing the power consumption of the rectifier circuit IDN the saturation voltage on the N-channel MOSFET QMn (Product of the on-resistance of the N-channel MOSFET QMn and the current flowing between drain and source) is controlled to the smallest possible value, i.e. if the forward voltage Vf is to be expressed with equation (5), the forward voltage Vf in equation (5) must be greater than the minimum saturation voltage of the N-channel MOSFET QMn being. This condition is described below. For example, if in equation (5) is the resistance value of the resistor R1 compared to the resistance value of the resistor R2 is very small and, moreover, the difference δ is sufficiently small, a forward voltage Vf can be achieved which is lower than the forward voltage of a conventional diode element (about 0.7 V).

In equation (5), become the resistance value of the resistor R1 set to 0 and the difference δ set to 0 are the potential of the input terminal Vi and the potential of the output terminal Vout same. Therefore, the forward voltage is Vf and the saturation voltage of the N-channel MOSFET QMn theoretically 0 V.

In the case of a negative difference δ (<0) in equation (6), which is the right-hand side of equation (5), however, a virtual negative forward voltage Vf results. In this case, the voltage at the output terminal increases Vout at | Vf | except for the voltage of the input terminal Vi settling to a reverse current from the output terminal Vout to the input port Vi , making the function of the rectifier circuit IDN is affected. Even if for the NPN transistor Q11 and the NPN transistor Q12 Similar NPN bipolar transistor elements can be used due to individual deviations and differences in the respective ambient temperature of the NPN transistor Q11 and NPN transistor Q12 and the like happen that δ <0. To ensure that δ> 0 and to prevent reverse current, either the resistance value of the resistor must be R1 greater than 0 and equation (6) set to a positive value, or as a connection method for the NPN transistor Q11 must instead of the procedure 7A this in 7B methods shown can be used.

When the NPN transistor Q11 as in 7A is connected, the voltage between the anode connection (A) and the cathode connection (K) is equal to the voltage V _BE between the base and emitter of the NPN transistor Q12 , since the base current is 1 / H _{FE of} the collector current.

If, on the other hand, the NPN transistor Q11 as in 7B connected, all the current flows between the collector and the base, and the voltage gradient is large. The voltage between the anode connection (A) and the cathode connection (K) is thus stronger than in the case of 7A . Therefore δ> 0 results.

Next, referring to FIG 8th and 9 the operation of the rectifier circuit IDN in the event that described with the input connector Vi a DC power supply and to the output terminal Vout a consumer is connected. 8th Fig. 13 is an explanatory view of the operation of the rectifier circuit IDN the second embodiment in the event of a potential increase due to an external factor. It describes the change in the load current and the gate potential of the N-channel MOSFET QMn over time when in a steady state in which the output voltage at the output terminal Vout E0 is and a load current flows I0 and the gate potential of the N-channel MOSFET QMn V0 is, from the outside, a forced voltage E1 to the output terminal Vout higher than (Vi-Vf). The external factor in the following is one with the output port Vout connected external power supply.

9 Fig. 13 is an explanatory view of the gate capacitance of the N-channel MOSFET QMn . At the drain, gate and source connections of the N-channel MOSFET QMn there are electrical capacitances Cgd, Cgs, Cds. The gate capacitance Ciss of the N-channel MOSFET QMn is (Cgd + Cgs).

In 8th there is no voltage E1 from the external voltage supply at the output terminal up to a point in time t0 Vout on and the rectifier circuit IDN is in the steady state above.

At time t0, the collector connection and the base connection of the NPN transistor become Q11 short-circuited, which is why the voltage between the connection point between the collector connection and the base connection and the emitter connection is constant. When the voltage E1 to the output terminal Vout is applied, the base potential of the NPN transistor increases Q12 on, making the NPN transistor Q12 becomes more conductive, so that the potential at the P point (see 6th ), which is the connection point between the collector terminal of the NPN transistor Q12 and the other terminal of the resistor R3 acts, is lowered. Since, however, on the N-channel MOSFET QMn as in 9 shown the gate capacitance Ciss (= Cgd + Cgs) is charged by the potential difference between P-point and drain or by the potential difference between P-point and source, the gate potential of the N-channel MOSFET QMn not be lowered immediately.

When the N-Channel MOSFET QMn switches on (ON) and the potential on the P-point side is at least equal to the voltage V _BE between the base and emitter of the PNP transistor Q14 lower than the gate potential of the N-channel MOSFET QMn becomes, that is, when the potential difference between the two ends of the resistor R4 the voltage V _BE between the base and emitter of the PNP transistor Q14 increases, the PNP transistor switches Q14 one. By turning on the PNP transistor Q14 forming a current amplifying circuit, at time t0, there is an abrupt discharge of charge on the gate of the N-channel MOSFET QMn possible. During the discharge of the charge on the gate of the N-channel MOSFET QMn the potential of the gate drops. The time span from time t0 to time t1 in 8th is
an amplification period of the discharge by the current amplification circuit.

Since at time t1 the charge on the gate of the N-channel MOSFET QMn has been discharged, the potential difference between the two ends of the resistor will drop R4 below the voltage V _BE between the base and emitter of the PNP transistor Q14 which is why the PNP transistor Q14 switches off (OFF). From time t1, the gate of the N-channel MOSFET is slowly discharged QMn about the resistance R4 , and at time t2 the N-channel MOSFET switches QMn out. The gate potential at the time the N-channel MOSFET is switched off QMn is in 8th indicated as V1. The time span from time t1 to time t2 in 8th is the non-amplification period.

During the time span from time t0 to time t2, that is, the time of the settling of the N-channel MOSFET QMn from switch-on to switch-off depends on the gate potential of the N-channel MOSFET QMn to a reverse current from the output port Vout to the input port Vi .

If at time t4 the voltage E1 of the external voltage supply is no longer at the output connection Vout is applied, decreases due to the decrease in the base potential of the NPN transistor Q11 the voltage between the base and emitter of the NPN transistor Q12 , which is why the NPN transistor Q12 weaker conductors. From the point in time t4, the potential of the P point increases due to the resistance R3 . However, since at time t4 the gate capacitance of the N-channel MOSFET QMn is discharged, it is not possible to use the gate potential of the N-channel MOSFET QMn to increase immediately, i.e. to complete the charging of the gate capacitance.

When the NPN transistor Q12 turns off and the P-point-side potential around the voltage V _BE between the base and emitter of the NPN transistor Q13 higher than the gate potential of the N-channel MOSFET QMn becomes, that is, when the potential difference between the two ends of the resistor R4 the voltage V _BE between the base and emitter of the NPN transistor Q13 increases, the NPN transistor switches Q13 one. By turning on the NPN transistor Q13 , which constitutes a current amplifying circuit, at time t4 is a rapid charge of the gate capacitance of the N-channel MOSFET QMn possible. In the course of charging the charge on the gate of the N-channel MOSFET QMn the potential of the gate increases. The period from Time t4 to time t5 in 8th is a boosting period of charging by the current boosting circuit.

Since at time t5 the charge on the gate of the N-channel MOSFET QMn charged, the potential difference between the two ends of the resistor will drop R4 below the voltage V _BE between the base and emitter of the NPN transistor Q13 which is why the NPN transistor Q13 turns off. From the point in time t5, cause the resistance R3 and the resistance R4 a slow charging of the charge on the gate of the N-channel MOSFET QMn , and if at time t6 the gate potential of the N-channel MOSFET QMn When V0 is reached, the N-channel MOSFET switches QMn completely one. The time span from time t5 to time t6 in 8th is the non-amplification period.

Next, description will be made of the case that the rectifier circuit IDN the current amplification circuits of the NPN transistor Q13 and the PNP transistor Q14 are not present. In 8th are the gate potential of the N-channel MOSFET QMn and the consumer current in the event that the current amplification circuits are not present, shown with a dash-dot line.

When the voltage E1 of the external power supply at the output terminal Vout is applied, is the drop in potential at the gate of the N-channel MOSFET QMn compared to the presence of the current amplification circuits in the absence of the current amplification circuits. While reverse current flows in the time interval Ta between time t0 and time t2 when the current amplification circuit is present, the reverse current flows for a longer time interval Tb without the current amplification circuit, namely from time t0 to time t3. When the current boosting circuits are not in the rectifier circuit IDN are present, the duration of the flow of reverse current is thus lengthened, hence the possibility of damage to the one connected to the input port Vi connected power supply exists.

When there is no more voltage E1 at the output connection Vout is applied, the potential increase at the gate is N-channel MOSFET QMn compared to the presence of the current amplification circuit in the absence of the current amplification circuits. The time required for the recovery of the consumer current is therefore the time span Tc from time t4 to time t6 with the presence of the current amplification circuit, while without the current amplification circuits the longer time span Td results from time t4 to time t7, which is why there is more time until the N is fully switched on -Channel MOSFET QMn passes and thus the loss of the rectifier circuit IDN increases.

When the rectifier circuit IDN is used for a consumer with an extremely low power consumption and thus also the power consumption of the rectifier circuit IDN needs to be very small, as discussed in the first embodiment, the current amplifying circuits are useful.

As described above, the rectifier circuit includes IDN of the second embodiment, the N-channel MOSFET QMn , the NPN transistor Q11 , the NPN transistor Q12 , the NPN transistor Q13 and the PNP transistor Q14 with opposing polarity, the resistance R1 , the resistance R2 , the resistance R3 , the resistance R4 , the input connector Vi and the output connector Vout . This configuration enables the rectifier circuit IDN the potential difference between the input terminal Vi and the output connector Vout can be set to an extremely low value (for example, 200 mV) compared to the forward voltage of a diode element (0.4 V to 0.7 V). If at the rectifier circuit IDN an electromotive force to the output terminal Vout connected and the potential of the output connection Vout higher than the potential of the input terminal Vi the reverse current can be compared to the absence of that through the NPN transistor Q13 and the PNP transistor Q14 formed amplification circuits are quickly blocked. Can also be used in the rectifier circuit IDN after removing the electromotive force, quickly start supplying power to the consumer.

In the 6th The shown current amplification circuits of the second embodiment are formed by bipolar transistor elements, but can also be formed by MOSFET elements.

10 FIG. 13 is a view illustrating a modification example of the current amplifying circuits of the second embodiment. Off in the current amplification circuits 10 is used as the third transistor element instead of the NPN transistor Q13 an N-channel MOSFET Q13n used. As the fourth transistor element is used in place of the PNP transistor Q14 a P-channel MOSFET Q14p used. In the case of the N-channel MOSFET Q13n and the P-channel MOSFET Q14p the drain connection corresponds to the first connection, the source connection corresponds to the second connection and the gate connection corresponds to the third connection.

If in 10 the P point potential higher than that by the gate-source threshold potential Source potential of the N-channel MOSFET Q13n is, the N-channel MOSFET switches Q13n one. When the N-Channel MOSFET Q13n turns on, the gate connection and the power supply Vcc of the N-channel MOSFET QMn shorted. When the P-point potential is lower than the source potential of the P-channel MOSFET by the gate-source threshold potential Q14p the P-channel MOSFET turns on Q14p one. When the P-Channel MOSFET Q14p turns on, the gate and source of the N-channel MOSFET become QMn shorted.

Even if the current amplification circuits through the N-channel MOSFET Q13n and the P-channel MOSFET Q14p are formed, thus results in the same mode of action as in the formation by the NPN transistor Q13 and the PNP transistor Q14 . When the current amplifying circuits through the N-channel MOSFET Q13n and the P-channel MOSFET Q14p are designed whose on-resistance is low, there is also the possibility of the settling time of the N-channel MOSFET QMp to shorten further.

Next, an example of a booster circuit that increases the voltage of the power supply will be described Vcc the second embodiment generated.

11 Fig. 13 is a view showing a circuit example of the power supply Vcc illustrated in the second embodiment. The booster circuit is through a switching section SW that performs switching operations, a capacitor C11 , a capacitor C12 , a diode D11 and a diode D12 educated. The condenser C11 corresponds to the first capacitor and the capacitor C12 corresponds to the second capacitor. The diode D11 corresponds to the first diode element and the diode D12 corresponds to the second diode element. The forward voltage of the diode D11 and the diode D12 is in each case Vf.

With the output connector Vout the rectifier circuit IDN are the input side of the switching section SW , the anode connection of the diode D11 and one connection of the capacitor C12 connected. The output side of the switching section SW and one connection of the capacitor C11 are connected. The other terminal of the capacitor C11 , the cathode connection of the diode D11 and the anode connection of the diode D12 are connected. The connection point between the other terminal of the capacitor C11 , the cathode connection of the diode D11 and the anode connection of the diode D12 is considered a Q point. The connection point between the cathode connection of the diode D12 and the other connection of the capacitor C12 is to the connection point between the other terminal of the resistor R2 , one connection of the resistor R3 and the collector connection of the NPN transistor Q13 connected.

The switching section SW is a circuit of a DC-DC converter or the like that generates a sine wave that varies with duty cycle values that are neither 0% nor 100%. The switching section SW is with the output connector Vout connected and performs switching operations between the potential of the output terminal Vout and the potential of the crowd GND out. When the switching section SW on the potential of the earth GND is located via the diode D11 on the capacitor C11 the potential (Vout-Vf) is charged and smoothed to the DC potential of (Vout-Vf). When the switching section SW at the potential of the output terminal Vout takes the potential of the output terminal Vout about the DC potential of (Vout-Vf) with which the capacitor C11 charged to, making the potential of the Q point (2xVout-Vf). The condenser C12 is going through the diode D12 charged with this potential, which is thereby smoothed, thus acting as a voltage supply Vcc the DC potential (2x (Vout-Vf)) is obtained.

The booster circuit off 11 is just an example of the power supply Vcc , and the power supply Vcc is not limited to this booster circuit.

Third embodiment

12th Fig. 13 is a circuit diagram showing a configuration example of a rectifier circuit IDP illustrated according to a third embodiment. The rectifier circuit IDP of the third embodiment is configured such that the in 1 shown rectifier circuit IDP the first embodiment a Zener diode Double room was added. Elements of the third embodiment associated with 1 until 5 are identical or correspond to these are provided with the same reference numerals and their description is omitted.

The anode connection of the Zener diode Double room is to the base connection of the NPN transistor Q4 connected, and the cathode connection of the Zener diode Double room is with the output connector Vout connected. The Zener diode Double room limits a voltage V _GS between the gate and source of the P-channel MOSFET QMp . However, it applies that the Zener voltage of the Zener diode Double room at least one voltage V _GS between gate and source, at which an on-resistance can be guaranteed, at which the P-channel MOSFET QMp that of the consumer at the output connection Vout can allow the required output current to flow sufficiently. Since in this way the gate potential of the P-channel MOSFET QMp only drops to the potential that, after subtracting the Z-voltage, is from the potential of the output connection Vout (i.e. from the source-side potential), it can be prevented that the P-channel MOSFET QMp approaches a state of saturation further than necessary. Since in the transient state of the P-channel MOSFET QMp that charge size of the gate capacitance that needs to be changed, namely the fluctuation amplitude of the gate potential, can be restricted, the transient response of the P-channel MOSFET is improved QMp in relation to a potential increase at the output connection Vout about the potential of the input connection Vi out. This is in 13th shown.

13th Fig. 13 is an explanatory view of the operation of the rectifier circuit IDP the third embodiment in the event that the Zener diode Double room is available. In 13th becomes just like in 3 the change in the load current and the gate potential of the P-channel MOSFET QMp described over time when in a steady state in which the output voltage at the output terminal Vout E0 is and a load current flows I0 and the gate potential of the P-channel MOSFET QMp V0 is, from the outside, a forced voltage E1 to the output terminal Vout higher than (Vi-Vf). The gate potential of the P-channel MOSFET QMp and the consumer current in the event that the Zener diode Double room is present are shown with a dashed line. The gate potential of the P-channel MOSFET QMp and the consumer current in the event that the Zener diode Double room does not exist are shown with a dash-dotted line.

If no Zener diode Double room is present, is the gate potential of the P-channel MOSFET QMp V0. When the Zener diode Double room the gate potential increases from V0 to V0 _DZ (> V0) and thereby despite the alleviation of the degree of saturation of the P-channel MOSFET QMp a sufficient consumer current can be guaranteed, the duration of the flow of reverse current from the output connection can be increased by raising the gate potential from V0 to V0 _DZ Vout to the input port Vi be shortened. This means that the period of time for reverse current to flow is sufficient in the event that there is no Zener diode Double room is present from time t0 to time t2, during the period of flow of reverse current in the event that the Zener diode Double room is present, extends from time t0 to time t8 (<t2). The time for the recovery of the consumer current, that is to say the time from time t4 to time t6, depends on the presence or absence of the Zener diode Double room unaffected.

As described above, the rectifier circuit includes IDP of the third embodiment, the Zener diode Double room whose cathode connection with the output connection Vout is connected and its anode connection to the base connection of the NPN transistor Q4 connected is. Because by this configuration, the fluctuation amplitude of the gate potential of the P-channel MOSFET QMp can be restricted, the time of flow of reverse current from the output port Vout to the input port Vi be shortened.

Fourth embodiment

14th Fig. 13 is a circuit diagram showing a configuration example of a rectifier circuit IDN illustrated according to a fourth embodiment. The rectifier circuit IDN of the fourth embodiment is configured such that the in 6th shown rectifier circuit IDN the second embodiment a Zener diode Double room was added. Elements of the fourth embodiment associated with 6th until 11 are identical or correspond to these are provided with the same reference numerals and their description is omitted.

The anode connection of the Zener diode Double room is with the input connector Vi connected and the cathode connection of the Zener diode Double room is to the base connection of the PNP transistor Q14 connected. The Zener diode Double room limits a voltage V _GS between the gate and source of the N-channel MOSFET QMn . However, it applies that the Zener voltage of the Zener diode Double room at least one voltage V _GS between gate and source, at which an on-resistance can be guaranteed, at which the N-channel MOSFET QMn that of the consumer at the output connection Vout can allow the required output current to flow sufficiently. There
in this way the gate potential of the N-channel MOSFET QMn only increases up to the potential that is added to the potential of the output connection when the Z voltage is added Vout (i.e. from the source-side potential), it can be prevented that the N-channel MOSFET QMn enters a state of saturation further than necessary. As in the transient state of the N-channel MOSFET QMn that charge size of the gate capacitance that needs to be changed, namely the fluctuation amplitude of the gate potential, can be restricted, the transient response of the N-channel MOSFET is improved QMn in relation to a potential increase at the output connection Vout about the potential of the input connection Vi out. This is in 15th shown.

15th Fig. 13 is an explanatory view of the operation of the rectifier circuit IDN the fourth embodiment for the case that a Zener diode Double room is available. In 15th becomes just like in 8th the change in the load current and the gate potential of the N-channel MOSFET QMn described in the course of time when in a steady state State in which the output voltage at the output terminal Vout E0 is and a load current flows I0 and the gate potential of the N-channel MOSFET QMn V0 is, from the outside, a forced voltage E1 to the output terminal Vout higher than (Vi-Vf). The gate potential of the N-channel MOSFET QMn and the consumer current in the event that the Zener diode Double room is present are shown with a dashed line. The gate potential of the N-channel MOSFET QMn and the consumer current in the event that the Zener diode Double room does not exist are shown with a dash-dotted line.

If no Zener diode Double room is present, is the gate potential of the N-channel MOSFET QMn V0. When the Zener diode Double room the gate potential drops from V0 to V0 _DZ (<V0) and thereby despite the reduction in the degree of saturation of the N-channel MOSFET QMn a sufficient consumer current can be guaranteed, the duration of the flow of reverse current from the output connection can be reduced by lowering the gate potential from V0 to V0 _DZ Vout to the input port Vi be shortened. This means that the period of time for reverse current to flow is sufficient in the event that there is no Zener diode Double room is present from time t0 to time t2, during the period of flow of reverse current in the event that the Zener diode Double room is present, extends from time t0 to time t8 (<t2). The time for the recovery of the consumer current, that is to say the time from time t4 to time t6, depends on the presence or absence of the Zener diode Double room unaffected.

As described above, the rectifier circuit includes IDN the Zener diode Double room , whose anode connection with the input connection Vi is connected and its cathode connection to the base connection of the PNP transistor Q14 connected is. Since this configuration reduces the fluctuation amplitude of the gate potential of the N-channel MOSFET QMn can be restricted, the time of flow of reverse current from the output port Vout to the input port Vi be shortened.

Fifth embodiment

16 Fig. 13 is a circuit diagram showing a configuration example of a DC power supply combination circuit 1 illustrated according to a fifth embodiment. Elements of the fifth embodiment associated with 1 until 15th are identical or correspond to these are provided with the same reference numerals and their description is omitted.

The DC power supply combination circuit 1 is by combining n rectifier circuits ID1-IDn (where n is any integer) and m common diodes D1-Dm (where m is any integer). With the rectifier circuits ID1-IDn it is any of the rectifier circuit IDP of the first embodiment, the rectifier circuit IDN of the second embodiment, the rectifier circuit IDP the third embodiment and the rectifier circuit IDN the fourth embodiment. The rectifier circuits ID1- IDN are ideal diode circuits with a forward voltage lower than that of conventional diodes D1-Dm is. The following are the rectifier circuits ID1-IDn as rectifier circuits ID1-IDn with a low voltage gradient ‟. Among the rectifier circuits ID1-IDn with a small voltage gradient, the rectifier circuit IDP and the rectifier circuit IDN present mixed with one another. In this case, the rectifier circuit is the same IDP a first rectifier circuit and the rectifier circuit IDN a second rectifier circuit.

With the input connectors Vi of the rectifier circuits ID1-IDn DC voltage supplies are used with a small voltage gradient Vi1-Vin connected. The reference potential Vref is used to supply drive current to the rectifier circuits ID1-IDn with a small voltage gradient. The reference potential Vref the rectifier circuit IDP is the crowd GND , their potential in relation to the potential of the input terminal Vi is at least lower by the potential between the gate and source at which the P-channel MOSFET QMp can turn on. The reference potential Vref the rectifier circuit IDN is the power supply Vcc , their potential in relation to the potential of the input terminal Vi is at least higher by the potential between gate and source at which the N-channel MOSFET QMn can turn on. With the anode connections of the diodes D1-Dm are DC power supplies Ei1-Eim connected. All cathode connections of the diodes D1-Dm and all output connections Vout of the rectifier circuits ID1-IDN with a small voltage gradient are connected. V0 is the output voltage of the DC power supply combination circuit 1 .

A concrete example of the DC power supply combination circuit will now be given 1 described. n = 1 and m = 1, and the DC power supply Egg1 is 12 V. The rectifier circuit ID1 with a small voltage drop is a rectifier circuit IDP and the DC power supply Vi1 is 5 V. The reference potential Vref is the potential of the crowd GND . If the output power is constant with this configuration, the supply voltage is high on the 12 V side, whose power consumption is low, which is why the voltage gradient of the diode is high D1 with regard to the supply voltage can be ignored can, and also the loss of power on the diode D1 can be ignored. Therefore, the usual diode D1 are used whose voltage gradient in relation to the DC voltage supply Egg1 big, but inexpensive. On the other hand, on the 5 V side with the high power consumption, the supply voltage is low, which is why the size of the voltage gradient in relation to the supply voltage cannot be ignored and the power loss at the diode cannot be ignored either. Hence the rectifier circuit IDP used, which is an ideal diode circuit, whose voltage gradient in relation to the DC voltage supply Vi1 is low, but it is more expensive. Therefore, it is with the DC power supply combination circuit 1 possible to agree a limitation of power losses and a limitation of costs.

As described above, the DC power supply combination circuit comprises 1 of the fifth embodiment, the DC power supplies Ei1-Eim , Vi1-Vin who have favourited rectifier circuits ID1-IDn with a small voltage gradient and the diodes D1-Dm . Ei1-Eim are each connected to the anode connections of the diodes D1-Dm connected. The DC power supplies Vi1-Vin are each with the input connections Vi of the rectifier circuits ID1-IDn associated with a low voltage gradient. The cathode connections of the diodes D1-Dm and the output terminals Vout of the rectifier circuits ID1-IDn with a small voltage gradient are connected. Thus, with the DC power supplies Ei1-Eim whose supply voltage is high and whose power consumption is low, the usual diodes D1-Dm connected while with the DC power supplies Vi1-Vin whose supply voltage is low and whose power consumption is high, the rectifier circuits ID1-IDn connect with a low voltage gradient, which are ideal diode circuits, whereby the limitation of power losses and the limitation of costs can be agreed with each other.

The DC power supply combination circuit 1 The fifth embodiment is configured such that in addition to at least one of the rectifier circuit IDP and the rectifier circuit IDN at least one diode D1 is used, but configuration is also possible with only at least one of the rectifier circuit IDP and the rectifier circuit IDN is used.

Sixth embodiment

17th Fig. 13 is a circuit diagram showing a configuration example of a full-wave rectifying circuit 2 illustrated according to a sixth embodiment. Elements of the sixth embodiment associated with 1 until 15th are identical or correspond to these are provided with the same reference numerals and their description is omitted.

The full wave rectifier circuit 2 is a full-wave bridge-type rectifier circuit powered by a transformer Tr subjected the output AC voltage to full-wave rectification. The transformer Tr comprises a primary winding, a secondary winding and a center tap provided on the secondary winding. The full wave rectifier circuit 2 uses the center tap as reference potential and leads using rectifier circuits IDP1 , IDP2 on the positive potential side and rectifier circuits IDN1 , IDN2 full-wave rectification on the negative potential side. The rectifier circuits IDP1 , IDP2 are each a rectifier circuit IDP of the first embodiment or a rectifier circuit IDP
the third embodiment. The rectifier circuits IDN1 , IDN2 are each a rectifier circuit IDN of the second embodiment or a rectifier circuit IDN the fourth embodiment. The rectifier circuits IDP1 , IDP2 , IDN1 , IDN2 are ideal diode circuits with low forward voltage. With the output side of the full wave rectifier circuit 2 are about capacitors C1 , C2 for residual ripple smoothing consumers Za , E.g. , Zc connected.

As in 17th shown, one output side of the secondary winding is the input terminal Vi the rectifier circuit IDP1 and the output connector Vout the rectifier circuit IDN2 connected. With the other output side of the secondary winding are the input connection Vi the rectifier circuit IDP2 and the output connector Vout the rectifier circuit IDN1 connected. The connection point between the output port Vout the rectifier circuit IDP1 , the output connector Vout the rectifier circuit IDP2 and one connection of the capacitor C1 is an output terminal with positive power supply. + V1 is the output potential of the positive voltage supply in relation to the reference potential of the center tap. The connection point between the, input port Vi the rectifier circuit IDN1 , the input connector Vi the rectifier circuit IDN2 and one connection of the capacitor C2 is an output terminal with negative power supply. -V1 is the output potential of the negative voltage supply in relation to the reference potential of the center tap. The crowd GND the rectifier circuit IDP1 , the crowd GND the rectifier circuit IDP2 , the power supply Vcc the rectifier circuit IDN1 , the power supply Vcc the Rectifier circuit IDN2 , the other terminal of the capacitor C1 and the other terminal of the capacitor C2 are connected to the center tap.

As described above, it is the full wave rectifier circuit 2 of the sixth embodiment, a full-wave bridge type rectifier circuit constituted by four rectifier circuits IDP1 , IDP2 , IDN1 , IDN2 is formed and undergoes from the transformer Tr output AC voltage of a full wave rectification. Because the full wave rectifier circuit 2 through the four rectifier circuits IDP1 , IDP2 , IDN1 , IDN2 which are ideal diode circuits with a low forward voltage, power loss can be restrained as compared with a full-wave bridge-type rectifier circuit using conventional diode elements.

Seventh embodiment

18th Fig. 13 is a circuit diagram showing a configuration example of a full-wave rectifying circuit 3 illustrated according to a seventh embodiment. Elements of the seventh embodiment associated with 1 until 15th are identical or correspond to these are provided with the same reference numerals and their description is omitted.

The full wave rectifier circuit 3 is a full-wave bridge-type rectifier circuit generated by a three-phase generating circuit 4th subjects output three-phase AC voltage to full-wave rectification. The three-phase generating circuit 4th includes sinusoidal power supplies Eu , Possibly , Ew of the three phases and a neutral point Vn with which the sinusoidal voltage supplies Eu , Possibly , Ew are connected. The sinusoidal voltage supply Possibly has a phase angle that is opposite to the sinusoidal voltage supply Eu is delayed by 2 π / 3. The sinusoidal voltage supply Ew has a phase angle that is opposite to the sinusoidal voltage supply Possibly is delayed by 2 π / 3. The full wave rectifier circuit 3 uses the neutral point Vn as reference potential and leads for the individual phases using rectifier circuits IDP3 , IDP4 , IDP5 on the positive potential side and rectifier circuits IDN3 , IDN4 , IDN5 full-wave rectification on the negative potential side. The rectifier circuits IDP3 , IDP4 , IDP5 are each a rectifier circuit IDP of the first embodiment or a rectifier circuit IDP the third embodiment. The rectifier circuits IDN3 , IDN4 , IDN5 are each a rectifier circuit IDN of the second embodiment or a rectifier circuit IDN the fourth embodiment. The rectifier circuits IDP3 , IDP4 , IDP5 , IDN3 , IDN4 , IDN5 are ideal diode circuits with low forward voltage. With the output side of the full wave rectifier circuit 3 is through a capacitor C3 a consumer for smoothing residual ripple Zd connected.

As in 18th are shown with the output side of the sinusoidal voltage supply Eu the three-phase generating circuit 4th the input port Vi the rectifier circuit IDP3 and the output connector Vout the rectifier circuit IDN3 connected. With the output side of the sinusoidal voltage supply Ew are the input port Vi the rectifier circuit IDP4 and the output connector Vout the rectifier circuit IDN4 connected. With the output side of the sinusoidal voltage supply Possibly are the input port Vi the rectifier circuit IDP5 and the output connector Vout the rectifier circuit IDN5 connected. The respective mass GND of the rectifier circuits IDP3 , IDP4 , IDP5 and the respective power supplies Vcc of the rectifier circuits IDN3 , IDN4 , IDN5 are with the neutral point Vn connected. The connection point between the output ports Vout of the rectifier circuits IDP3 , IDP4 , IDP5 on the positive potential side and one terminal of the capacitor C3 is an output terminal with positive power supply. The connection point between the input ports Vi of the rectifier circuits IDN3 , IDN4 , IDN5 on the negative potential side and the other terminal of the capacitor C3 is an output terminal with negative power supply. V2 is the output potential at the consumer Zd .

As described above, it is the full wave rectifier circuit 3 of the seventh embodiment, a full-wave bridge type rectifier circuit constituted by six rectifier circuits IDP3 , IDP4 , IDP5 , IDN3 , IDN4 , IDN5 is formed, and undergoes from the the neutral point Vn having three-phase generating circuit 4th output three-phase AC voltage of a full-wave rectification. Because the full wave rectifier circuit 3 through the six rectifier circuits IDP3 , IDP4 , IDP5 , IDN3 , IDN4 , IDN5 which are ideal diode circuits with a low forward voltage, power loss can be restrained as compared with a full-wave bridge-type rectifier circuit using conventional diode elements.

In the seventh embodiment, it is the full-wave rectifying circuit 3 designed such that it subjects three-phase AC voltage to full-wave rectification, but it can also be designed such that it receives an AC voltage Full-wave rectification of n phases (n≥4).

In the present invention, it is possible, within the scope of the invention, to freely combine the various embodiments, to make modifications to any configuration elements of the embodiments, or to omit any configuration elements of the embodiments.

Commercial use

The rectifier circuit according to the invention has an extremely small potential difference between input and output and a good response behavior and is suitable for voltage supply combination circuits and rectifier circuits which require a fast response with a low loss.

List of reference symbols

1

DC power supply combination circuit

2, 3

Full wave rectifier circuit

4th

Three-phase generating circuit

C1, C2, C3, C11, C12

capacitor

D1-Dm, D11, D12

diode

Double room

Zener diode

Ei1-Eim, Vi1-Vin

DC power supply

Eu, Ev, Ew

Sinus voltage supply

GND

Dimensions

ID1-IDn, IDP, IDN, IDP1, IDP2, IDP3, IDP4, IDP5, IDN1, IDN2, IDN3, IDN4, IDN5

Rectifier circuit

Q1, Q2, Q3, Q14

PNP transistor

Q4, Q11, Q12, Q13

NPN transistor

Q3p, Q14p, QMp

P-channel MOSFET

Q4n, Q13n, QMn

N-channel MOSFET

R1, R2, R3, R4

resistance

SW

Switching section

Tr

transistor

Vi

Input connector

Vcc

Power supply

Vn

Neutral point

Vout

Output connector

Vref

Reference potential

Za, Zb, Zc, Zd

consumer

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• JP S6212332 [0003]

Claims (18)

A rectifier circuit (IDP) comprising: a P-channel MOSFET element (QMp), a first PNP bipolar transistor element (Q1), a second PNP bipolar transistor element (Q2), a third transistor element (Q3) and a fourth transistor element (Q4) having of opposite polarity, a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), an input connection (Vi) and an output connection (Vout), characterized in that a connection point between a drain connection of the P-channel MOSFET element and a connection of the first resistor is connected to the input connection, the first PNP bipolar transistor element forms an equivalent diode element, an anode connection (A) of the equivalent diode element and another connection of the first Resistance are connected and a cathode connection (K) of the equivalent diode element, a base connection of the second PNP bipolar transistor element and a r connection of the second resistor are connected, a connection point between another connection of the second resistor, a connection of the third resistor and a first connection of the third transistor element are connected to ground (GND), another connection of the third resistor, a collector connection of the second PNP bipolar transistor element, a third connection of the third transistor element, a third connection of the fourth transistor element and a one connection of the fourth resistor are connected, a second connection of the third transistor element, a second connection of the fourth transistor element, another connection of the fourth resistor and a gate Connection of the P-channel MOSFET element and a connection point between an emitter connection of the second PNP bipolar transistor element, a source connection of the P-channel MOSFET element and a first connection of the fourth transistor element with the output flange luss are connected. Rectifier circuit according to Claim 1 , characterized in that an emitter connection of the first PNP bipolar transistor element is the anode connection of the equivalent diode element and a connection point between a base connection and a collector connection of the first PNP bipolar transistor element is the cathode connection of the equivalent diode element. Rectifier circuit according to Claim 1 , characterized in that a collector connection of the first PNP bipolar transistor element is the anode connection of the equivalent diode element, a base connection of the first PNP bipolar transistor element is the cathode connection of the equivalent diode element and the emitter connection of the first PNP bipolar transistor element is open. Rectifier circuit according to Claim 1 , characterized by a Zener diode element (DZ), a cathode connection being connected to the output connection and an anode connection being connected to the third connection of the fourth transistor element. Rectifier circuit according to Claim 1 , characterized in that the third transistor element is a PNP bipolar transistor element (Q3), the first connection, the second connection and the third connection of the third transistor element are each a collector connection, an emitter connection and a base connection of the PNP bipolar transistor element, the fourth The transistor element is an NPN bipolar transistor element (Q4) and the first connection, the second connection and the third connection of the fourth transistor element are each a collector connection, an emitter connection and a base connection of the NPN bipolar transistor element. Rectifier circuit according to Claim 1 , characterized in that the third transistor element is a P-channel MOSFET element (Q3p), the first connection, the second connection and the third connection of the third transistor element are each a drain connection, a source connection and a gate connection of the P-channel MOSFET element, the fourth transistor element is an N-channel MOSFET element (Q4n) and the first connection, the second connection and the third connection of the fourth transistor element are each a drain connection, a source connection and a gate terminal of the N-channel MOSFET element. A rectifier circuit (IDN) comprising: an N-channel MOSFET element (QMn), a first NPN bipolar transistor element (Q11), a second NPN bipolar transistor element (Q12), a third transistor element (Q13) and a fourth transistor element (Q14) of opposite polarity, a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), an input connection (Vi) and an output connection (Vout), characterized in that a connection point between a source connection of the N-channel MOSFET element and an emitter connection of the second NPN Bipolar transistor element is connected to the input terminal, the first NPN bipolar transistor element forms an equivalent diode element, wherein an anode terminal (A) of the equivalent diode element, a base terminal of the second NPN bipolar transistor element and a terminal of the second resistor are connected, a connection point between another terminal of the second resistor, a terminal of the third resistor and a first terminal of the third transistor element are connected to a voltage supply (Vcc) whose potential is higher than the input voltage of the input terminal, another terminal of the third resistor, a collector terminal of the second NPN bipolar transistor element , a third connection of the third transistor element, a third connection of the fourth transistor element and a connection of the fourth resistor are connected, a second connection of the third transistor element, a second Ans Connection of the fourth transistor element, another connection of the fourth resistor and a gate connection of the N-channel MOSFET element are connected, a cathode connection (K) of the equivalent diode element and one connection of the first resistor are connected and a connection point between a drain Terminal of the N-channel MOSFET element and another terminal of the first resistor is connected to the output terminal. Rectifier circuit according to Claim 7 , characterized in that an emitter connection of the first NPN bipolar transistor element is the cathode connection of the equivalent diode element and a connection point between a base connection and a collector connection of the first NPN bipolar transistor element is the anode connection of the equivalent diode element. Rectifier circuit according to Claim 7 , characterized in that a collector connection of the first NPN bipolar transistor element is the cathode connection of the equivalent diode element, a base connection of the first NPN bipolar transistor element is the anode connection of the equivalent diode element and the emitter connection of the first NPN bipolar transistor element is open. Rectifier circuit according to Claim 7 , characterized by a Zener diode element (DZ), an anode connection being connected to the input connection and a cathode connection being connected to the third connection of the fourth transistor element. Rectifier circuit according to Claim 7 , characterized in that the power supply, the potential of which is higher than the input voltage of the input terminal, is a booster circuit formed by a switching section (SW) that performs a switching operation, a first capacitor (C11), a second capacitor (C12) first diode element (D11) and a second diode element (D12) is formed, wherein an input side of the switching section, an anode terminal of the first diode element and one terminal of the second capacitor are connected to the output terminal, an output side of the switching section and one terminal of the first capacitor are connected, another connection of the first capacitor, a cathode connection of the first diode element and an anode connection of the second diode element are connected and a connection point between a cathode connection of the second diode element and another connection of the second capacitor with a connection point between hen the other terminal of the second resistor, one terminal of the third resistor and the first terminal of the third transistor element is connected. Rectifier circuit according to Claim 7 , characterized in that the third transistor element is an NPN bipolar transistor element (Q13), the first connection, the second connection and the third connection of the third transistor element are respectively a collector connection, an emitter connection and a base connection of the NPN bipolar transistor element, the fourth The transistor element is a PNP bipolar transistor element (Q14) and the first terminal, the second terminal and the third terminal of the fourth transistor element are respectively a collector terminal, an emitter terminal and a base terminal of the PNP bipolar transistor element. Rectifier circuit according to Claim 7 , characterized in that the third transistor element is an N-channel MOSFET element (Q13n), the first connection, the second connection and the third connection of the third transistor element are each a drain connection, a source connection and a gate connection of the N-channel MOSFET element, the fourth transistor element is a P-channel MOSFET element (Q14p), and the first connection, the second connection and the third connection of the fourth transistor element are each a drain connection, a source connection and a gate terminal of the P-channel MOSFET element. DC voltage source combination circuit (1), comprising a plurality of DC voltage sources (Ei1-Eim, Vi1-Vin), the rectifier circuit (IDP, ID1-IDn) to Claim 1 and a diode element (D1-Dm), characterized in that the plurality of DC voltage sources are each connected to the input connection of the rectifier circuit or an anode connection of the diode element and all output connections of the rectifier circuit are connected to all cathode connections of the diode element. DC voltage source combination circuit (1), comprising a plurality of DC voltage sources (Eil-Eim, Vil-Vin), the rectifier circuit (IDN, ID1-IDn) according to Claim 7 and a diode element (D1-Dm), characterized in that the plurality of direct voltage sources are each connected to the input connection of the rectifier circuit or an anode connection of the diode element and the respective output connections of the rectifier circuit which are connected to the direct voltage sources are connected to the respective cathode connections of the diode element are. DC voltage source combination circuit (1), comprising a plurality of DC voltage sources (Ei1-Eim, Vi1-Vin), a first rectifier circuit (IDP, IDl-IDn), which is the rectifier circuit (IDN, IDl-IDn) according to Claim 1 is a second rectifier circuit, which is the rectifier circuit after Claim 7 acts, and a diode element (D1-Dm), characterized in that the DC voltage sources are each connected to the input connection of the first rectifier circuit, to the input connection of the second rectifier circuit or to an anode connection of the diode element and all output connections of the first rectifier circuit and all output connections of the second Rectifier circuit are connected to a cathode terminal of the diode element. Full-wave rectifier circuit (2), which is a full-wave rectifier circuit of the bridge type, which subjects an alternating voltage of a transformer (Tr) with a primary winding, a secondary winding and a center tap provided on the secondary winding to a full-wave rectification, characterized by two rectifier circuits (IDP) according to Claim 1 and two rectifier circuits (IDN) according to Claim 7 . Full-wave rectifier circuit (3), which is a full-wave bridge-type rectifier circuit that converts an n-phase alternating voltage of an n-phase alternating current generator circuit (4) with a neutral point (Vn) with which an n-phase (where n is an integer of 3 or greater) sinusoidal voltage supply (Eu, Ev, Ew) is connected, subjected to a full-wave rectification, characterized by n rectifier circuits (IDP) according to Claim 1 and n rectifier circuits (IDN) according to Claim 7 .

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