DE112019004175T5 - Electro-optical device, electronic device and control method - Google Patents

Abstract

The present invention realizes a pixel circuit which is advantageous for a high-precision pixel layout in which the number of elements is small. This electro-optical device comprises a pixel circuit (11) which is intended to be connected to a relay line (12-2) and a scan line (16), and a control circuit which controls the pixel circuit, the control circuit being designed to perform from driving to: switching on a first transistor (WS), a second transistor (AZ2) and a fourth transistor (AZ1) in a light-emitting time period of a light-emitting element (OLED); and, upon transition to an erase time period, writing an erase power source (Vss) to a gate electrode of a drive transistor (Drv) via the first transistor, the second transistor, a third transistor (DS) and the fourth transistor, turning off the third transistor for correction a threshold voltage for the drive transistor, and adapting the voltage of the gate electrode of the drive transistor to a voltage which represents the threshold voltage.

Description

TECHNICAL AREA

The present technology relates to an electro-optical device, an electronic device and a driving method.

STATE OF THE ART

Electro-optical devices using elements with organic light-emitting diodes (hereinafter referred to as OLED) or the like as light-emitting elements are known. In the electro-optical devices, pixel circuits including the light emitting elements, transistors or the like are provided at intersections of scan lines and data lines to correspond to pixels. In the pixel circuit, when a data signal of a potential according to a gradation level of pixels is applied to a gate of the transistor, the transistor supplies a current according to a gate-source voltage to the light-emitting element, and the light-emitting element emits light having a luminance according to the Gradation level.

When a threshold voltage (hereinafter referred to as Vth for convenience) of the transistor provided in each pixel varies, the current flowing through the light-emitting element varies and the image quality deteriorates. In order to prevent the picture quality from deteriorating, it is necessary to compensate for variations in Vth. In the case of compensation, a method is known in which a drain and the gate of the transistor are coupled to a feed line of the data signal supplied in each column and the potential is set to a value in accordance with the threshold voltage of the transistor.

However, since a parasitic capacitor is associated with the lead of the data signal, the parasitic capacitor is also charged or discharged when a compensation operation is performed. A period of the compensation process is extended by the time required to charge or discharge the parasitic capacitor. In addition, if a period of the compensation operation is set without considering the time required for charging or discharging the parasitic capacitor, the compensation becomes insufficient.

Patent Document 1 aims to make a compensation operation for compensating for variations in Vth faster. One aspect disclosed in Patent Document 1 is a circuit structure having a “relay line” that couples a plurality of pixels in a V direction and is used to hold charges at the time of correcting Vth of each pixel, thereby achieving high-speed driving.

REFERENCE LIST

PATENT DOCUMENT

Patent Document 1: JP 2016-038425 A

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

However, the configuration of Patent Document 1 requires six MOSFETs and two capacitors as elements for constituting this one pixel circuit. The design has a large number of elements, which makes high definition layout difficult.

An object of the present technology is to provide an electro-optical device, an electronic device and a driving method which can achieve an increase in the speed of a compensating operation for compensating for variations in a threshold voltage of a transistor used for adjusting a light emission intensity with a smaller number of elements .

SOLUTIONS TO THE PROBLEMS

The present technology is an electro-optic device that includes: a signal line; a relay line; a scan line; a power supply line that supplies power for cancellation; a transfer capacitor connected between the signal line and the relay line; a pixel circuit provided in connection with the relay line and the scanning line; and a drive circuit that drives the pixel circuit in the
the pixel circuit has a drive transistor having a gate electrode, a first power connection and a second power connection, a light-emitting element that emits light with a luminance according to a magnitude of a current supplied via the drive transistor, a first transistor connected between the relay line and the gate electrode of the drive transistor is connected, a second transistor which conducts the first current connection of the drive transistor and the gate electrode of the drive transistor, a third transistor which is connected between the first current connection and a Terminal of the light emitting element is inserted, and a fourth transistor inserted between the power supply line and the one terminal of the light emitting element, and
the drive circuit turns on the first transistor, the second transistor and the fourth transistor in a light emitting period of the light emitting element to change to an erasing period, and the power for erasing through the first transistor, the second transistor, the third transistor and the fourth transistor in the gate electrode of the drive transistor writes, and corrects a threshold voltage of the drive transistor by switching off the third transistor and drives a voltage of the gate electrode of the drive transistor so that the voltage reflects the threshold voltage.

In addition, the present technology is an electronic device incorporating the above-described electro-optical device.

In addition, the present technology is a method of driving an electro-optical device including: a signal line; a relay line; a scan line; a power supply line that supplies power for cancellation; a first capacitor connected between the signal line and the relay line; a pixel circuit provided corresponding to the relay line and the scanning line; and a drive circuit that drives the pixel circuit,
wherein the pixel circuit includes: a drive transistor having a gate electrode, a first power connection and a second power connection; a light emitting element that emits light having a luminance according to an amount of a current supplied through the drive transistor; a first transistor connected between the relay line and the gate electrode of the drive transistor; a second transistor which conducts the first current connection of the drive transistor and the gate electrode of the drive transistor; a third transistor inserted between the first power terminal and one terminal of the light emitting element; and a fourth transistor inserted between the power supply line and the one terminal of the light emitting element,
wherein the method performed by the drive circuit includes: turning on the first transistor, the second transistor and the fourth transistor in a light emitting period of the light emitting element to change to an erasing period, and writing the power for erasing through the first transistor, the second transistor , the third transistor and the fourth transistor in the gate electrode of the drive transistor; and correcting a threshold voltage of the drive transistor by turning off the third transistor and driving the gate electrode of the drive transistor with a voltage so that the voltage reflects the threshold voltage.

EFFECTS OF THE INVENTION

According to at least one embodiment, a pixel circuit capable of threshold correction can be achieved with a smaller number of elements. It should be noted that the effects described herein are not necessarily limiting and that any or various effects described in the present technology can be obtained. Furthermore, the content of the present technology should not be interpreted as being limited by the exemplary effects in the following description.

Figure list

• 1 Figure 13 is a connection diagram of one embodiment of a pixel circuit in accordance with the present technology.
• 2 FIG. 13 is a timing diagram for describing the embodiment of FIG 1 .
• 3 Fig. 13 is a connection diagram of an example of a conventional pixel circuit.
• 4th Fig. 10 is a timing chart for describing the conventional pixel circuit.

MODE FOR CARRYING OUT THE INVENTION

The embodiments described below are specific examples suitable for the present technology, and various technically preferred limitations are given. However, the scope of the present technology is not limited to the embodiments unless a statement that restricts the present technology is made in the following description.

1. <1. Herkömmliche Ausgestaltung>
2. <2. Eine Ausführungsform der vorliegenden Technologie>
3. <3. Modifikation>
4. <4. Anwendungsbeispiel>

It should be noted that the present technology is described in the following order.

1. <1. Conventional design>
2. <2. An embodiment of the present technology>
3. <3. Modification>
4. <4. Application example>

<Conventional design>

Before describing an embodiment of the present technology, a conventional configuration described in Patent Document 1 will be described. 3 illustrated a conventional pixel circuit, and 4th Fig. 13 is a timing chart showing an operation of the conventional pixel circuit. Although not shown, an electro-optical device includes a display panel and a control circuit that controls an operation of the display panel. The display panel includes a plurality of pixel circuits and a drive circuit which drives the pixel circuits. The plurality of pixel circuits and the drive circuit included in the display panel are formed on a silicon substrate, and an OLED as an example of a light emitting element is used for the pixel circuit.

The control circuit is supplied with digital image data in synchronism with a synchronization signal. The image data is data in which a gradation level of a pixel of an image to be displayed on the display panel is indicated in eight bits, for example. In addition, the synchronization signal is a signal including a vertical synchronization signal, a horizontal synchronization signal and a dot clock signal. The control circuit generates various control signals based on the synchronization signal and supplies the generated control signals to the display panel. In addition, the control circuit includes a voltage generating circuit. The voltage generating circuit supplies various potentials to the display panel. Furthermore, the control circuit generates an analog image signal based on the image data.

The display field contains a display unit and the control circuit that controls the display unit. In the display unit, pixel circuits corresponding to pixels of an image to be displayed are arranged in a matrix. That is, in the display unit, scan lines of M rows extending in the horizontal direction (X direction) in the figure and, in addition, signal lines of (3N) columns grouped for each of the three columns in the figure extend in the vertical direction (Y direction) and are provided so as to be insulated from the respective scan lines. The pixel circuits are arranged in a matrix of vertical M rows x horizontal (3N) columns.

Each pixel circuit has the same configuration. A pixel circuit 11 is made with reference to 3 described. One electrode of a transfer capacitor (first capacitor) Cs2 and a source or a drain of a fifth transistor AZ3 are with a signal line 12-1 connected. In addition, the other electrode is the transfer capacitor Cs2 and the other of the source and drain of the fifth transistor AZ3 with a relay line 12-2 connected. That is, the transfer capacitor Cs2 and the fifth transistor AZ3 parallel to each other between the signal line 12-1 and the relay line 12-2 are switched.

In addition, there is the pixel circuit 11 with the relay line 12-2 connected. That is, the pixel circuit 11 is over the signal line 12-1 and the relay line 12-2 a gradation potential is supplied according to a designated gradation.

Each of the pixel capacitor Cs1 and the transfer capacitor Cs2 contains two electrodes. A gate of a first transistor WS is with a scan line 16 connected, and a source or a drain of the first transistor WS is with the relay line 12-2 connected. In addition, the other is the source and drain of the first transistor WS each with a gate of a control transistor Drv and an electrode of the pixel capacitor Cs1 connected. That is, the first transistor WS is between the gate of the drive transistor Drv and a second electrode of the transfer capacitor Cs2 switched. Then the first transistor acts WS as a transistor providing the coupling between the gate of the driving transistor Drv and the second electrode of the transfer capacitor Cs2 controls that with the relay line 12-2 connected is.

A source of the drive transistor Drv (second power connection) is with a power supply line 15th connected, and a drain of the drive transistor Drv (first power connection) is to a source or a drain of a second transistor AZ2 and a source of a third transistor DS connected. A potential VCCP that is on a high side of a power supply in the pixel circuit 11 is located, the power supply line 15th fed. A current according to a gate-source voltage of the drive transistor Drv flows.

The second transistor AZ2 acts as a switching transistor that provides the coupling between the gate and drain of the drive transistor Drv controls. The second transistor AZ2 is a transistor for conducting between the gate and drain of the drive transistor Drv about the first transistor WS .

The third transistor DS acts as a switching transistor that provides the coupling between the drain of the drive transistor Drv and an anode of an OLED. A gate of a fourth transistor AZ1 is connected to a control line, and a control signal is supplied to the gate. In addition, there is a drain of the fourth transistor AZ1 with the power supply line 13th which serves as a line for supplying power for erasure, and is at an erase potential Vss held. The extinguishing potential Vss is a voltage to keep the OLED in an erased state. The fourth transistor AZ1 acts as a switching transistor, the coupling between the power supply line 13th and the anode of the OLED controls.

A control signal is applied to a gate of the fifth transistor AZ3 fed. In addition, is the source or drain of the fifth transistor AZ3 with the relay line 12-2 and over the relay line 12-2 with the second electrode of the transfer capacitor Cs2 and the other of the source and drain of the second transistor AZ2 connected. In addition, the other is the source and drain of the fifth transistor AZ3 with the signal line 12-1 connected. The fifth transistor AZ3 acts mainly as a switching transistor that provides the coupling between the signal line 12-1 and the relay line 12-2 controls.

One electrode of the pixel capacitor Cs1 is to the gate of the drive transistor Drv connected, and the other electrode of the pixel capacitor Cs1 is with the power supply line 15th (Potential VCCP ) connected. The pixel capacitor Cs1 acts as a holding capacitor that has a gate-source voltage of the drive transistor Drv holds. Note that as the pixel capacitor Cs1 a capacitor can be used to connect to the gate of the drive transistor Drv is parasitic, or a capacitor formed by sandwiching an insulating layer between mutually different conductive layers on the silicon substrate can be used.

The anode of the OLED is a pixel electrode that is separate for each pixel circuit 11 is provided. In contrast, a cathode of the OLED is a common electrode that is the same for all pixel circuits 11 is provided, and holds a potential Vcath that is on a low side of the power supply in the pixel circuit 11 lies. The OLED is an element in which a white organic EL layer is arranged between the anode and the translucent cathode on the silicon substrate. In addition, a color filter corresponding to one of RGB overlaps an emission side (cathode side) of the OLED.

In such an OLED, when a current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode are recombined in an organic EL layer, and thereby excitons are generated and white light is generated. The white light generated at this point in time passes the cathode on a side opposite the silicon substrate (anode) and is visually recognized by an observer after it has been colored by the color filter.

An overview of the operation of the conventional pixel circuit will be given with reference to the drive timing diagram of FIG 4th described. A horizontal scanning period is divided into a light emitting period, an erasing period, an initializing period, a Vth correction period, and a signal writing period. In terms of time, one cycle of the light emission period → the erase period → the initialization period → the Vth correction period → the signal writing period → the light emission period is repeated. 4th illustrates on / off states of the transistors that make up the pixel circuit 11 create. A high level indicates the off-state of the transistor and a low level indicates the on-state of the transistor. In addition, the gate represents a gate potential of the drive transistor Drv .

In the light emission period is the third transistor DS turned on and the transistors WS , AZ2 , AZ1 and AZ3 are turned off. As a result, the drive transistor leads Drv the OLED is supplied with a voltage that is generated by the pixel capacitor Cs1 is held, that is, a drive current according to a gate-source voltage. A current according to a gradation potential according to a certain gradation of each pixel is supplied to the OLED through the driving transistor Drv is supplied, and the OLED emits light with a luminance according to the current. Here, a transistor OFS is turned off and a transmission gate 42 is turned off in the light emission period.

From the light emission period, the transistor is DS turned off and the transistor AZ1 turned on and the period shifts to the erase period. As a result, a path of the current supplied to the OLED is blocked, and thereby the OLED enters an erased state.

In the subsequent initialization period, the transistor OFS, the transistor WS and the transistor AZ3 that is with the signal line 12-1 are coupled, turned on, and a Vth correction reference voltage Vofs is put into the signal line 12-1 written to perform an initialization operation. Because the fifth transistor AZ3 is turned on at the same time, the signal line will be 12-1 and the relay line 12-2 coupled, and the second electrode of the transfer capacitor Cs2 is also set to an initial potential. As a result, the transfer capacitor becomes Cs2 initialized.

When the above-described initialization period ends, the Vth correction period begins. The transistors are in the Vth correction period WS , AZ2 and AZ1 turned on and the third transistors DS and AZ3 are turned off. At this point in time, the gate of the drive transistor is Drv about the first transistor WS and the second transistor AZ2 with the drain of the drive transistor Drv connected, and a drain current flows through the drive transistor Drv which charges the gate. That is, the drain and the gate of the Control transistor Drv are with the relay line 12-2 connected. When a threshold voltage of the drive transistor Drv Vth, a potential Vg of the gate of the drive transistor converges Drv against ( VCCP-Vth ) and the Vth correction is complete.

Here, in the Vth correction period, the transistor OFS is on and a transmission gate 14th switched off. At this point the relay line is 12-2 short and thus becomes a time it takes to charge or discharge one with the relay line 12-2 accompanying parasitic capacitor is required is shortened and the Vth correction period is shortened.

Note that since the third transistor DS is off, the drain of the drive transistor Drv is electrically decoupled from the OLED. In addition, the fourth transistor is similar to the initialization period AZ1 turned on, and thereby the anode of the OLED and the power supply line are turned on 13th coupled to each other, and a potential of the anode becomes the erasing potential Vss set.

When the above-described Vth correction period ends, the write period begins. During the write period the transistors are WS and AZ1 in the pixel circuit 11 turned on, whereas the transistors AZ2 , DS and AZ3 are turned off. During the write period, the transistor OFS is switched off and the transmission gate is switched off 14th turned on. Thus, one electrode of the transfer capacitor Cs2 a gradation potential supplied. Then, a signal generated by level shifting the gradation potential becomes the gate of the drive transistor Drv fed and into the pixel capacitor Cs1 written.

Note that since the third transistor DS is off, the drain of the drive transistor Drv is electrically decoupled from the OLED. In addition, the fourth transistor is similar to the initialization period AZ1 turned on, and thereby the anode of the OLED and the power supply line are turned on 13th coupled to each other, and the potential of the anode is set to the extinguishing potential Vss initialized. Then the period shifts to the light emission period described above.

<An embodiment of the present technology>

In the conventional pixel circuit described above 11 the Vth correction operation is performed while the first transistor WS is on. Thus, a voltage for Vth correction does not become only in the pixel capacitor Cs1 written, but also in a parasitic capacitor Cp of the relay line 12-2 . The relay line 12-2 is shared by a plurality of pixels, and a capacitance value changes according to the number of the shared pixels. When the number of shared pixels is decreased, the capacity value is decreased, a Vth correction speed can be increased, and the operation is advantageous for high-speed driving. On the other hand, since the number of transistors and capacitive elements must be eight elements, there is a disadvantage that the number of elements is large and high resolution layout is hindered.

The present technology provides a pixel circuit that reduces the number of elements while maintaining a function of the pixel circuit. 1 Figure 3 is a circuit diagram of one embodiment of the present technology. The embodiment has a configuration in which the fifth transistor AZ3 in the circuit design of 3 away. In addition, a predetermined voltage rst is applied to the signal line via a transistor RST 12-1 created. A control signal is supplied to a gate of the transistor RST.

2 Fig. 10 illustrates a drive timing of the embodiment of the present technology. There is a third transistor in one light emission period DS turned on and the transistors WS , AZ1 and AZ2 are turned off. As a result, a drive transistor leads Drv an OLED to a voltage that is generated by a pixel capacitor Cs1 is held, that is, a drive current according to a gate-source voltage. A current according to a gradation potential according to a certain gradation of each pixel is supplied to the OLED through the driving transistor Drv is supplied, and the OLED emits light with a luminance according to the current. Here, in the light emission period, the transistor RST is off and a transmission gate 42 is off.

In the light emission period are the first transistor WS , the fourth transistor AZ1 , the second transistor AZ2 and the transistor RST is turned on and the period shifts to an erased state. At the same time, an erasure potential is used in preparation for the Vth correction Vss a power supply line 13th about the transistor AZ2 , the transistor DS and the transistor AZ1 written.

This is where the extinguishing potential Vss set to a voltage so that the drive transistor Drv is turned on in preparation for Vth correction while the OLED is being cleared.

Here is when a voltage to turn on of the transistors AZ1 , AZ2 and DS is referred to as V Low and a threshold voltage of the transistors AZ1 , AZ2 and DS Vth (AZ1) = Vth (AZ2) = Vth (DS) = Vth, a gate voltage Vg of the drive transistor Drv expressed by the following equations.

$$\text{When Vss}<\left|\text{Vth}\right|+\text{V}\_\text{Low},\text{Vg}=\left|\text{Vth}\right|+\text{V}\_\text{Low}$$

$$\text{When Vss}\ge \left|\text{Vth}\right|+\text{V}\_\text{Low},\text{Vg}=\text{Vss}$$

After that the third transistor DS turned off to start a Vth correction period. When the third transistor DS is off, is a drain of the drive transistor Drv decoupled from the OLED. The gate of the drive transistor Drv converges to (VCCP-Vth) and the Vth correction period is completed.

After the Vth correction period, the period shifts to a writing period. The first transistor is in the write period WS turned on, the third transistor is DS off, the fourth transistor is AZ1 turned on and the third transistor AZ3 and the transistor RST are turned off. When a Vsig voltage of VCCP transitions to (VCCP-Vsig), a gate voltage transitions to that expressed by the following expression:

$$\text{VCCP}-\text{Vth}-\text{Vdata}\times \text{Cs}2/\left(\text{<figure-callout id="1" label="Cs" filenames="DE112019004175T5\_0004.png,DE112019004175T5\_0007.png" state="{{state}}">Cs</figure-callout>}1+\text{Cs}2\right)$$

Thus, the gate voltage of the drive transistor Drv to a voltage representing Vth, and Vth is canceled at the time of light emission. After that become the first transistor WS and the fourth transistor AZ1 turned off and the third transistor DS is turned on to switch to the light emission period.

As described above, the Vth correcting operation can be performed similarly to the conventional embodiment even if the transistor AZ3 is removed from the conventional six-transistor, two-capacitor configuration to form the five-transistor, two-capacitor configuration by setting a drive timing at which a Vth correction preparation voltage is written from Vss. That is, in the pixel circuit of the present technology, the Vth correction preparation voltage is not written from the signal line in preparation for Vth correction, but a power supply connected to an anode of the OLED serving as a light emitting element via a switching transistor coupled is used. Since the number of elements can be reduced in this way, a pixel circuit advantageous for a high definition pixel layout can be achieved.

<modification>

In the above, a specific description has been given of the embodiments of the present technology. However, the present technology is not limited to any embodiment described above, and various modifications based on a technical idea of the present technology can be made. For example, various modifications as described below are possible. In addition, one or more aspects of the modifications as described below can be optionally selected and combined as appropriate. In addition, the configurations, methods, steps, shapes, materials, numerical values and the like in the above-described embodiments can be combined with one another without departing from the core of the present technology.

In the embodiments described above, the transistors are all P-channel transistors, but may all be N-channel transistors. In addition, P-channel transistors and N-channel transistors can be combined as required.

In the above-described embodiments, an example is described in which an OLED serving as a light-emitting element is used as an electro-optic element, but the electro-optic element may also be an element that emits light having a luminance according to a current such as e.g. an inorganic light-emitting diode or a light-emitting diode (LED).

<Application example>

Next, an electronic device to which an electro-optical device according to the embodiments or the like or the application example is applied will be described. The electro-optic device is suitable for use in high resolution displays with small pixels. Therefore, a display device such as a head-mounted display, smart glasses, a smartphone, or an electronic viewfinder of a digital camera can be used as the electronic device.

Note that the present technology can also have the following configurations.

1. (1) An electro-optic device that includes:
   • a signal line;
   • a relay line;
   • a scan line;
   • a power supply line that supplies power for cancellation;
   • a transfer capacitor connected between the signal line and the relay line;
   • a pixel circuit provided corresponding to the relay line and the scanning line; and
   • a control circuit that controls the pixel circuit,
   wherein the pixel circuit includes:
   • a control transistor with a gate electrode, a first power connection and a second power connection,
   • a light emitting element that emits light having a luminance according to a magnitude of a current supplied through the driving transistor,
   • a first transistor which is connected between the relay line and the gate electrode of the control transistor,
   • a second transistor which conducts the first current connection of the control transistor and the gate electrode of the control transistor,
   • a third transistor inserted between the first power terminal and one terminal of the light emitting element, and
   • a fourth transistor inserted between the power supply line and the one terminal of the light emitting element, and
   • the control circuit
   • turns on the first transistor, the second transistor and the fourth transistor in a light emitting period of the light emitting element to change to an erasing period, and the power for erasing through the first transistor, the second transistor, the third transistor and the fourth transistor into the gate -Electrode of the control transistor writes, and
   • corrects a threshold voltage of the control transistor by switching off the third transistor and controls a voltage of the gate electrode of the control transistor in such a way that the voltage reflects the threshold voltage.
2. (2) The electro-optical device according to (1), in which the power for erasing is set so that the driving transistor is turned on during the erasing period while the light-emitting element is being erased.
3. (3) The electro-optical device according to (1) or (2), further comprising a pixel capacitor having an electrode which is coupled to the gate electrode of the drive transistor, and another electrode which is coupled to a voltage supply line, wherein the pixel capacitor is a Gate-source voltage of the control transistor holds.
4. (4) An electronic device that includes:
   • the electro-optical device according to (1).
5. (5) A method of driving an electro-optical device that includes:
   • a signal line;
   • a relay line;
   • a scan line;
   • a power supply line that supplies power for cancellation;
   • a first capacitor connected between the signal line and the relay line;
   • a pixel circuit provided corresponding to the relay line and the scanning line; and
   • a control circuit that controls the pixel circuit,
   • wherein the pixel circuit includes:
     • a drive transistor having a gate electrode, a first power connection and a second power connection;
     • a light emitting element that emits light having a luminance according to an amount of a current supplied through the drive transistor;
     • a first transistor connected between the relay line and the gate electrode of the drive transistor;
     • a second transistor which conducts the first current connection of the drive transistor and the gate electrode of the drive transistor;
     • a third transistor inserted between the first power terminal and one terminal of the light emitting element; and
     • a fourth transistor inserted between the power supply line and the one terminal of the light emitting element,
   • wherein the method performed by the control circuit includes:
     • Turning on the first transistor, the second transistor and the fourth transistor in a light emitting period of the light emitting element to change to an erasing period, and writing the power for erasing through the first transistor, the second transistor, the third transistor and the fourth transistor to the Gate electrode of the drive transistor; and
     • Correcting a threshold voltage of the drive transistor by switching off the third transistor and driving the gate electrode of the drive transistor with a voltage so that the voltage reflects the threshold voltage.
6. (6) The method of driving the electro-optical device according to (5), wherein the power for erasing is set so that the driving transistor is turned on during the erasing period while the light-emitting element is being erased.
7. (7) The method for driving the electro-optical device according to (5) or (6), in which the pixel circuit further comprises a pixel capacitor having one electrode which is coupled to the gate electrode of the drive transistor, and another electrode which is connected to a voltage supply line is coupled, wherein the pixel capacitor holds a gate-source voltage of the drive transistor, includes.

List of reference symbols

11

Pixel circuit

12-1

Signal line

12-2

Relay line

13, 15

Power supply line

14th

Transmission gate

16

Scan line

VCCP

Power supply line

Drv, WS, AZ2, DS, AZ1, AZ3

transistor

Cs1

Pixel capacitor

Cs2

Transfer capacitor

Vss

Extinguishing potential

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• JP 2016038425 A [0006]

Claims (7)

An electro-optical device comprising: a signal line; a relay line; a scan line; a power supply line that supplies power for cancellation; a transfer capacitor connected between the signal line and the relay line; a pixel circuit provided corresponding to the relay line and the scanning line; and a drive circuit which drives the pixel circuit, wherein the pixel circuit includes: a control transistor with a gate electrode, a first power connection and a second power connection, a light emitting element that emits light having a luminance according to a magnitude of a current supplied through the driving transistor, a first transistor which is connected between the relay line and the gate electrode of the control transistor, a second transistor which conducts the first current connection of the control transistor and the gate electrode of the control transistor, a third transistor inserted between the first power terminal and one terminal of the light emitting element, and a fourth transistor inserted between the power supply line and the one terminal of the light emitting element, and the control circuit turns on the first transistor, the second transistor and the fourth transistor in a light emitting period of the light emitting element to change to an erasing period, and the power for erasing through the first transistor, the second transistor, the third transistor and the fourth transistor into the gate -Electrode of the control transistor writes, and corrects a threshold voltage of the control transistor by switching off the third transistor and controls a voltage of the gate electrode of the control transistor in such a way that the voltage reflects the threshold voltage. Electro-optical device according to Claim 1 wherein the power for erasing is set so that the drive transistor is turned on during the erasing period while the light emitting element is being erased. Electro-optical device according to Claim 1 , further comprising a pixel capacitor having one electrode coupled to the gate electrode of the drive transistor and another electrode coupled to a voltage supply line, the pixel capacitor holding a gate-source voltage of the drive transistor. Electronic device comprising the electro-optical device according to Claim 1 . A method of driving an electro-optic device that includes: a signal line; a relay line; a scan line; a power supply line that supplies power for cancellation; a first capacitor connected between the signal line and the relay line; a pixel circuit provided corresponding to the relay line and the scanning line; and a control circuit that controls the pixel circuit, wherein the pixel circuit includes: a drive transistor having a gate electrode, a first power connection and a second power connection; a light emitting element that emits light having a luminance according to an amount of a current supplied through the drive transistor; a first transistor connected between the relay line and the gate electrode of the drive transistor; a second transistor which conducts the first current connection of the drive transistor and the gate electrode of the drive transistor; a third transistor inserted between the first power terminal and one terminal of the light emitting element; and a fourth transistor inserted between the power supply line and the one terminal of the light emitting element, wherein the method carried out by the control circuit comprises the following: Turning on the first transistor, the second transistor and the fourth transistor in a light emitting period of the light emitting element to change to an erasing period, and writing the power for erasing through the first transistor, the second transistor, the third transistor and the fourth transistor into the Gate electrode of the drive transistor; and Correcting a threshold voltage of the drive transistor by switching off the third transistor and driving the gate electrode of the drive transistor with a voltage so that the voltage reflects the threshold voltage. Method for controlling the electro-optical device according to Claim 5 wherein the power for erasing is set so that the drive transistor is turned on during the erasing period while the light emitting element is being erased. Method for controlling the electro-optical device according to Claim 5 wherein the pixel circuit further includes a pixel capacitor having one electrode coupled to the gate electrode of the drive transistor and another electrode coupled to a voltage supply line, the pixel capacitor holding a gate-source voltage of the drive transistor.

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