DE112018004220T5 - Speicherzugriffs-Vermittlersystem mit anwendungsgesteuerter Unterstützung für frühzeitige Schreibbestätigung - Google Patents

Speicherzugriffs-Vermittlersystem mit anwendungsgesteuerter Unterstützung für frühzeitige Schreibbestätigung Download PDF

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Publication number
DE112018004220T5
DE112018004220T5 DE112018004220.0T DE112018004220T DE112018004220T5 DE 112018004220 T5 DE112018004220 T5 DE 112018004220T5 DE 112018004220 T DE112018004220 T DE 112018004220T DE 112018004220 T5 DE112018004220 T5 DE 112018004220T5
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Germany
Prior art keywords
ewack
memory
memory access
write request
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE112018004220.0T
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German (de)
English (en)
Inventor
Dimitrios SYRIVELIS
Andrea REALE
Kostas KATRINIS
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
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International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE112018004220T5 publication Critical patent/DE112018004220T5/de
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Hardware Redundancy (AREA)
  • Memory System (AREA)
  • Debugging And Monitoring (AREA)
DE112018004220.0T 2017-10-13 2018-10-10 Speicherzugriffs-Vermittlersystem mit anwendungsgesteuerter Unterstützung für frühzeitige Schreibbestätigung Pending DE112018004220T5 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/783,069 2017-10-13
US15/783,069 US10423563B2 (en) 2017-10-13 2017-10-13 Memory access broker system with application-controlled early write acknowledgment support and identification of failed early write acknowledgment requests to guarantee in-order execution of memory requests of applications
PCT/IB2018/057834 WO2019073394A1 (en) 2017-10-13 2018-10-10 MEMORY ACCESS BROKER SYSTEM WITH APPLICATION-EARLY WRITTEN RECEIVING RECEIPT SUPPORT

Publications (1)

Publication Number Publication Date
DE112018004220T5 true DE112018004220T5 (de) 2020-05-07

Family

ID=66096466

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112018004220.0T Pending DE112018004220T5 (de) 2017-10-13 2018-10-10 Speicherzugriffs-Vermittlersystem mit anwendungsgesteuerter Unterstützung für frühzeitige Schreibbestätigung

Country Status (6)

Country Link
US (1) US10423563B2 (https=)
JP (1) JP7100941B2 (https=)
CN (1) CN111201521B (https=)
DE (1) DE112018004220T5 (https=)
GB (1) GB2580275B (https=)
WO (1) WO2019073394A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11855831B1 (en) 2022-06-10 2023-12-26 T-Mobile Usa, Inc. Enabling an operator to resolve an issue associated with a 5G wireless telecommunication network using AR glasses
US12314626B2 (en) 2022-06-17 2025-05-27 T-Mobile Usa, Inc. Enable interaction between a user and an agent of a 5G wireless telecommunication network using augmented reality glasses

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US10911308B2 (en) * 2017-09-18 2021-02-02 Rapyuta Robotics Co., Ltd. Auto-determining and installing missing components to a to-be-managed device by a single execution of unique device setup command
US11025445B2 (en) * 2018-06-08 2021-06-01 Fungible, Inc. Early acknowledgment for write operations
US10802974B2 (en) 2018-10-15 2020-10-13 Texas Instruments Incorporated Virtual network pre-arbitration for deadlock avoidance and enhanced performance
US11921637B2 (en) * 2019-05-24 2024-03-05 Texas Instruments Incorporated Write streaming with cache write acknowledgment in a processor
US11354455B2 (en) 2019-09-11 2022-06-07 International Business Machines Corporation Maintenance of access for security enablement on a host system
US11308243B2 (en) 2019-09-11 2022-04-19 International Business Machines Corporation Maintenance of access for security enablement in a storage device
US11410417B2 (en) * 2020-08-17 2022-08-09 Google Llc Modular system for automatic hard disk processing and verification

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US5537555A (en) 1993-03-22 1996-07-16 Compaq Computer Corporation Fully pipelined and highly concurrent memory controller
US6279065B1 (en) 1998-06-03 2001-08-21 Compaq Computer Corporation Computer system with improved memory access
JP2001216259A (ja) * 2000-02-04 2001-08-10 Hitachi Ltd マルチプロセッサシステム及びそのトランザックション制御方法
JP3904869B2 (ja) * 2001-09-26 2007-04-11 株式会社東芝 学習支援装置および学習支援方法
US7111153B2 (en) * 2003-09-30 2006-09-19 Intel Corporation Early data return indication mechanism
US20100306442A1 (en) * 2009-06-02 2010-12-02 International Business Machines Corporation Detecting lost and out of order posted write packets in a peripheral component interconnect (pci) express network
US9189441B2 (en) * 2012-10-19 2015-11-17 Intel Corporation Dual casting PCIE inbound writes to memory and peer devices
US10073626B2 (en) * 2013-03-15 2018-09-11 Virident Systems, Llc Managing the write performance of an asymmetric memory system
US9235521B2 (en) 2013-07-22 2016-01-12 Avago Technologies General Ip (Singapore) Pte Ltd Cache system for managing various cache line conditions
US20150261677A1 (en) 2014-03-12 2015-09-17 Silicon Graphics International Corp. Apparatus and Method of Resolving Protocol Conflicts in an Unordered Network
US11392517B2 (en) 2014-09-10 2022-07-19 Sony Group Corporation Access control method, bus system, and semiconductor device
GB2533808B (en) * 2014-12-31 2021-08-11 Advanced Risc Mach Ltd An apparatus and method for issuing access requests to a memory controller
US10037220B2 (en) 2015-11-20 2018-07-31 International Business Machines Corporation Facilitating software-defined networking communications in a container-based networked computing environment

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11855831B1 (en) 2022-06-10 2023-12-26 T-Mobile Usa, Inc. Enabling an operator to resolve an issue associated with a 5G wireless telecommunication network using AR glasses
US12463859B2 (en) 2022-06-10 2025-11-04 T-Mobile Usa, Inc. Enabling an operator to resolve an issue associated with a 5G wireless telecommunication network using AR glasses
US12314626B2 (en) 2022-06-17 2025-05-27 T-Mobile Usa, Inc. Enable interaction between a user and an agent of a 5G wireless telecommunication network using augmented reality glasses

Also Published As

Publication number Publication date
JP7100941B2 (ja) 2022-07-14
US20190114284A1 (en) 2019-04-18
WO2019073394A1 (en) 2019-04-18
JP2020537227A (ja) 2020-12-17
US10423563B2 (en) 2019-09-24
CN111201521A (zh) 2020-05-26
GB2580275A (en) 2020-07-15
GB202006359D0 (en) 2020-06-17
GB2580275B (en) 2021-03-03
CN111201521B (zh) 2023-09-15

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