DE112014006733B4 - Semiconductor device, power module, power converter, and semiconductor device manufacturing method - Google Patents

Abstract

A semiconductor device (1) comprising: a semiconductor substrate (10) of a first conductivity type having a first main plane (10a) and a second main plane (10b) on the opposite side of the first main plane (10a); a semiconductor layer (12) of the first conductivity type formed over the first main plane (10a) of the semiconductor substrate (10); a first semiconductor region (13) formed in an upper layer of the semiconductor layer (12), the first semiconductor region (13) having a second conductivity type which is different from the first conductivity type; a second semiconductor region (14) of the first conductivity type, which is formed in an upper layer of the first semiconductor region (13); a third semiconductor region (15) of the second conductivity type, which is formed in the upper layer of the first semiconductor region (13 ); a gate electrode (19) disposed over a top surface of a portion of the first Ha semiconductor region (13) is formed, which is sandwiched between the second semiconductor region (14) and the semiconductor layer (12) with a gate insulating film (18) interposed therebetween; a source electrode (21) which is located over the second semiconductor region ( 14) and is formed over the third semiconductor region (15); a drain electrode (22) formed over the second major plane (10b) of the semiconductor substrate (10); anda fourth semiconductor region (24) of the first conductivity type formed in a portion of the semiconductor layer (12) underlying the first semiconductor region (13); wherein the semiconductor substrate (10), the semiconductor layer (12), the first semiconductor region (13 ), the second semiconductor region (14), the third semiconductor region (15) and the fourth semiconductor region (24) consist of silicon carbide; wherein the semiconductor layer (12) comprises a first semiconductor section (16) consisting of an upper layer of the semiconductor layer adjacent to the first Semiconductor region (13) is formed, wherein the fourth semiconductor region (24) is doped with elements for forming crystal defects; and wherein either said first semiconductor section (16) is doped with the elements for forming crystal defects in such a manner that the concentration of the elements for forming crystal defects in the first semiconductor section (16) is lower than the concentration of the elements for forming crystal defects in the fourth The semiconductor region (24) or the first semiconductor portion (16) is not doped with the elements for forming crystal defects, characterized in that the fourth semiconductor region (24) is in contact with a lower surface of the first semiconductor region (13).

Description

Technical area

The present invention relates to a semiconductor device, a power module and a power converter. In particular, the present invention relates to a semiconductor device, a power module and a power converter each having a switching element.

State of the art

Inverter devices have been used as power converters for high power applications that require converting the power to power loads such as high power loads. B. to drive motors, include between direct current and alternating current. The inverter device, which acts as a power converter for such high-power applications, has a power module which serves as an inverter circuit. The power module functioning as an inverter circuit has a plurality of switching elements each functioning as a semiconductor device.

The breakdown field of semiconductors with a wide band gap such as B. Silicon carbide (SiC) is about 10 times that of silicon (Si). The withstand voltage of vertical metal-insulator-semiconductor field effect transistors (MISFET), which act as switching elements, each made of SiC, is extensively in the range of several hundred voltages (V) to several kilovolts (kV). This has prompted the development of power converters suitable for the high power applications mentioned above, each power converter having a power module comprising vertical MISFETs made of SiC.

The Japanese patent application JP 2011-109018 A (Patent Literature 1) discloses a technology regarding a semiconductor element having semiconductor layers made of silicon carbide. The semiconductor element described in Patent Literature 1 comprises a substrate made of a silicon carbide semiconductor and a buffer layer of a first conductivity type formed over the substrate and made of the silicon carbide semiconductor. The semiconductor element described in Patent Literature 1 further comprises a first conductivity type drift layer formed over the buffer layer and made of the silicon carbide semiconductor, and a second conductivity type semiconductor layer formed over the drift layer and made of silicon carbide. In addition, Patent Literature 2 discloses a semiconductor device having a wide band gap semiconductor.

The below-mentioned Non-Patent Literature 1 describes the deterioration of a property called “forward voltage deterioration” which is specific to semiconductor elements having semiconductor layers made of silicon carbide.

Citation list

Patent literature

Patent Literature 1: JP 2011-109018 A Patent literature 2: JP 2014-017326 A

Non-patent literature

Non-patent literature 1: K. Konishi et al., “Stacking fault expansion from basal plane dislocations converted into threading edge dislocations in 4H-SiC epilayers under high current stress”, Journal of Applied Physics, 114, p. 014504 (2013).

Summary of the invention

Technical problem

The aforementioned power module, which functions as an inverter circuit having a plurality of switching elements, may have a high inductance load connected to the output terminal of the power module. If so, when each of the plurality of switching elements is switched from the on-state to the off-state, a current flows through the inverter circuit in a direction opposite to that of the on-state current of the switching element. The inverter circuit must consequently have a so-called “freewheeling diode” which is connected in parallel so that the forward current flows through the diode under the off-state condition.

Meanwhile, the vertical MISFET includes a body diode between its source and drain electrodes, the body diode acting as a free wheeling diode and being able to let the forward current flow under the off-state condition. It follows that the power module with vertical MISFETs as its switching elements has no need to have additional freewheeling diodes mounted in a manner outside of these MISFETs.

However, if the vertical MISFETs included in the power module that acts as the inverter circuit are made of SiC, the forward current flowing through the body diodes within the vertical MISFETs may suffer the aforementioned forward voltage degradation, which increases the on-resistance of the MISFETs leads. The forward voltage degradation increases when it occurs Power loss of the power module that acts as an inverter circuit.

An object of the present invention is to provide a semiconductor device that prevents or inhibits the forward voltage deterioration from occurring when a forward current flows through the body diodes of vertical MISFETs made of SiC in the semiconductor device. Another object of the present invention is to provide a power module including such semiconductor devices capable of reducing the power loss attributable to forward voltage degradation and a power converter including such a power module.

The above and other objects and advantages of the present invention will become apparent upon reading the following description and the accompanying drawings.

Solution to the problem

Typical embodiments of the present invention disclosed below are briefly outlined below.

According to a typical embodiment of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate of a first conductivity type having a first main plane and a second main plane on the opposite side of the first main plane; a semiconductor layer of the first conductivity type formed over the first major plane of the semiconductor substrate; and a first semiconductor region formed in an upper layer of the semiconductor layer, the first semiconductor region having a second conductivity type different from the first conductivity type. The semiconductor device also includes: a second semiconductor region of the first conductivity type formed in an upper layer of the first semiconductor region; a third semiconductor region of the second conductivity type formed in the upper layer of the first semiconductor region; and a gate electrode formed over the top surface of a portion of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor layer with a gate insulating film interposed therebetween. The semiconductor device further includes: a source electrode formed over the second semiconductor region and over the third semiconductor region; a drain electrode formed over the second major plane of the semiconductor substrate; and a fourth semiconductor region of the first conductivity type formed in a portion of the semiconductor layer underlying the first semiconductor region. The semiconductor substrate, the semiconductor layer, the first semiconductor region, the second semiconductor region, the third semiconductor region and the fourth semiconductor region consist of silicon carbide. The semiconductor layer comprises a first semiconductor section composed of an upper Layer of the semiconductor layer is formed adjacent to the first semiconductor region. The fourth semiconductor region is doped with inert elements. Either the first semiconductor section is doped with the inert elements in such a way that the concentration of the inert elements in the first semiconductor section is lower than the concentration of the inert elements in the fourth semiconductor region, or the first semiconductor section is not doped with the inert elements, the fourth semiconductor region is in contact with a lower surface of the first semiconductor region.

According to another typical embodiment of the present invention, there is provided a semiconductor device manufacturing method comprising: a step of forming a semiconductor layer of a first conductivity type over a first main plane of a semiconductor substrate of the first conductivity type having the first main plane and a second main plane on the opposite side of the having first main level; and a step of forming a first semiconductor region in an upper layer of the semiconductor layer, the first semiconductor region having a second conductivity type different from the first conductivity type. The semiconductor device manufacturing method also includes: a step of forming a second semiconductor region of the first conductivity type in an upper layer of the first semiconductor region; a step of forming a third semiconductor region of the second conductivity type in the upper layer of the first semiconductor region; and a step of forming a gate electrode over the upper surface of a portion of the first semiconductor region sandwiched between the second semiconductor region and the semiconductor layer with a gate insulating film sandwiched therebetween. The semiconductor device manufacturing method further includes: a step of forming a source electrode over the second semiconductor region and over the third semiconductor region; and a step of forming a drain electrode over the second major plane of the semiconductor substrate. The step of forming the first semiconductor region forms a fourth semiconductor region of the first conductivity type in a portion of the semiconductor layer that lies under the first semiconductor region, the fourth semiconductor region being doped with inert elements. The semiconductor substrate, the semiconductor layer, the first semiconductor region, the second semiconductor region, the third semiconductor region and the fourth semiconductor region consist of silicon carbide. Either a first semiconductor section, which is formed from an upper layer of the semiconductor layer adjacent to the first semiconductor region, is doped with the inert elements in such a way that the concentration of the inert elements in the first semiconductor section is lower than the concentration of the inert elements in the fourth semiconductor region , or the first semiconductor section is not doped with the inert elements, the fourth semiconductor region being in contact with a lower surface of the first semiconductor region.

Advantageous Effects of the Invention

The beneficial effects provided by the typical embodiments of the present invention are briefly outlined below.

The semiconductor device as a typical embodiment of the present invention prevents or inhibits forward voltage degradation from occurring when forward current flows through the body diodes of vertical MISFETs made of SiC in the semiconductor device.

Figure list

• 1 Fig. 13 is a plan view of a semiconductor device as a first embodiment of the present invention.
• 2 Fig. 13 is a set of main part sectional views of the semiconductor device as the first embodiment.
• 3 Fig. 13 is a flow chart showing part of a manufacturing process for the semiconductor device as the first embodiment.
• 4th Fig. 13 is another flow chart showing part of the manufacturing process for the semiconductor device as the first embodiment.
• 5 Fig. 13 is a set of main part sectional views of the semiconductor device as the first embodiment which is in the manufacturing process.
• 6th Fig. 13 is another set of main part sectional views of the semiconductor device as the first embodiment which is in the manufacturing process.
• 7th Fig. 13 is another set of main part sectional views of the semiconductor device as the first embodiment which is in the manufacturing process.
• 8th Fig. 13 is another set of main part sectional views of the semiconductor device as the first embodiment which is in the manufacturing process.
• 9 Fig. 13 is another set of main part sectional views of the semiconductor device as the first embodiment which is in the manufacturing process.
• 10 Fig. 13 is another set of main part sectional views of the semiconductor device as the first embodiment which is in the manufacturing process.
• 11 Fig. 13 is another set of main part sectional views of the semiconductor device as the first embodiment which is in the manufacturing process.
• 12th Fig. 13 is another set of main part sectional views of the semiconductor device as the first embodiment which is in the manufacturing process.
• 13th Fig. 13 is another set of main part sectional views of the semiconductor device as the first embodiment which is in the manufacturing process.
• 14th Fig. 13 is another set of main part sectional views of the semiconductor device as the first embodiment which is in the manufacturing process.
• 15th Fig. 13 is another set of main part sectional views of the semiconductor device as the first embodiment which is in the manufacturing process.
• 16 Fig. 13 is a schematic view showing a structure of an engine system using the first embodiment.
• 17th Fig. 13 is a set of main part sectional views of a semiconductor device as a comparative example.
• 18th Fig. 13 is a set of main part sectional views of a semiconductor device as a second embodiment of the present invention.
• 19th Fig. 13 is a flow chart showing part of a manufacturing process for the semiconductor device as a second embodiment.
• 20th Fig. 13 is a set of main part sectional views of the semiconductor device as a second embodiment which is in the manufacturing process.
• 21 Fig. 13 is another set of main part sectional views of the semiconductor device as a second embodiment which is in the manufacturing process.
• 22nd Fig. 13 is another set of main part sectional views of the semiconductor device as a second embodiment which is in the manufacturing process.
• 23 Fig. 13 is a schematic view showing a structure of a three-phase motor system as a third embodiment of the present invention.
• 24 Fig. 13 is a schematic view showing a structure of an electric vehicle as a fourth embodiment of the present invention.
• 25th Fig. 13 is a circuit diagram of a boost converter for use in the vehicle of the fourth embodiment.
• 26th Fig. 13 is a schematic view showing a structure of a railroad vehicle as a fifth embodiment of the present invention.

Description of the embodiments

In the following description of each preferred embodiment of the present invention, the embodiment may be explained in several sections or examples as necessary. These sections or examples are not without reference to one another, but are variable, explanatory or complementary to one another, unless otherwise stated.

In the description of each preferred embodiment below, references to the numerical aspects of the constituent elements making up the embodiment (including sizes, values, amounts and ranges) are meant to be exemplary only and are not intended to limit the embodiment unless otherwise specified or unless the numbers are obviously theoretical are determined.

In the description that follows of each preferred embodiment, the compositional elements (including steps) making up the embodiment are obviously not indispensable unless otherwise specified or unless clearly theoretically deemed indispensable.

In the following description of each preferred embodiment as well, references to the shapes or positional relationships of the composing elements include shapes, configurations or positional relationships approximated or similar to the elements indicated, unless otherwise indicated or unless what is indicated, obviously everything else theoretically excludes. This also applies to the values and ranges of the elements mentioned above.

Some preferred embodiments of the present invention will now be described in detail below with reference to the accompanying drawings. Throughout the accompanying drawings, like reference numerals designate like elements or components with like functions. In the description that follows, the explanations of the same or corresponding parts or paragraphs are not repeated unless specifically required.

In the sectional views illustrating the preferred embodiments, some of the usual hatching may be omitted for ease of viewing. In the plan views illustrating the embodiments, some hatching may be added to them for easy observation.

In the following description of the preferred embodiments, the term "A-B" means that the range is from A to B, inclusive.

First embodiment

<Semiconductor device>

A semiconductor device as a first embodiment of the present invention will be described below. This semiconductor device as the first embodiment includes vertical MISFETs each made of silicon carbide (SiC).

1 Fig. 13 is a plan view of a semiconductor device as a first embodiment of the present invention. 2 Fig. 13 is a set of main part sectional views of the semiconductor device 1 as a first embodiment. 2 indicates two cross sections: one that is in an active area AR1 and on the line AA in 1 is taken, and another one that is in a graduation area AR2 and on the line BB in 1 is taken. Shows for easy understanding 1 a semiconductor device such as through a gate insulating film 18th , a gate electrode 19th , an interlayer insulating film 20th , a source electrode 21 and a contact electrode 21a seen, all of which are taken as removed.

As in 1 and 2 shown, the semiconductor device 1 of the first embodiment has an n ⁺ -type SiC substrate 10 serving as a semiconductor substrate.

The SiC substrate 10 of the n ⁺ -type is a semiconductor substrate of the n-type, which consists of silicon carbide (SiC), which with impurities of the n-type such. B. nitrogen (N) or phosphorus (P) is doped. That is, the n ⁺ -type SiC substrate 10 serving as a semiconductor substrate has the n-conductivity type. The concentration of the n-type impurity in the n ⁺ -type SiC substrate 10 is relatively high, for example from about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ^-3 . ^{The n +} -type SiC substrate 10 has a thickness of, for example, about 50 to 500 μm.

^{The n +} type SiC substrate 10 has an upper surface 10a as a main plane and a lower surface 10b than other main level on. ^{The n +} -type SiC substrate 10 has the active region AR1 as a section of the upper surface 10a and the graduation area AR2 as the outer peripheral area of the active area AR1 surrounds in a plan view. A body area 13a p-type and a contact area 15a are in the graduation area AR2 arranged.

In this specification, the term “in a plan view” means that the n ⁺ -type SiC substrate 10 is in one to its upper surface 10a perpendicular direction is viewed.

In the in 1 The example shown is the active area AR1 on the middle side of the top surface 10a of the n ⁺ -type SiC substrate 10. In the active area AR1 are multiple cells CL1 each consisting of a vertical MISFET are formed over the n ⁺ -type SiC substrate 10. In the plan view, these cells are arranged, for example, in a matrix pattern. The graduation area AR2 is on the outer peripheral side of the top surface 10a of the n ⁺ -type SiC substrate 10 arranged in a manner so that it is the active region AR1 surrounds. In a section of the graduation area AR2 who is on the side of the active area AR1 is arranged in the plan view, is the contact area 15a above the top surface 10a of the n ⁺ -type SiC substrate 10. In a section of the graduation area AR2 , the one on the opposite side of the active area AR1 is arranged in the plan view, is the body area 13a p-type over the top surface 10a of the n ⁺ -type SiC substrate 10.

As in 1 and 2 shown, the semiconductor device 1 in the active area AR1 ^{the n +} type SiC substrate 10, a buffer layer 11 , an epitaxial layer 12th of the n ^- type, a body area 13th p-type, a source region 14th of the n ⁺ type and a body contact area 15th of the p ⁺ type. The semiconductor device 1 in the active area AR1 also has the gate insulating film 18th who have favourited Gate Electrode 19th , the interlayer insulation film 20th , the source electrode 21 and a drain electrode 22nd on.

In the graduation area AR2 on the other hand, has the semiconductor device 1 ^{the n +} type SiC substrate 10, the buffer layer 11 who have favourited the epitaxial layer 12th of the n ^- type, the body area 13a p-type and the contact area 15a on. The semiconductor device 1 points in conclusion AR2 also the interlayer insulating film 20th , the contact electrode 21a and the drain electrode 22nd on.

In the active area AR1 and graduation area AR2 is the buffer layer 11 above the top surface 10a of the n ⁺ -type SiC substrate 10. The buffer layer 11 is an n-type semiconductor layer made of silicon carbide (SiC) coated with n-type impurities such as. B. nitrogen (N) or phosphorus (P) is doped, consists. That is, the buffer layer 11 as the semiconductor layer has the n-conductivity type. The concentration of the n-type impurity in the buffer layer 11 , for example, about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ^-3 , is lower than that in the n ⁺ -type SiC substrate 10. The buffer layer 11 has a thickness of, for example, about 3 to 20 μm.

The epitaxial layer 12th n ^- type is above the top surface 10a of the n ⁺ -type SiC substrate 10 in the active region AR1 and graduation area AR2 educated. The epitaxial layer 12th n ^- -type is an n-type semiconductor layer made of silicon carbide (SiC) coated with n-type impurities such as e.g. B. nitrogen (N) or phosphorus (P) is doped, consists. That is, the epitaxial layer 12th the n ^- -type semiconductor layer has the n-conductivity type. The concentration of n-type impurities in the epitaxial layer 12th of the n ^- type, for example, about 1 × 10 ¹⁵ to 1 × 10 16 cm ^-3 , is lower than that in the SiC substrate 10 of the n ⁺ type. The epitaxial layer 12th of the n ^- type has a thickness of, for example, about 5 to 50 μm.

In the example of 2 is the epitaxial layer 12th of the n ^- type over the buffer layer 11 educated. Alternatively, it can be used without a buffer layer provided 11 the epitaxial layer 12th of the n ^- type just above the top surface 10a of the SiC substrate 10 can be formed of the n ⁺ type.

The buffer layer 11 and the epitaxial layer 12th n ^- type are formed by the epitaxial growth method, for example. Alternatively, the buffer layer 11 and the epitaxial layer 12th n ^- -type by implanting p-type impurities such as e.g. B. Aluminum (Al) or boron (B) can be formed in the entire upper surface of the n ⁺ -type SiC substrate 10 by the ion implantation technique to reduce the concentration of the n-type impurities in the n ⁺ - SiC substrate 10. Type (the same applies to the second embodiment to be discussed later).

The following description is made on the assumption that the buffer layer 11 and the epitaxial layer 12th n ^- -type can be formed by the epitaxial growth method with an interface between the n ⁺ -type SiC substrate 10 and the buffer layer 11 as the top surface 10a of the n ⁺ type SiC substrate 10 is pictured. Alternatively, the buffer layer 11 and the epitaxial layer 12th n ^- -type are formed by the ion implantation technique, with the upper surface of the epitaxial layer 12th of the n ^- type as the top surface 10a ^{of the n +} -type SiC substrate 10 is illustrated.

In the active area AR1 is a body area 13th p-type in an upper layer of the epitaxial layer 12th of the n ^- type. The body area 13th p-type is a p-type semiconductor region, which is made of silicon carbide (SiC), which with the p-type impurities such as. B. aluminum (Al) or boron (B) is doped. That is, the body area 13th the p-type semiconductor region has the p-conductivity type. The concentration of p-type impurities in the body area 13th p-type is, for example, about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ^-3 . The body area 13th p-type has a thickness of, for example, about 1 to 2 µm.

In the graduation area AR2 is the body area 13a p-type in an upper layer of the epitaxial layer 12th of the n ^- type. The body area 13a p-type is a p-type semiconductor region, which is made of silicon carbide (SiC), which with the p-type impurities such as. B. aluminum (Al) or boron (B) is doped. That is, the body area 13a the p-type semiconductor region has the p-conductivity type. The concentration of p-type impurities in the body area 13a p-type is, for example, about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ^-3 . The body area 13a p-type has a thickness of, for example, about 1 to 2 µm.

There is a fear that the field intensity is close to the body area 13a of the p-type in the termination area AR2 becomes higher than the field intensity near the body area 13th p-type in the active area AR1 what causes the withstand voltage of the semiconductor device 1 falls off. Accordingly, it is preferable that the concentration of the p-type impurity in the body region 13a p-type is lower than the concentration of p-type impurities in the body region 13th p-type. This prevents or prevents the field intensity from being close to the body area 13a of the p-type in the termination area AR2 becomes higher than the field intensity near the body area 13th p-type in the active area AR1 , thereby reducing the withstand voltage of the semiconductor device 1 is improved.

There is also a concern that the field intensity of a portion of the body area 13a p-type on the opposite side of the active area AR1 becomes higher than the field intensity of a section of the body area 13a p-type on the active area side AR1 what causes the withstand voltage of the semiconductor device 1 falls off. Therefore, it is preferable that the concentration of the p-type impurity in this portion of the body region 13a p-type on the opposite side of the active area AR1 is lower than the concentration of the p-type impurity in the portion of the body region 13a p-type on the active area side AR1 . This prevents or prevents the field intensity of the section of the body area 13a p-type on the opposite side of the active area AR1 becomes higher than the field intensity of the portion of the body area 13a p-type on the active area side AR1 , thereby reducing the withstand voltage of the semiconductor device 1 is improved.

In the active area AR1 is the source area 14th of the n ⁺ type in an upper layer of the body region 13th formed of the p-type. The source area 14th from the n ⁺ -type is an n-type semiconductor region, which is made of silicon carbide (SiC) with the n-type impurities such as. B. nitrogen (N) or phosphorus (P) is doped, consists. That is, the source area 14th of the n ⁺ type as a semiconductor region has the n conductivity type. The concentration of n-type impurities in the source region 14th of the n ⁺ type, for example about 1 × 10 ¹⁹ to 1 × 10 20 cm ^-3 , is higher than the concentration of the n-type impurities in the epitaxial layer 12th of the n ^- type. The source area 14th of the n ⁺ type has a thickness of, for example, about 100 to 500 nm.

In the active area AR1 is the body contact area 15th of the p ⁺ type in an upper layer of the body region 13th formed of the p-type. The body contact area 15th p ⁺ -type is a p-type semiconductor region, which is made of silicon carbide (SiC) with the p-type impurities such as. B. aluminum (Al) or boron (B) is doped. That is, the body contact area 15th of the p ⁺ -type semiconductor region has the p-conductivity type. The concentration of p-type impurities in the body contact area 15th of the p ⁺ type, for example about 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ^-3 , is higher than the concentration of the n-type impurities in the body region 13th p-type. The body contact area 15th of the p ⁺ type has a thickness of, for example, about 100 to 500 nm.

In the graduation area AR2 is the contact area 15a in an upper layer of the body area 13a formed of the p-type. The contact area 15a is a p-type semiconductor region, which is made of silicon carbide (SiC), which with the p-type impurities such as. B. aluminum (Al) or boron (B) is doped. That is, the contact area 15a as a semiconductor region has the p conductivity type. The concentration of p-type impurities in the contact area 15a , for example about 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ^-3 , is higher than the concentration of the n-type impurities in the body region 13a p-type. The contact area 15a has a thickness of, for example, about 100 to 500 nm.

In the active area AR1 is an upper layer of the epitaxial layer 12th of the n ^- type, which is between two adjacent body areas 13th p-type is inserted, a junction field effect transistor area (JFET area) 16 . In other words, the JFET section 16 is an upper layer of the epitaxial layer 12th of the n ^- type, which are on the opposite side of the source region 14th of the n ⁺ -type, where the body region 13th p-type is interposed therebetween. In other words, the JFET area 16 is a semiconductor section that passes through an upper layer of the epitaxial layer 12th of the n ^- type adjacent to the body area 13th is formed of the p-type.

A canal area 17th is as the upper layer of the body area 13th p-type formed between the source region 14th of the n ⁺ type and the JFET area 16 is inserted, ie as the upper layer of the body area 13th of the p-type, which is between the source area 14th of the n ⁺ type and the epitaxial layer 12th of the n ^- type is inserted.

In the active area AR1 is the gate insulating film 18th above the top surface of the body area 13th formed of the p-type. The gate insulation film 18th is an insulating film that covers the top surface of the body area 13th p-type is formed between the source region 14th of the n ⁺ type and the epitaxial layer 12th of the n ^- type is inserted. The gate insulation film 18th consists for example of silicon oxide (SiO ₂ ), silicon oxide nitride (SiON), aluminum oxide (Al ₂ O ₃ ) or hafnium oxide (HfO ₂ ) and is formed by the thermal oxidation method or by the method of CVD (chemical vapor deposition). The gate insulation film 18th has a thickness of a few tens of nm, for example.

In the active area AR1 is the gate electrode 19th over the gate insulating film 18th educated. The gate electrode 19th is above the top surface of the body area 13th p-type, the gate insulating film 18th inserted in between, the gate electrode 19th between the source area 14th of the n ⁺ type and the epitaxial layer 12th of the n ^- type is inserted. The gate electrode 19th is a conductive layer made of, for example, polysilicon and formed by the CVD method.

In the example of 2 becomes the gate insulating film 18th successively formed in such a way that it stands out from the top surface of a given body area 13th p-type to the top surface of the adjacent body region 13th p-type extends and the top surface of the JFET region 16 includes that between the two body areas 13th p-type is inserted. In the example of 2 also becomes the gate electrode 19th successively formed in such a way that they stand out from the top surface of a given body area 13th p-type to the top surface of the adjacent body region 13th p-type and over the top surface of the JFET region 16 extends with the gate insulating film 18th is inserted in between.

In the active area AR1 is the interlayer insulating film 20th over the epitaxial layer 12th of the n ^- type, the body area 13th of the p-type, the source region 14th of the n ⁺ type and the body contact area 15th of the p ⁺ -type formed in such a way that it is the gate electrode 19th and the gate insulating film 18th covered. In the graduation area AR2 is the interlayer insulating film 20th over the epitaxial layer 12th of the n - type, the body area 13a p-type and the contact area 15a educated. The interlayer insulating film 20th consists for example of PSG (phosphosilicate glass) or silicon oxide.

In the active area AR1 has the interlayer insulating film 20th Contact holes 20a which are formed therein as openings. The contact holes 20a penetrate the interlayer insulation film 20th so that it is the top surface of the source area 14th of the n ⁺ type and the top surface of the body contact area 15th of the p ⁺ type. That is, at the bottom of the contact holes 20a lie the top surface of the source area 14th of the n ⁺ type and the top surface of the body contact area 15th of the p ⁺ type free.

In the graduation area AR2 has the interlayer insulating film 20th also contact holes 20b which are formed therein as openings. The contact holes 20b penetrate the interlayer insulation film 20th so that they are the top surface of the contact area 15a reach. That is, at the bottom of the contact holes 20b is the top surface of the contact area 15a free.

In the active area AR1 is the source electrode 21 within the contact holes 20a and over the interlayer insulating film 20th educated. The source electrode 21 is above the source area 14th of the n ⁺ type and the body contact area 15th formed of the p ⁺ type and with the source region 14th of the n ⁺ type and the body contact area 15th of the p ⁺ -type electrically connected. The source electrode 21 is for example a conductive layer made of titanium (Ti) or aluminum (Al). This conductive layer is used to make the source electrode 21 with the source area 14th of the n ⁺ type and with the body contact area 15th of the p ⁺ -type with low resistance to connect electrically.

In the graduation area AR2 is the contact electrode 21a within the contact holes 20b and over the interlayer insulating film 20th educated. The contact electrode 21a is above the contact area 15a formed and electrically connected to it. The contact electrode 21a can be a conductive layer made of titanium (Ti) or aluminum (Al), for example. This conductive layer is used to make the contact electrode 21a with the contact area 15a to connect electrically with low resistance. Alternatively, the contact electrode 21a in the same layer as that of the source electrode 21 be formed and with the source electrode 21 be electrically connected.

In the active area AR1 and graduation area AR2 is the drain electrode 22nd above the lower surface 10b of the n ⁺ -type SiC substrate 10. The drain electrode 22nd is electrically connected to ^{the n +} -type SiC substrate 10. The drain electrode 22nd can be a conductive layer laminated with titanium (Ti), nickel (Ni) or gold (Au), for example. This conductive layer is used to make the drain electrode 22nd to be electrically connected to the low resistance ^{n +} type SiC substrate 10.

Although in 2 not shown, passivation films may be provided over the top surface and the bottom surface of the semiconductor device 1 be formed in such a way that it is the gate electrode 19th , the interlayer insulation film 20th , the source electrode 21 , the contact electrode 21a and the drain electrode 22nd cover. As another alternative, openings may be formed in the portions of the passivation films in which pad areas for electrically connecting the gate electrode 19th , the source electrode 21 and the drain electrode 22nd be formed with the outside.

In the semiconductor device 1 involves a power up operation to turn on any vertical MISFET passing through the cell CL1 is shown, the application of a positive gate voltage VGS (VGS> 0 V) to the source electrode 21 through the gate electrode 19th . At this point, an inversion layer appears in an upper layer of the body area 13th of the p-type formed between the source region 14th of the n ⁺ type and the epitaxial layer 12th of the n ^- type is inserted, ie in the channel area 17th .

As a result, electrons flow from the source electrode 21 to the drain electrode 22nd through the source area 14th of the n ⁺ type, which are in the channel area 17th formed inversion layer, the epitaxial layer 12th of the n ^- type, the buffer layer 11 and the n ⁺ type SiC substrate 10. That is, the current flows from the drain electrode 22nd to the source electrode 21 through the n ⁺ -type SiC substrate 10, the buffer layer 11 who have favourited the epitaxial layer 12th of the n ^- type, which are in the canal area 17th formed inversion layer and the source region 14th of the n ⁺ type.

On the other hand, a turn-off operation involves turning off any vertical MISFET passed through the cell CL1 is shown, the application of a zero or a negative gate voltage VGS (VGS 0 V) to the source electrode 21 through the gate electrode 19th . At this point the in the canal area disappears 17th formed inversion layer, whereby consequently the current is switched off.

In the active area AR1 form the body contact area 15th of the p ⁺ type, the body area 13th p-type, the epitaxial layer 12th of the n ^- type, the buffer layer 11 ^{and the n +} -type SiC substrate 10 is a diode, the body diode 23 is called that between the source electrode 21 and the drain electrode 22nd is inserted. In the graduation area AR2 form the contact area 15a , the body area 13a p-type, the epitaxial layer 12th of the n ^- type, the buffer layer 11 ^{and the n +} -type SiC substrate 10 is a diode, the body diode 23a is called that between the contact electrode 21a and the drain electrode 22nd is inserted.

As later using 16 is discussed, multiple semiconductor devices 1 be included in an inverter circuit. In this setup any vertical MISFET running through the cell can be used CL1 is shown in each semiconductor device 1 can be switched from the on-state to the off-state. At this point a forward current flows through the body diodes 23 and 23a . In a semiconductor device 101 as a comparative example to be described later using 17th As discussed, the forward current flowing through the body diodes may suffer forward voltage degradation of the semiconductor device 101.

In the semiconductor device 1 of the first embodiment is a semiconductor region 24 n ^- type doped with inert elements in a portion of the epitaxial layer 12th of the n ^- type, which is below the body area 13th p-type in the active area AR1 is arranged, formed. The semiconductor sector 24 the n ^- type has the n conductivity type. The semiconductor sector 24 of the n ^- type is associated with the inert elements such. B. helium (He) or argon (Ar) and has crystal defects such. B. Point defects PD1 who are trained in it.

The concentration of inert elements in the semiconductor area 24 n ^- -type is higher than in the upper layer of the epitaxial layer 12th of the n ^- type, which is between two adjacent body areas 13th p-type is inserted. In other words, the concentration of the inert elements in the section of the epitaxial layer 12th of the n ^- type, which is below the body area 13th is p-type is higher than in the upper layer of the epitaxial layer 12th of the n ^- type, which are on the opposite side of the source region 14th of the n ⁺ -type, where the body region 13th p-type is interposed therebetween.

In other words, the epitaxial layer 12th of the n ^- type includes the JFET region 16 as a semiconductor portion consisting of the upper layer of the epitaxial layer 12th of the n ^- type adjacent to the body area 13th of the p-type. Either is the JFET section 16 doped with the inert elements in such a way that their concentration is lower than the concentration of the inert elements in the semiconductor region 24 of the n ^- type, or the JFET range 16 is not doped with the inert elements.

When a forward current through the body diodes 23 in the active area AR1 flows, consequently positive holes, which flow as a forward current, recombine with electrons at the crystal defects such as e.g. B. the point defects PD1 that are in the semiconductor field 24 of the n ^- type are formed. This prevents or prevents positive holes, which flow as a forward current, from interacting with electrons at stacking faults in the buffer layer 11 and in the epitaxial layer 12th recombine of the n ^{- type.} This in turn prevents or prevents the stacking faults in the buffer layer 11 and the epitaxial layer 12th of the n ^- -type, thus preventing or preventing the electrical resistance, known as on-resistance, from increasing as the on-state current flows through the semiconductor device 1 flows. As a result, forward voltage deterioration occurs in each semiconductor device 1 prevented or stopped when the forward current through the body diodes 23 in the semiconductor devices 1 flows contained in the power module that serves as an inverter circuit.

In 2 The reference character “h” denotes positive holes that flow as a forward current.

In the semiconductor device 1 the first embodiment is also a semiconductor region 24a n ^- type doped with the inert elements in a portion of the epitaxial layer 12th of the n ^- type, which is under the body area 13a of the p-type in the termination area AR2 is arranged. The semiconductor sector 24a the n ^- type has the n conductivity type. The semiconductor sector 24a of the n ^- type is associated with the inert elements such. B. helium (He) or argon (Ar) and has crystal defects such. B. the point defects PD1 who are trained in it.

The concentration of inert elements in the semiconductor area 24a of the n ^- type is higher than the concentration of the inert elements in the upper layer of the epitaxial layer 12th of the n ^- type, which is between two adjacent body areas 13th p-type in the active area AR1 is inserted. In other words, the concentration of the inert elements in the section of the epitaxial layer 12th of the n ^- type, which is below the body area 13a is p-type is higher than the concentration of the inert elements in the upper layer of the epitaxial layer 12th of the n ^- type, which are on the opposite side of the source region 14th of the n ^- -type, the body region 13th p-type is interposed therebetween.

In other words, either is the JFET area 16 doped with the inert elements in such a way that their concentration is lower than the concentration of the inert elements in the semiconductor region 24a of the n ^- type and the concentration of the inert elements in the semiconductor region 24a of the n ^- type, or the JFET range 16 is not doped with the inert elements.

When a forward current through the body diodes 23a flows, consequently positive holes, which flow as a forward current, recombine with electrons at the crystal defects such as e.g. B. the point defects PD1 that are in the semiconductor field 24a of the n ^- type are formed. This prevents or prevents positive holes, which flow as a forward current, from interacting with electrons at stacking faults in the buffer layer 11 and in the epitaxial layer 12th recombine of the n ^{- type.} This in turn prevents or prevents the stacking faults in the buffer layer 11 and in the epitaxial layer 12th of the n ^- -type, thus preventing or preventing the on-resistance in the semiconductor device 1 increases. As a result, forward voltage deterioration occurs in each semiconductor device 1 prevented or stopped when the forward current through the body diodes 23a in the semiconductor devices 1 flows contained in the power module that serves as an inverter circuit.

Helium (He) or argon (Ar) can preferably be used as inert elements. These inert elements are used in the semiconductor field 24 n ^- type implanted by, for example, the ion implantation technique. This easily forms crystal defects such as B. the point defects PD1 as places where positive holes, flowing as a forward current, recombine with electrons.

The concentration of the inert elements is preferably in the semiconductor region 24 of the n ^- type 1 × 10 ¹⁵ to 1 × 10 ²² cm ^-3 .

When the concentration of inert elements in the semiconductor area 24 of the n ^- -type were lower than 1 × 10 ¹⁵ cm ^-3 , there would only be a small number of positive holes of those flowing in as forward currents, which deal with electrons at the crystal defects such as e.g. B. the point defects PD1 recombine by the inert elements in the semiconductor area 24 of the n ^- type are formed. As a result, some of the positive holes flowing in as a forward current may form a lower layer of the Epitaxial layer 12th of the n ^- type or the buffer layer 11 reach. When the concentration of inert elements in the semiconductor area 24 of the n ^- -type would be higher than 1 × 10 ²² cm ^-3 , the semiconductor area would 24 of the n ^- type itself change in quality or a section of the epitaxial layer 12th of the n ^- type, which is the semiconductor region 24 of the n ^- -type would increase the electrical resistance.

As long as the concentration of inert elements in the semiconductor area 24 of the n ^- type is 1 × 10 ¹⁵ to 1 × 10 ²² cm ^-3 , consequently, the semiconductor region remains 24 of the n ^- -type unchanged in quality and the portion of the epitaxial layer 12th of the n ^- type, which is the semiconductor region 24 of the n ^- -type does not increase the electrical resistance. The positive holes, which flow in as a forward current, are also enabled to reliably interact with electrons at the crystal defects such as e.g. B. the point defects PD1 to recombine by the inert elements in the semiconductor field 24 of the n ^- type are formed.

In the semiconductor device 1 of the first embodiment is the concentration of the inert elements in a portion of the epitaxial layer 12th of the n ^- type, which is in the JFET range 16 is arranged, lower than in the semiconductor area 24 of the n-type. This causes the electrical resistance of the JFET area 16 is lower than that of the semiconductor area 24 of the n ^- type. This in turn reduces the on-resistance that occurs when there is an on-state current from the JFET area 16 to the source area 14th of the n ⁺ type over the channel area 17th flows.

The semiconductor region is preferably standing 24 of the n ^- type with the lower surface of the body area 13th p-type in contact. This allows positive holes through the body diodes 23 flow as a forward current and focus on the body area 13th move from p-type past to straight into the semiconductor area 24 of the n ^- -type to flow. The positive holes that are in the semiconductor area 24 flow of the n ^- -type, recombine with electrons at the crystal defects such. B. the point defects PD1 that are in the semiconductor field 24 of the n ^- type are formed. This prevents or prevents, more reliably than before, the positive holes that are located on the body area 13th p-type move past, with electrons past the stacking faults in the buffer layer 11 and in the epitaxial layer 12th recombine of the n ^{- type.} This prevents or prevents more reliably that the stacking faults in the buffer layer 11 and in the epitaxial layer 12th of the n ^- -type spread.

As with the concentration of inert elements in the semiconductor area 24 of the n ^- type is the concentration of the inert elements in the semiconductor region 24a of the n ^- type, preferably 1 × 10 ¹⁵ to 1 × 10 ²² cm ^-3 . And as with the semiconductor sector 24 n ^- type in contact with the lower surface of the body region 13th the semiconductor region is of the p-type 24a of the n ^- type preferably with the lower surface of the body region 13a p-type in contact.

The semiconductor sector 24 The n ^- type includes, in a plan view, a side portion SS1 that is on the side of the JFET region 16 is arranged. The body area 13th the p-type includes a side portion SS2 on the side of the JFET area 16 . In the first embodiment, the side portion SS1 is approximately at the same location as the side portion SS2 in the plan view. This makes it possible for the semiconductor field 24 n ^- -type using the same mask that is used to form the body region 13th of the p-type.

The section of the epitaxial layer 12th of the n ^- type, the between two adjacent semiconductor regions 24 of the n ^- type is inserted, has a width WD1 on. The section of the epitaxial layer 12th of the n ^- type, between two adjacent body areas 13th p-type inserted has a width WD2 on, i.e. the width of the JFET area 16 . In this setup, the width WD1 about the same as the width WD2 be.

The boundary between the epitaxial layer 12th of the n ^- type and the body area 13th the p-type may be arranged in such a manner that the magnitude correlation between the concentration of the p-type impurities and that of the n-type impurities is tilted exactly over the limit. The outer periphery of the semiconductor regions 24 n ^- type may be arranged in such a manner that the concentration of the inert elements becomes ^{1 × 10 15} cm ^-3.

<Semiconductor Device Manufacturing Process>

A typical process for manufacturing the semiconductor device 1 as a first embodiment will be described below with reference to the accompanying drawings. 3 and 4th Fig. 13 are flowcharts showing part of the manufacturing process for the semiconductor device as the first embodiment. 5 until 15th Fig. 13 are main part sectional views of the semiconductor device as the first embodiment which is in the manufacturing process. 4th FIG. 13 shows the manufacturing steps performed in step S14 of FIG 3 are included. 3 and 4th outline the manufacturing process of the active area AR1 covers.

^{The n +} -type SiC substrate 10 is first prepared (step S11 in FIG 3 ). As in 5 As shown, what is prepared in step S11 is the n ⁺ -type SiC substrate 10 which is made of silicon carbide (SiC) coated with the n-type impurities such as. B. nitrogen (N) or phosphorus (P) is doped. As discussed above, the concentration of n-type impurities in the n ⁺ -type SiC substrate 10 is relatively high, for example about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ^-3 . ^{The n +} -type SiC substrate 10 can have a thickness of, for example, approximately 50 to 500 μm.

The buffer layer 11 is formed next (step S12 in 3 ). In step S12, as in 5 shown is the buffer layer 11 by the epitaxial growth process over the top surface 10a of the n ⁺ -type SiC substrate 10 in the active region AR1 and graduation area AR2 educated. A buffer layer made of SiC is formed, for example, by maintaining the substrate temperature at about 1500 to 1800 ° C using a gas containing a silicon atom (Si atom) (SiH ₄ gas), a gas containing a chlorine atom (Cl atom) (HCl gas), a gas containing a carbon atom (C atom) (C ₃ H ₈ gas) and a reducing gas (H2 gas).

The buffer layer 11 is associated with the n-type impurities such as B. nitrogen (N) or phosphorus (P) doped. As mentioned above, the concentration of the n-type impurity in the buffer layer 11 for example about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ^-3 . The buffer layer 11 can have a thickness of, for example, about 3 to 20 μm.

The epitaxial layer 12th n ^- -type is then formed (step S13 in FIG 3 ). In step S13, as in 5 shown the epitaxial layer 12th n ^- type by the epitaxial growth method over the buffer layer in the active area AR1 and graduation area AR2 educated. The epitaxial layer 12th of the n ^- type, which consists of SiC, is obtained by maintaining the substrate temperature at about 1500 to 1800 ° C using a gas containing a silicon atom (Si atom) (SiH ₄ gas), a gas containing a chlorine atom (Cl atom) containing gas (HCl gas), a carbon atom (C atom) containing gas (C ₃ H ₈ gas) and a reducing gas (H ₂ gas).

The epitaxial layer 12th of the n ^- -type is associated with the impurities of the n-type such. B. nitrogen (N) or phosphorus (P) doped. As mentioned above, the concentration of n-type impurities in the epitaxial layer can be increased 12th of the n ^- type, for example, about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ^-3 . The epitaxial layer 12th of the n ^- type can, for example, have a thickness of about 5 to 50 μm.

As in 6th and 7th then shown are the body area 13th p-type and the semiconductor region 24 formed of the n ^- -type (step S14 in 3 ).

In step S14, as in 6th shown, a resist film RF1 first over the epitaxial layer 12th of the n ^- type in the active area AR1 formed (step S21 in 4th ). The resist film RF1 thus formed is subjected to exposure and development using photolithography. This creates openings OP1 from that penetrate the resist film RF1 so that they form the epitaxial layer 12th of the n ^- type in an area of the active area AR1 reach where the body area 13th p-type has been formed (step S22 in 4th ). At this point there is a resist pattern RP1 which consists of the resist film RF1 in which the openings OP1 were trained. At the bottom of the openings OP1 is the epitaxial layer 12th of the n ^- type free.

In the example of 6th when the resist film RF1 is in the active area AR1 is formed, the resist film RF1 is also formed over the epitaxial layer 12th of the n ^- type in the termination area AR2 educated. When the openings OP1 are formed become openings OP11 that penetrate the resist film RF1 so that they form the epitaxial layer 12th of the n ^- type, even in a region of the termination area AR2 trained where the body area 13a p-type. At this point there is a resist pattern RP11 which consists of the resist film RF1 in which the openings OP11 were trained. At the bottom of the openings OP11 is the epitaxial layer 12th of the n ^- type free.

As in 6th then the p-type impurities such as B. aluminum (Al) or boron (B) in the epitaxial layer 12th of the n-type in the active area AR1 implanted by the ion implantation technique, which the resist pattern RP1 used as a mask (step S23 in 4th ). This forms the body area 13th p-type in an upper layer of the epitaxial layer 12th of the n ^- type. As mentioned above, the concentration of p-type impurities in the body region can be 13th p-type, for example, about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ^-3 . The body area 13th p-type may have a thickness of, for example, about 1 to 2 µm.

In the example of 6th when the p-type impurities are in the active region AR1 are implanted, the p-type impurities such. B. aluminum (Al) or boron (B) also in the epitaxial layer 12th of the n ^- type in the termination area AR2 by the ion implantation technique using the resist pattern RP11 implanted as a mask. This forms the body area 13a p-type in an upper layer of the epitaxial layer 12th of the n ^- type in the termination area AR2 the end. As mentioned above, the concentration of p-type impurities in the body region can be 13a p-type, for example, about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ^-3 . The body area 13a p-type may have a thickness of, for example, about 1 to 2 µm.

The concentration of the impurity sites is preferably of the p-type in the body region 13a p-type lower than in the body area 13th p-type. This prevents or prevents the field intensity from being close to the body area 13a of the p-type in the termination area AR2 becomes higher than the field intensity near the body area 13th p-type in the active area AR1 , thereby reducing the withstand voltage of the semiconductor device 1 is improved.

Preferably, the concentration of the p-type impurities is in a portion of the body region 13a p-type on the opposite side of the active area AR1 lower than the concentration of inert elements in the section of the body area 13a p-type on the active area side AR1 . This prevents or prevents the field intensity of the section of the body area 13a p-type on the opposite side of the active area AR1 becomes higher than the field intensity of the portion of the body area 13a p-type on the active area side AR1 , which is consequently the withstand voltage of the semiconductor device 1 improved.

The steps for forming the body areas 13th and 13a of the p-type can be followed by a thermal treatment at, for example, about 1700 ° C. in order to activate the implanted impurities.

As in 7th shown, then the inert elements such. B. helium (He) or argon (Ar) in a portion of the epitaxial layer 12th of the n ^- type, which is below the body area 13th p-type in the active area AR1 is implanted by the ion implantation technique that forms the resist pattern RP1 used as a mask (step S24 in 4th ). At this point the inert elements are implanted in such a way that their concentration is in the section of the epitaxial layer 12th of the n ^- type, which is below the body area 13th is p-type becomes higher than the concentration of the inert elements in the upper layer of the epitaxial layer 12th of the n ^- type, which is between two adjacent body areas 13th p-type is inserted. This implants the inert elements in the portion of the epitaxial layer 12th of the n ^- type, which is below the body area 13th p-type is what is the semiconductor area 24 of the n ^- -type with crystal defects such as e.g. B. the point defects PD1 formed therein.

The inert elements are in an upper layer of the epitaxial layer 12th of the n ^- type adjacent to the body area 13th p-type, ie in a section that later becomes the JFET area 16 (see to be discussed later 14th ), implanted in such a way that the concentration of inert elements in the section leading to the JFET area 16 is lower than the concentration of inert elements in the semiconductor area 24 of the n ^- type. Alternatively, the inert elements are not implanted in the portion facing the JFET area 16 will.

This prevents or eliminates positive holes caused by the body diodes 23 flow as forward current, dealing with electrons at stacking faults in the buffer layer 11 and in the epitaxial layer 12th recombine of the n ^{- type.} This in turn prevents or prevents the stacking faults in the buffer layer 11 and in the epitaxial layer 12th of the n ^- type, thereby preventing or suppressing the on-resistance in the semiconductor device 1 increases.

Helium (He) or argon (Ar) can preferably be used as inert elements. Such inert elements can, for example, be introduced into the semiconductor region by the ion implantation technique 24 of the n ^- -type are implanted. This easily forms crystal defects such as B. the point defects PD1 as places where positive holes, which flow in as a forward current, recombine with electrons.

The concentration of the inert elements is preferably in the semiconductor region 24 of the n ^- type 1 × 10 ¹⁵ to 1 × 10 ²² cm ^-3 . This enables the semiconductor area 24 of the n ^- -type remains unchanged in quality, and prevents a portion of the epitaxial layer 12th of the n ^- type, which is the semiconductor region 24 of the n ^- type, increases the electrical resistance. The positive holes, which flow in as a forward current, are also enabled to reliably interact with electrons at the crystal defects such as e.g. B. the point defects PD1 to recombine by the inert elements in the semiconductor field 24 of the n ^- type are formed.

Preferably the semiconductor region 24 of the n ^- -type formed so that it fits with the lower surface of the body region 13th p-type is in contact. This more reliably prevents or prevents the positive holes that are located on the body area 13th p-type move past, with electrons past the stacking faults in the buffer layer 11 and in the epitaxial layer 12th recombine of the n ^{- type.}

In the example of 7th when the inert elements are in the active area AR1 are implanted, the inert elements such. B. helium (He) or argon (Ar) also in a section of the epitaxial layer 12th of the n ^- type implanted under the body area 13th of the p-type in the termination area AR2 lies. At this point the inert elements are implanted in such a way that their concentration is in the section of the epitaxial layer 12th of the n ^- type, which is below the body area 13a p-type becomes higher than that in the upper layer of the epitaxial layer 12th of the n ^- type, which is between two adjacent body areas 13th of p-type in the active area AR1 is inserted. This implants the inert elements in the portion of the epitaxial layer 12th of the n ^- type, which is below the body area 13a of the p-type in the termination area AR2 lies what the semiconductor field 24a of the n ^- -type with crystal defects such as e.g. B. the point defects PD1 formed therein.

That is, the inert elements are in the section leading to the JFET area 16 (see to be discussed later 14th ), implanted in such a way that the concentration of inert elements is lower than in the semiconductor area 24 of the n ^- type as well as in the semiconductor field 24a of the n ^- type. Alternatively, no inert elements are implanted in the section facing the JFET area 16 will.

In the examples of 6th and 7th can use the same resist pattern RP1 and RP11 can be used to implant the p-type impurities (step S23 in FIG 4th ) and to implant the inert elements (step S24 in 4th ). This helps reduce the number of steps that make up the semiconductor device manufacturing process and decrease the number of masks to be used during the process.

In the examples of 6th and 7th The same step can also be used to remove the p-type impurities into the active region AR1 to implant and the p-type impurities in the termination region AR2 to implant. Furthermore, the same step can be used to add the inert elements to the active area AR1 and implant the inert elements in the termination area AR2 to implant. This also helps reduce the number of steps that make up the semiconductor device manufacturing process and decrease the number of masks to be used during the process.

After the step for implanting the inert elements has been carried out (step S24 in FIG 4th ), the step of implanting the p-type impurities can be carried out (step S23 in FIG 4th ). Alternatively, step S14 can be carried out, as in FIG 8th until 11 shown.

In the examples of 8th until 11 first becomes the resist film RF1 over the epitaxial layer 12th of the n ^- type in the active area AR1 and graduation area AR2 formed (step S21 in 4th ), as in 8th shown. The openings OP1 be in the active area AR1 formed (step S22 in 4th ) to the resist pattern RP1 to produce, which consists of the resist film RF1, in which the openings OP1 were trained. At this point there are no openings in the termination area AR2 formed so that the epitaxial layer 12th n-type is covered with the resist film RF1.

As in 8th as shown, the p-type impurities are then introduced into the epitaxial layer 12th of the n ^- type in the active area AR1 implanted (step S23 in 4th ) to the body area 13th of the p-type. At this point is the epitaxial layer 12th of the n ^- type with the resist film RF1 in the termination region AR2 covered so that the p-type impurities do not enter the termination region AR2 be implanted.

As in 9 Next, the inert elements are shown in the active area AR1 implanted (step S24 in 4th ) to the semiconductor area 24 of the n ^- type. At this point is the epitaxial layer 12th of the n ^- type with the resist film RF1 in the termination region AR2 covered so that the inert elements do not enter the termination area AR2 be implanted.

As in 10 then the resist pattern is shown RP1 from the active area AR1 and graduation area AR2 removed. In the same way as the resist film RF1, a resist film RF2 becomes over the epitaxial layer 12th of the n ^- type in the active area AR1 and graduation area AR2 educated. openings OP2 are in the graduation area AR2 formed to a resist pattern RP2 to produce, which consists of the resist film RF2, in which the openings OP2 were trained. The openings OP2 penetrate the resist film RF1, making the epitaxial layer 12th of the n ^- type in a region of the termination area AR2 reach where the body area 13a is of the p-type. At this point, however, are the epitaxial layer 12th of the n ^- type and the body area 13th p-type in the active area AR1 covered with the resist film RF1.

As in 10 Next, the body area is shown 13a p-type by implanting the p-type impurities in the epitaxial layer 12th of the n ^- type in the termination area AR2 formed using the ion implantation technique, the resist pattern RP2 used as a mask. At this point are the epitaxial layers 12th of the n ^- type and the body area 13th p-type in the active area AR1 covered with the resist film RF2 so that the p-type impurities do not enter the active area AR1 be implanted.

As in 11 then the semiconductor area is shown 24a of the n ^- type by implanting the inert elements in the epitaxial layer 12th of the n ^- type in the termination area AR2 formed using the ion implantation technique, the resist pattern RP2 used as a mask. At this point are the epitaxial layers 12th of the n ^- type and the body area 13th p-type in the active area AR1 covered with the resist film RF2 so that the p-type impurities do not enter the active area AR1 be implanted.

In the examples of 8th until 11 can be the same resist pattern RP1 can also be used to implant the p-type impurities (step S23 in FIG 4th ) and to implant the inert elements (step S24 in 4th ). This also contributes to reducing the number of steps that make up the semiconductor device manufacturing process and lowering the number of masks to be used during the process.

In the examples of 8th until 11 a step is also performed to remove the p-type impurities in the active region AR1 to implant, and a different step is carried out to place the p-type impurities in the termination region AR2 to implant. Likewise, a step is carried out to remove the inert elements in the active area AR1 to implant, and a separate step is performed to place the inert elements in the termination region AR2 to implant. Consequently, the amount of p-type impurities that exist in the active area can be reduced AR1 and the amount of p-type impurities that are in the termination region AR2 implanted, can be set independently of each other. Likewise, the amount of inert elements that are in the active area AR1 to be implanted, and the amount of inert elements that are in the termination area AR2 implanted, can be set independently of each other.

Incidentally, the resist pattern made up of the resist film RF1 and the resist pattern made up of the resist film RF2 may be exchanged for the mask patterns made up of different types of films.

The source area 14th of the n ⁺ type is formed next (step S15 in FIG 3 ). In step S15, as in 12th shown the resist pattern RP1 or RP2 first removed. A resist film RF3 is then placed over the epitaxial layer 12th of the n ^- type, the body area 13th of the p-type and the body region 13a p-type in the active area AR1 and graduation area AR2 educated. The resist film RF3 thus formed is subjected to exposure and development using photolithography. This creates openings OP3 from that penetrate the resist film RF3 so that they can penetrate the body area 13th p-type in an area of the active area AR1 reach where the source area 14th is of the n ⁺ type. At this point there is a resist pattern RP3 which consists of the resist film RF3 in which the openings OP3 were trained. This defines the body area 13th p-type at the bottom of the openings OP3 free. In the graduation area AR2 on the other hand, no openings are formed, so that the epitaxial layer 12th of the n-type and the body area 13a p-type are covered with the resist film RF3.

Then the n-type impurities such as B. nitrogen (N) or phosphorus (P) in the body area 13th p-type by the ion implantation technique using the resist pattern RP3 implanted as a mask. This forms the source area 14th of the n ⁺ type in an upper layer of the body region 13th of the p-type. As mentioned above, the concentration of n-type impurities in the source region can be increased 14th of the n ⁺ type, for example, about 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ^-3 . The source area 14th of the n ⁺ type can have a thickness of, for example, about 100 to 500 nm. At this point are the epitaxial layers 12th of the n ^- type and the body area 13a of the p-type in the termination area AR2 are covered with the resist film RF3 and are not doped with n-type impurities.

Next is the body contact area 15th of the p ⁺ -type (step S16 in 3 ). In step S16, as in 13th shown the resist pattern RP3 first removed. Then a resist film RF4 is made over the epitaxial layer 12th of the n ^- type, the body area 13th of the p-type, the body area 13a p-type and the source region 14th of the n ⁺ type in the active area AR1 educated. The resist film RF4 thus formed is subjected to exposure and development using photolithography. This creates openings OP4 out that penetrate the resist film RF4 so that they can penetrate the body area 13th p-type or the source region 14th of the n ⁺ type in an area of the active area AR1 reach in which the body contact area 15th is of the p ⁺ type. At this point there is a resist pattern RP4 generated from the resist film OP4 consists in which the openings OP4 were trained. At the bottom of the openings OP4 is the body area 13th p-type or the source region 14th of the n ⁺ type free.

In the example of 13th when the resist film RF4 is in the active area AR1 is formed, the resist film RF4 is also formed over the epitaxial layer 12th of the n ^- type and the body area 13a of the p-type in the termination area AR2 educated. And if the openings OP4 are formed become openings OP41 that penetrate the resist film RF4 so that they are the body area 13a of the p-type even in an area of the termination area AR2 formed where the contact area 15a is trained. At this point there is a resist pattern RP41 which consists of the resist film RF4 in which the openings OP41 were trained. At the bottom of the openings OP41 is the body area 13a p-type free.

As in 13th then the p-type impurities such as B. aluminum (Al) or boron (B) in the body area 13th p-type or in the source area 14th of the n ⁺ type in the active area AR1 by the ion implantation technique below Using the resist pattern RP4 implanted as a mask. This forms the body contact area 15th of the p ⁺ type in an upper layer of the body region 13th p-type in the active area AR1 the end. As mentioned above, the concentration of the p-type impurity in the body contact area can be increased 15th of the p ⁺ type, for example, about 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ^-3 . The body contact area 15th of the p ⁺ type can have a thickness of, for example, about 100 to 500 nm.

In the example of 13th when the p-type impurities are in the active region AR1 are implanted, the p-type impurities such. B. aluminum (Al) or boron (B) also in the body area 13a of the p-type in the termination area AR2 by the ion implantation technique using the resist pattern RP4 implanted as a mask. This forms the contact area 15a in an upper layer of the body area 13a of the p-type. As mentioned above, the concentration of the p-type impurity in the contact area can be increased 15a for example about 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ^-3 . The contact area 15a can have a thickness of, for example, about 100 to 500 nm.

The steps for forming the source region 14th of the n ⁺ type, the body contact area 15th of the p ⁺ type and the contact area 15a can be performed either in the sequence described above or in any other sequence as long as appropriately patterned resist films are used as masks. The resist pattern composed of the resist film RF3 and the resist pattern composed of the resist film RF4 can also be replaced with other mask patterns composed of different types of films. Furthermore, any or all of the steps for forming the source region 14th of the n ⁺ type, the body contact area 15th of the p ⁺ type and the contact area 15a a heat treatment at about 1700 ° C follow in order to activate the implanted impurities.

As in 14th are then shown the gate insulating film 18th and the gate electrode 19th formed (step S17 in 3 ).

In step S17, as in FIG 14th shown an insulation film 18a over the top surfaces of the epitaxial layer 12th of the n ^- type, the body area 13th p-type, the source region 14th of the n ⁺ type and the body contact area 15th of the p ⁺ type in the active area AR1 educated. Preferably, the insulating film 18a can be formed from any of various types of films made of, for example, silicon oxide (SiO ₂ ), silicon oxide nitride (SiON), aluminum oxide (Al ₂ O ₃ ), or hafnium oxide (HfO ₂ ). As another preferred alternative, the insulating film 18a be a laminated film composed of the above-mentioned various types of films. The isolation film 18a is produced, for example, by the CVD method.

A conductive layer 19a is next over the insulation film 18a educated. The conductive layer 19a may consist of polysilicon in which the n-type impurities such as e.g. B. phosphorus (P) or arsenic (As) are diffused in high concentration, or consist of polysilicon in which the p-type impurities such. B. boron (B) can be diffused in high concentration. The conductive layer 19a is formed by the CVD method, for example.

As in 14th are then shown the conductive layer 19a and the insulation film 18a patterned to the gate electrode 19th and the gate insulating film 18th to train. The step of forming the gate electrode 19th and the gate insulating film 18th includes structuring, ie machining, of the conductive layer 19a and the insulation film 18a by photolithography and dry etching. In particular, the gate electrode 19th and the gate insulating film 18th patterned by the dry etching technique using, for example, a resist film patterned by photolithography as a mask. This step transforms the conductive layer 19a into the gate electrode 19th and the insulation film 18a into the gate insulating film 18th around.

In the example of 14th becomes the gate insulating film 18th successively formed in such a way that it stands out from the top surface of a given body area 13th p-type to the top surface of the adjacent body region 13th p-type extends and the top surface of the JFET region 16 includes the one between the two body areas 13th p-type is inserted. In the example of 14th also becomes the gate electrode 19th successively formed in such a way that they stand out from the top surface of a given body area 13th p-type to the top surface of the adjacent body region 13th p-type and over the top surface of the JFET region 16 extends with the gate insulating film 18th is inserted in between.

The interlayer insulating film 20th is formed next (step S18 in 3 ). In step S18, as in 15th shown, the interlayer insulating film 20th over the epitaxial layer 12th of the n ^- type, the body area 13th of the p-type, the source region 14th of the n ⁺ type and the body contact area 15th of the p ⁺ -type formed in such a way that it is the gate electrode 19th and the gate insulating film 18th in the active area AR1 covered. In step S18, as in 15th also shown the interlayer insulating film 20th over the epitaxial layer 12th of the n ^- type, the body area 13a from p- Type and the contact area 15a in the graduation area AR2 educated. The interlayer insulating film 20th can for example consist of silicon oxide and be formed by the CVD method.

The source electrode 21 is then formed (step S19 in 3 ). In step S19, as in 15th shown the contact holes 20a and 20b first as openings in the interlayer insulating film 20th in the active area AR1 and graduation area AR2 using photolithography and etching.

In the active area AR1 become the contact holes 20a formed the interlayer insulating film 20a penetrate so that they penetrate the source area 14th of the n ⁺ type and the body contact area 15th of the p ⁺ type. At the bottom of the contact holes 20a lie the top surface of the source area 14th of the n ⁺ type and those of the body contact area 15th of the p ⁺ type free.

In the graduation area AR2 on the other hand become the contact holes 20b who have favourited the interlayer insulation film 20th penetrate so that they penetrate the contact area 15a reach, trained. At the bottom of the contact holes 20b is the top surface of the contact area 15a free.

As in 15th then, in step S19, a conductive layer made of titanium (Ti) or aluminum (Al) is placed in the contact holes 20a and over the interlayer insulating film 20th in the active area AR1 deposited for example by the evaporation process or by the sputtering process. This forms the source electrode 21 the end.

In step S19, as in 15th Also shown is a conductive layer made of titanium (Ti) or aluminum (Al) in the contact holes 20b and over the interlayer insulating film 20th in the graduation area AR2 deposited for example by the evaporation process or by the sputtering process. This forms the contact electrode 21a the end. The contact electrode 21a may be in the same layer as that of the source electrode 21 and can be electrically connected to the latter.

The drain electrode 22nd is formed next (step S20 in 3 ). In step S20, a metal film composed of titanium (Ti), nickel (Ni), gold (Au), or silver (Ag), or a laminated film composed of metal films of at least two of these elements is typically formed by evaporation or by Sputtering over the lower surface 10b of the n ⁺ -type SiC substrate 10 in the active region AR1 and graduation area AR2 deposited. This forms the drain electrode 22nd above the lower surface 10b of the n ⁺ -type SiC substrate 10 in the active region AR1 and graduation area AR2 off, thus the semiconductor device 1 such as B. an in 2 shown is manufactured.

Although in 2 not shown, can after the drain electrode 22nd is formed passivation films over the top surface and the bottom surface of the semiconductor device 1 can be formed in such a way that they are the gate electrode 19th , the interlayer insulation film 20th , the source electrode 21 , the contact electrode 21a and the drain electrode 22nd cover. Openings can then be formed in the portions of the manufactured passivation films in which pad areas for electrically connecting the gate electrode 19th , the source electrode 21 and the drain electrode 22nd be formed with the outside.

<Power module, power converter and motor system>

A power module, a power converter, and a motor system according to the first embodiment will be described below. The power module includes the semiconductor device of the first embodiment.

16 Fig. 13 is a schematic view showing a structure of an engine system using the first embodiment.

As in 16 shown includes the engine system 30th a power converter 31 acting as an inverter device, a load 32 , typically formed by a motor, is a direct current power source 33 (DC power source), and a capacitance 34 such as B. a capacitor. The power converter 31 includes a power module 35 acting as an inverter circuit and a control circuit 36 . Weight 32 is with two output connections TO1 and TO2 of the power module 35 tied together. The DC power source 33 and the capacity 34 are between two input ports TI1 and TI2 of the power module 35 connected in parallel with each other.

The power module 35 , which acts as an inverter circuit, includes switching elements 37u , 37v , 37x and 37y . The switching elements 37u and 37x are between the input terminals TI1 and TI2 connected in series. The switching elements 37v and 37y are between the input terminals TI1 and TI2 connected in series.

Each of the switching elements 37u , 37v , 37x and 37y includes a MISFET 38 and a body diode 39 that came with the MISFET 38 is connected in parallel. The semiconductor device 1 the first embodiment (see 2 ) can be used as any of the switching elements 37u , 37v , 37x and 37y be used. In this case the body diode can 23 that is contained in every vertical MISFET that runs through the cell CL1 in every semiconductor device 1 is shown as a body diode 39 can be used (see 2 ).

The gate electrodes of the MISFETs 38 that are individually in the switching elements 37u , 37v , 37x and 37y are included are each with four control connections TC1, TC2, TC3 and TC4 of the power module 35 tied together. The control circuit 36 is also connected to the control terminals TC1, TC2, TC3 and TC4. This means that the control circuit 36 with the gate electrodes of the MISFETs 38 connected individually in the switching elements 37u , 37v , 37x and 37y are included. The control circuit 36 controls the switching elements 37u , 37v , 37x and 37y at.

The control circuit 36 controls the switching elements 37u , 37v , 37x and 37y in such a way that the on-state or off-state of a set of switching elements 37u and 37y with the on-state or off-state of another set of switching elements 37v and 37x alternates. This enables the power module 35 As an inverter circuit, an alternating voltage (AC voltage) is generated from a direct voltage (DC voltage), whereby direct current power is converted into alternating current power. The AC power drives the load 32 at.

<Forward voltage deterioration caused by forward current>

The forward voltage degradation of the semiconductor device caused by the forward current flowing therethrough will be discussed below with reference to FIG 16 and 17th and in comparison with a semiconductor device of a comparative example. 17th Fig. 13 is a set of main part sectional views of the semiconductor device of the comparative example.

As with the semiconductor device 1 In the first embodiment, the semiconductor device 101 of the comparative example includes vertical MISFETs made of silicon carbide. In contrast to the semiconductor device 1 the first embodiment is the semiconductor region 24 n-type (see 2 ), which is doped with the inert elements, not in the section of the epitaxial layer 12th of the n ^- type, which is under the body area 13th is arranged in the p-type.

A case will be described below in which the semiconductor devices 101 of the comparative example are used as switching elements 37u , 37v , 37x and 37y in the power module 35 can be used as described above using 16 explained inverter circuit works.

Let it be assumed that the load 32 connected to the output terminals TO1 and TO2 of the power module 35 is connected, has a large inductance. In this case, it causes switching of each of the switching elements 37u , 37v , 37x and 37y from the on-state to the off-state that a forward current flows in a direction opposite to that of the on-state current of each switching element. This requires the power module to be missed 35 as an inverter circuit with a diode connected to each MISFET 38 the switching elements 37u , 37v , 37x and 37y is connected in parallel to allow the forward current to flow.

The semiconductor device 101 with the vertical MISFET, on the other hand, has body diodes 123 and 123a interposed between the source electrode 21 or contact electrode 21a and the drain electrode 22nd in the active area AR1 and graduation area AR2 are inserted, the body diode 123 being able to let the forward current flow. Consequently, the power module has 35 with the vertical MISFETs as its switching elements 37u , 37v , 37x and 37y no need to have additional diodes mounted in a manner outside of these MISFETs.

However, if the vertical MISFETs that are in the power module 35 which functions as an inverter circuit are made of SiC, forward current flowing through the diodes within the vertical MISFETs may experience forward voltage degradation, which leads to an increase in the on-resistance of the MISFETs. The forward voltage degradation, when it occurs, increases the power dissipation of the power module 35 that acts as an inverter circuit.

What takes place here is that when the forward current flows through the body diode 123 in the semiconductor device 101 as a vertical MISFET made of SiC, positive holes flowing through the semiconductor, which is typically made of SiC, coincide Recombine electrons at crystal defects in the semiconductor. This increases the concentration of crystal defects within the semiconductor.

For example, when the forward current flows through the body diode 123 in the semiconductor device 101 as a vertical MISFET made of SiC, the positive holes that flow as the forward current recombine with electrons on stacking faults or on various crystal defects that potentially become stacking faults , in the Buffer layer 11 and in the epitaxial layer 12th of the n ^- type. The energy from the recombination of positive holes and electrons spreads the stacking faults in the buffer layer 11 and in the epitaxial layer 12th of the n ^- type. This incurs forward voltage degradation, which causes the electrical resistance called on-resistance in the semiconductor device 101 to increase.

Therefore, it is necessary to minimize the forward current flowing through the body diode 123 when the semiconductor device 101 of the comparative example is used as a switching element. This may require the control circuit 36 synchronous rectification such as B. switching each of the semiconductor devices 101 to the on-state in synchronism with the forward current flowing through the body diode 123. As a result, it is difficult to adjust the design tolerance of the power module 35 that functions as an inverter circuit with the semiconductor device 101 of the comparative example. This in turn makes it difficult to monitor the performance of the power module 35 as an inverter circuit with the semiconductor device 101 of the comparative example.

Alternatively, in order to minimize the forward current flowing through the body diode 123 in the semiconductor device 101, another diode must be provided in a manner outside the body diode 123. This makes the power module difficult 35 as an inverter circuit with the semiconductor device 101 of the comparative example to be reduced in size.

According to the technology disclosed in Patent Literature 1 cited above, a minority carrier removing layer is provided between the n-type SiC substrate and the n-type buffer layer. Also, according to the technology of Patent Literature 1 cited above, application of an electron beam to the area where the minority carrier removing layer is formed creates carbon hole defects in the n-type SiC substrate made of silicon carbide. This means that the cited technology can suffer stacking faults that are located in the buffer layer 11 and in the epitaxial layer 12th n-type propagate when positive holes flowing as a forward current recombine with electrons at various defects already in the buffer layer 11 and in the epitaxial layer 12th of the n ^- type are present.

When the vertical MISFETs that are in the power module 35 which functions as an inverter circuit are made of SiC, a forward current flowing through the body diodes 123a in these MISFETs suffers forward voltage deterioration as in the case where the forward current flows through the body diodes 123.

<Main Features and Effects of This Embodiment>

In the semiconductor device 1 the first embodiment is the semiconductor region 24 n ^- type doped with the inert elements in a portion of the epitaxial layer 12th of the n ^- type, which is under the body area 13th is of the p-type. The concentration of inert elements in the semiconductor area 24 n ^- -type is higher than in the upper layer of the epitaxial layer 12th of the n ^- type adjacent to the body area 13th p-type.

Let us consider a case where the semiconductor device 1 of the first embodiment as each of the switching elements 37u , 37v , 37x and 37y of the power module 35 is used as described above using 16 discussed inverter circuit works. In this case, when the load caused 32 , which is connected to the output terminals TO1 and TO2, has a large inductance, the switching of each of the switching elements 37u , 37v , 37x and 37y from the on-state to the off-state, that a forward current flows through the inverter circuit in a direction opposite to that of the on-state current of each switching element.

With the semiconductor device 1 the first embodiment, which is used as a switching element when a forward current through the body diode 23 flows, however, positive holes recombine from the body area 13th p-type into the epitaxial layer 12th of the n ^- type flow, with electrons at crystal defects caused by the implantation of the inert elements in the semiconductor region 24 of the n ^- type.

At the time the forward current through the body diode 23 flows, is consequently prevented or prevented that the positive holes, which act as a forward current from the body area 13th p-type to the epitaxial layer 12th of the n ^- -type flow, interacting with electrons at various crystal defects in the buffer layer 11 or in the epitaxial layer 12th recombine of the n ^{- type.} This prevents or prevents the propagation of stacking faults in the buffer layer 11 and in the epitaxial layer 12th of the n ^- type, that is, prevents or prevents an increase in the concentration of crystal defects therein. This in turn prevents or suppresses the forward voltage degradation in the semiconductor device 1 occurs.

Also, in the first embodiment, the forward voltage deterioration rarely occurs even if the forward current passes through the body diode 23 in the semiconductor device 1 flows. Consequently, it is unnecessary for the control circuit 36 synchronous rectification such as B. Switching each of the semiconductor devices 101 to the on-state in synchronism with the forward current flowing through the body diode 23 flows, performs. This makes it possible to adjust the design tolerance of the power module 35 as an inverter circuit with the semiconductor device 1 of the first embodiment as well as the design tolerance of the power converter 31 with the power module 35 to expand. This in turn improves the performance of the power module 35 and that of the power converter 31 .

Since the first embodiment rarely suffers forward voltage degradation even when the forward current through the body diode 23 in the semiconductor device 1 flows, it is also unnecessary to use another diode in a way outside the body diode 23 in the semiconductor device 1 provide. This helps reduce the size of the power module 35 and the power converter 31 at.

The semiconductor region is preferred 24a n ^- type doped with the inert elements in a portion of the epitaxial layer 12th of the n ^- type, which is under the body area 13a of the p-type in the termination area AR2 lies. The concentration of inert elements in the semiconductor area 24a n ^- type is higher than the upper layer of the epitaxial layer 12th of the n ^- type adjacent to the body area 13th p-type in the active area AR1 . This prevents or eliminates the electrical resistance in the semiconductor device 1 increases due to the forward voltage degradation that occurs when the forward current through the body diode increases 23a in every semiconductor device 1 that flows in the power module 35 is included, which acts as an inverter circuit.

The first embodiment also applies to a case in which the n ⁺ -type SiC substrate 10 is replaced by a semiconductor substrate made of any of various semiconductor materials such as. Silicon (Si) or gallium nitride (GaN), and a semiconductor layer composed of any of these semiconductor materials is used as the n ^- -type epitaxial layer. In such a case, the same effects as those of the semiconductor device constituting the first embodiment are still obtained, although they are less conspicuous than when silicon carbide is used as the semiconductor material (the same applies to the second embodiment to be discussed below.

Second embodiment

<Semiconductor device>

A semiconductor device as a second embodiment of the present invention will be described below. The semiconductor device of the second embodiment includes vertical MISFETs each made of silicon carbide (SiC).

As with the semiconductor device 1 of the first embodiment has the semiconductor device 1 of the second embodiment, the semiconductor region 24 n ^- - Type up. Note that, in a plan view, the side portion SS1 of the semiconductor region 24 n ^- type on the opposite side of the JFET area 16 is arranged, the side section SS2 of the body area 13th p-type is interposed therebetween.

18th Fig. 13 is a set of main part sectional views of the semiconductor device as a second embodiment of the present invention.

In the semiconductor device 1 of the second embodiment are the portions other than the semiconductor region 24 n ^- type and the semiconductor region 24a n ^- -type are essentially the same as their counterparts in the semiconductor device 1 of the first embodiment and are therefore not explained further.

In the semiconductor device 1 the second embodiment is like the semiconductor device 1 of the first embodiment the semiconductor area 24 n ^- type doped with the inert elements in a portion of the epitaxial layer 12th of the n ^- type, which is under the body area 13th p-type in the active area AR1 lies. This prevents or suppresses forward voltage degradation in the semiconductor device 1 occurs when a forward current through the body diode 23 in every semiconductor device 1 that flows in the power module 35 is included, which acts as an inverter circuit (see 16 ).

In the semiconductor device 1 the second embodiment is also the same as the semiconductor device 1 of the first embodiment the semiconductor area 24a n ^- type doped with the inert elements in a portion of the epitaxial layer 12th of the n ^- type, which is under the body area 13a of the p-type in the termination area AR2 lies. This prevents or suppresses forward voltage degradation in the semiconductor device 1 occurs when a forward current through the body diode 23a in every semiconductor device 1 that flows in the power module 35 is included, which acts as an inverter circuit (see 16 ).

In a plan view, the semiconductor region comprises 24 of the n ^- type, the side section SS1 that is on the side of the JFET area 16 is arranged. The body area also includes 13th p-type, the side portion SS2 on the side of the JFET area 16 . In the second embodiment, however, is the Side section SS1 in a plan view on the opposite side of the JFET area 16 with the side portion SS2 interposed therebetween. As discussed above in connection with the first embodiment, is the JFET area 16 an upper layer of the epitaxial layer 12th of the n ^- type adjacent to the body area 13th p-type.

The section of the epitaxial layer 12th of the n ^- type, the between two adjacent semiconductor regions 24 of the n ^- type is inserted, has the width WD1 on. The section of the epitaxial layer 12th of the n ^- type, between two adjacent body areas 13th p-type is inserted, has the width WD2 on, i.e. the width of the JFET area 16 . In this setup is the width WD1 wider than the width WD2 . Consequently, there is a portion of the epitaxial layer 12th of the n ^- type, which is below the JFET area 16 lies where the concentration of inert elements is lower than in the semiconductor areas 24 of the n ^- type, that is, a section PR1 the epitaxial layer 12th n ^- type, which forms a current path that allows a current to flow, made wider in the flat area than the JFET area 16 . This reduces the on-resistance of any vertical MISFET passed through the cell CL1 is shown.

Preferably is a lower end LE1 of the side section SS1 is arranged on the opposite side of the side section SS2 in plan view, with an upper end UE1 of the side section SS1 is inserted therebetween. Hence is a width WD11 of the portion of the epitaxial layer 12th of the n ^- type, which is between the lower ends LE1 of the side sections SS1 of two adjacent semiconductor regions 24 n ^- type is inserted, made wider than one width WD12 of the portion of the epitaxial layer 12th of the n ^- type, which is between the upper ends UE1 of the side sections SS1 of these two adjacent semiconductor regions 24 - type is inserted ^- n. That is, an upper flat surface of the section PR1 the epitaxial layer 12th the n ^- type forming the current path is made wider than an upper flat surface of the section PR1 . This shortens the length of the current path for a current flowing through a portion of the n ⁺ -type SiC substrate 10 of the JFET region 16 flows away in plan view and around the side portion SS1 of the semiconductor region 24 the n ^- type goes to in the JFET range 16 to flow. This in turn reduces the on-resistance of any vertical MISFET passed through the cell CL1 is shown.

More preferred is the side portion SS1 of the semiconductor region 24 of the n ^- type an inclined in such a way that the lower end LE1 of the side section SS1 is arranged on the opposite side of the side section SS2 in plan view, the upper end UE1 of the side section SS1 is inserted therebetween. This allows that width WD1 of the portion of the epitaxial layer 12th of the n ^- type, which is between the side sections SS1 of two adjacent semiconductor regions 24 of the n ^- type is inserted, is progressively wider from top to bottom. That is, the flat area of the section PR1 the epitaxial layer 12th of the n ^- type, which forms the current path, is made progressively wider from top to bottom. This further shortens the length of the current path for the current flowing through a portion of the n ⁺ -type SiC substrate 10 of the JFET region 16 flows away in plan view and around the side portion SS1 of the semiconductor region 24 the n ^- type goes to in the JFET range 16 to flow. This further reduces the on-resistance of any vertical MISFET passed through the cell CL1 is shown.

Here it is assumed that the symbol θ the angle of the side portion SS1 relative to a plane perpendicular to the top surface 10a of the n ⁺ type SiC substrate 10, that is, the angle of the side of the portion PR1 , which forms the current path, relative to a plane perpendicular to the upper surface 10a of the n ⁺ type SiC substrate 10. In this case the angle is θ most preferably 45 degrees. That is, the angle θ may preferably range from about 30 to 60 degrees, and most preferably from 43 to 47 degrees. This enables the semiconductor region to be formed 24 of the n ^- type under the body area 13th of the p-type and shortens the length of the current path for the current flowing through a portion of the SiC substrate 10 of the n ⁺ -type of the JFET region 16 flows away in the plan view and around the side portion SS1 of the semiconductor region 24 the n ^- type goes to in the JFET range 16 to flow.

<Semiconductor Device Manufacturing Process>

A typical process for manufacturing the semiconductor device as a second embodiment will be described below with reference to the accompanying drawings. 19th Fig. 13 is a flow chart showing part of the manufacturing process for the semiconductor device as a second embodiment. 20th until 22nd Fig. 13 are main part sectional views of the semiconductor device as a second embodiment which is in the manufacturing process. 19th FIG. 10 shows the process in step S14 of FIG 3 included manufacturing steps. In particular, outlines 19th the manufacturing process that covers the active area AR1 covers.

As with the process for manufacturing the semiconductor device of the first embodiment, the process for manufacturing the semiconductor device of the second embodiment includes performing steps S11 to S13 in FIG 3 to sequentially apply the buffer layer 11 and the epitaxial layer 12th of the n ^- type above the top surface 10a of SiC substrate 10 of the n ⁺ type in the active region AR1 and graduation area AR2 to train.

Next up are the body area 13th p-type and the semiconductor region 24 of the n ^- type, as in 20th until 22nd shown (step S14 in 3 ).

In the second embodiment, unlike the first embodiment, step S14 first involves forming a resist film RF5 over the epitaxial layer 12th of the n ^- type in the active area AR1 , as in 20th shown (step S31 in 19th ). The resist film RF5 thus formed is subjected to exposure and development using photolithography. This creates openings OP5 from which penetrate the resist film RF5 so that they form the epitaxial layer 12th of the n ^- type in an area of the active area AR1 reach where a semiconductor area 25th n ^- -type is formed (step S32 in FIG 19th ). At this point there is a resist pattern RP5 which consists of the resist film RF5 in which the openings OP5 were trained. At the bottom of the openings OP5 is the epitaxial layer 12th of the n ^- type free.

In the example of 20th when the resist film RF5 is in the active area AR1 is formed, the resist film RF5 is also formed over the epitaxial layer 12th of the n ^- type in the termination area AR2 educated. When the openings OP5 are formed become openings OP51 that penetrate the resist film RF5, making them the epitaxial layer 12th of the n ^- type, even in a region of the termination area AR2 formed where a semiconductor area 25a is of the n ^- type. At this point there is a resist pattern RP51 which consists of the resist film RF5 in which the openings OP51 were trained. At the bottom of the openings RP51 is the epitaxial layer 12th of the n ^- type free.

The next step performed is the same as step S24 in FIG 4th for the first embodiment, as in 20th shown. The step involves using the ion implantation technique to remove the inert elements such as B. helium (He) or argon (Ar) in the epitaxial layer 12th of the n ^- type using the resist pattern RP5 as a mask (step S33 in 19th ). Implanting the inert elements in the epitaxial layer 12th of the n ^- type creates the semiconductor region 25th of the n ^- -type with crystal defects such as e.g. B. the point defects PD1 that are formed in it. The concentration of inert elements in the semiconductor area 25th of the n ^- type is higher than the concentration of the inert elements in the upper layer of the epitaxial layer 12th of the n ^- type adjacent to the body area 13th p-type.

In the example of 20th when the inert elements are in the active area AR1 are implanted, the inert elements such. B. helium (He) or argon (Ar) also in the epitaxial layer 12th of the n ^- type in the termination area AR2 implanted. Implanting the inert elements in the epitaxial layer 12th of the n ^- type creates the semiconductor region 25a of the n ^- -type with crystal defects such as e.g. B. the point defects formed therein PD1 . The concentration of inert elements in the semiconductor area 25a of the n ^- type is higher than the concentration of the inert elements in the upper layer of the epitaxial layer 12th of the n ^- type adjacent to the body area 13th p-type in the active area AR1 .

It is believed to be the body area 13th p-type a thickness Dpb having. It is believed to have a depth Dimp between the top surface of the body area 13th p-type, the top surface of the source region 14th of the n ⁺ type and the top surface of the body contact area 15th of the p ⁺ -type on the one hand and the place in which the inert elements are implanted on the other hand exists. The depth Dimp is determined by the ion energy Eimp released when the inert elements are implanted by the ion implantation technique. It is believed to be a distance Dx between a side portion SS3 of the resist film RF5 passing through the openings OP5 exposed in the resist pattern RP5 are formed, which serves as a mask for the ion implantation of the inert elements, on the one hand and the side section SS2 of the body region 13th of the p-type, on the other hand, exists. As mentioned above, the angle is θ the angle of the side portion SS1 relative to a plane perpendicular to the top surface 10a of the n ⁺ type SiC substrate 10, that is, the angle of the side of the portion PR1 , which forms the current path, relative to a plane perpendicular to the upper surface 10a of the n ⁺ type SiC substrate 10. In this case the distance will be Dx is determined in a manner satisfying Expression (1) below. $$\text{Dimp}\le \text{Dx}\times \text{tan}\left(90-0\right)+\text{Dpb}$$

That is, the distance Dx will according to the thickness Dpb and the depth Dimp certainly.

As mentioned above, the angle is θ preferably about 45 degrees in order to shorten the length of the current path for the current passing through a portion of the n ⁺ -type SiC substrate 10 of the JFET region 16 flows away in plan view and around the side portion SS1 of the semiconductor region 24 n-type is going to be in the JFET area 16 to flow while the semiconductor field 24 of the n-type. When the angle θ is set to 45 degrees, consequently, the above expression (1) is rewritten as follows: $$\text{Dimp}\le \text{Dx}\times \text{tan}45°+\text{Dpb}$$

As in 21 next, the resist pattern is shown RP5 in the active area AR1 subjected to isotropic etching to one opening width WP5 every opening OP5 to widen (step S34 in 19th ). That is, the opening widths WP5 of the openings OP5 are enlarged. In the example of 21 will when the opening width WP5 every opening OP5 in the active area AR1 is broadened, including the resist pattern RP51 in the graduation area AR2 subjected to isotropic etching to one opening width WP51 every opening OP51 to widen. That is, if the opening widths WP5 are widened, the opening widths WP51 also enlarged.

As in 21 then the same step as step S24 in FIG 4th repeated for the first embodiment to remove the inert elements such. B. helium (He) or argon (Ar) in the epitaxial layer 12th of the n ^- type (step S35 in FIG 19th ).

The above step implants the inert elements in a portion of the epitaxial layer 12th of the n ^- type, which is above the semiconductor region 25th is of the n ^- type. This creates a semiconductor area 26th of the n ^- -type with crystal defects such as e.g. B. the point defects formed therein PD1 , making the semiconductor area 24 of the n ^- type, that of the semiconductor region 25th of the n ^- type and the semiconductor region 26th of the n ^- type. The concentration of inert elements in the semiconductor area 24 of the n ^- type is higher than the concentration of the inert elements in the upper layer of the epitaxial layer 12th of the n ^- type adjacent to the body area 13th p-type.

In the example of 21 when the inert elements are in the active area AR1 are implanted, the inert elements such. B. helium (He) or argon (Ar) also in the epitaxial layer 12th of the n ^- type in the termination area AR2 implanted.

The above step implants the inert elements in a portion of the epitaxial layer 12th of the n ^- type, which is above the semiconductor region 25a n ^- type is what is a semiconductor region 26a of the n ^- -type with crystal defects such as e.g. B. the point defects formed therein PD1 generated. This creates the semiconductor area 24a of the n ^- type, which is derived from the semiconductor area 25a of the n ^- type and the semiconductor region 26a of the n ^- type. The concentration of inert elements in the semiconductor area 24a of the n ^- type is higher than the concentration of the inert elements in the upper layer of the epitaxial layer 12th of the n ^- type adjacent to the body area 13th p-type in the active area AR1 .

The opening width WP5 in step S35 is wider than the opening width WP5 in step S33. Hence the distance Dx shorter than the distance in step S35 Dx in step S33. Hence the depth becomes Dimp made smaller than the depth in step S35 Dimp in step S33 so that the above expression (1) or (2) is satisfied.

Steps S33 and S35 involve repeatedly implanting the inert elements by the distance Dx and the depth Dimp in a manner that satisfies the above expression (1) or (2). This forms the semiconductor area 24 of the n ^- -type in such a way that the lower end LE1 of the side section SS1 is arranged on the opposite side of the side section SS2 in plan view, the upper end UE1 of the side section SS1 is inserted therebetween.

For example, steps S34 and S35 can be alternately repeated many times in order to implant the inert elements by the distance Dx and the depth Dimp gradually decrease in a manner that satisfies the above expression (1) or (2). This inclines the side portion SS1 of the semiconductor region 24 of the n ^- type in such a way that the lower end LE1 of the side section SS1 is arranged on the opposite side of the side section SS2 in plan view, the upper end UE1 of the side section SS1 is inserted therebetween.

The resist pattern RP5 in the active area AR1 is next subjected to isotropic etching to the opening width WP5 every opening OP5 to widen, as in 22nd shown (step S36 in 19th ). That is, the opening widths WP5 of the openings OP5 are enlarged. In the example of 22nd will when the opening width WP5 every opening OP5 in the active area AR1 is broadened, including the resist pattern RP51 in the graduation area AR2 subjected to isotropic etching to the opening width WP51 every opening OP51 to widen. That is, at the time when the opening widths WP5 are widened, the opening widths WP51 also enlarged.

As in 22nd then the p-type impurities such as B. aluminum (Al) or boron (B) in an upper layer of the epitaxial layer 12th of the n ^- type, which are above the semiconductor region 24 of the n ^- type in the active area AR1 is implanted using the ion implantation technique, which the resist pattern RP5 used as a mask (step S37 in 19th ). This forms the body area 13th p-type in the upper layer of the epitaxial layer 12th of the n ^- type, which are above the semiconductor region 24 is of the n ^- type.

At this point is the width WD1 of Section of the epitaxial layer 12th of the n ^- -type between two adjacent semiconductor layers 24 of the n ^- type is inserted, wider than the width WD2 of the portion of the epitaxial layer 12th of the n ^- type, between two adjacent body areas 13th p-type is inserted. The width WD11 of the portion of the epitaxial layer 12th of the n ^- type, which is between the lower ends LE1 of the side sections SS1 of two adjacent semiconductor layers 24 of the n ^- type is inserted is also wider than the width WD12 of the portion of the epitaxial layer 12th of the n ^- type, which is between the upper ends UE1 of the side portions SS1 of these two adjacent semiconductor layers 24 of the n ^- type is inserted.

In the example of 22nd when the p-type impurities are in the active region AR1 are implanted, the p-type impurities such. B. aluminum (Al) or boron (B) also in an upper layer of the epitaxial layer 12th of the n ^- type, which are above the semiconductor region 24 of the n ^- type in the termination area AR2 is implanted using the ion implantation technique, which the resist pattern RP5 used as a mask. This forms the body area 13a p-type in the upper layer of the epitaxial layer 12th of the n ^- type, which are above the semiconductor region 24a is of the n ^- type.

Alternatively, the step of forming the body region 13a p-type separate from the step of forming the body region 13th of the p-type.

As another alternative, step S33 can be followed by step S36, steps S34 and S35 being skipped. These steps by themselves, when performed, still form the body area 13th p-type and the semiconductor layer 24 of the n ^- -type in such a way that the side section SS1 in plan view is on the opposite side of the JFET area 16 is arranged (see 18th ) with the side section SS2 interposed therebetween.

Thereafter, as in the process for manufacturing the semiconductor device of the first embodiment, steps S15 to S20 in FIG 3 performed to the semiconductor device 1 of the second embodiment.

<Power module, power converter and motor system>

A power module, a power converter, and a motor system each including the semiconductor device 1 of the second embodiment can each have the semiconductor device in the same manner as the power module, the power converter and the motor system 1 of the first embodiment described above using 16 has been discussed.

<Main Features and Effects of This Embodiment>

The semiconductor device 1 the second embodiment has substantially the same features as those of the semiconductor device 1 of the first embodiment. It follows that the semiconductor device 1 of the second embodiment also has substantially the same effects as the semiconductor device 1 the first embodiment offers.

In the second embodiment, the side section SS1 is the epitaxial layer 24 n ^- -type in plan view on the opposite side of the JFET area 16 arranged, the side section SS2 of the body area 13th p-type is interposed therebetween. Consequently it is in the area of the epitaxial layer 12th of the n ^- type, which is below the JFET area 16 is arranged, the flat surface of the portion where the concentration of the inert elements is lower than in the semiconductor region 24 of the n ^- type, made wider than the flat surface in the area of the JFET area 16 . This in turn reduces the on-resistance of each vertical MISFET.

Third embodiment

<Power module, power converter and three-phase motor system>

A description will be given below of a power module, a power converter, and a three-phase motor system having the power converter, each of which is implemented as a third embodiment of the present invention. The power module of the third embodiment includes the semiconductor device of the first embodiment. In contrast to the power module of the first embodiment, the power module of the third embodiment is implemented by applying the semiconductor device of the first embodiment to a three-phase inverter circuit. In the following description, the semiconductor device of the first embodiment may be replaced with the semiconductor device of the second embodiment (the same applies to the fourth and fifth embodiments below).

23 Fig. 13 is a schematic view showing a structure of a three-phase motor system as a third embodiment of the present invention.

As in 23 shown comprises a three phase motor system 30a a power converter 31a acting as an inverter device, a load 32a , typically formed by a three-phase motor, is a DC power source 33 and a capacity 34 such as B. a capacitor. The power converter 31a includes a power module 35a , which is a three-phase Inverter circuit acts, and a control circuit 36a . Weight 32a is with three-phase output terminals TO1, TO2 and TO3 of the power module 35a tied together. The DC power source 33 and the capacity 34 are between two input terminals TI1 and TI2 of the power module 35a connected in parallel with each other.

The power module 35a , which acts as an inverter circuit, includes switching elements 37u , 37v , 37w , 37x , 37y and 37z . The switching elements 37u and 37x are between the input terminals TI1 and TI2 connected in series. The switching elements 37v and 37y are between the input terminals TI1 and TI2 connected in series. The switching elements 37w and 37z are between the input terminals TI1 and TI2 connected in series.

Each of the switching elements 37u , 37v , 37w , 37x , 37y and 37z includes a MISFET 38 and a body diode 39 . The semiconductor device 1 the first or the second embodiment (see 2 or 18th ) can be used as any of the switching elements 37u , 37v , 37w , 37x , 37y and 37z be used. The body diode 23 (please refer 2 or 18th ) included in the semiconductor device 1 is included, can also be used as a body diode 39 be used.

The gate electrodes of the MISFETs 38 that are individually in the switching elements 37u , 37v , 37w , 37x , 37y and 37z are included are each with six control connections TC1, TC2, TC3, TC4, TC5 and TC6 of the power module 35a tied together. The control circuit 36a is also connected to control terminals TC1, TC2, TC3, TC4, TC5 and TC6. This means that the control circuit 36 with the gate electrodes of the MISFETs 38 connected individually in the switching elements 37u , 37v , 37w , 37x , 37y and 37z are included. The control circuit 36a controls the switching elements 37u , 37v , 37w , 37x , 37y and 37z at.

The control circuit 36a controls the switching elements 37u , 37v , 37w , 37x , 37y and 37z in such a manner that the on-state and the off-state of each switching element are alternately switched at a predetermined timing. This generates a three-phase alternating voltage of U, V and W phases from a direct voltage, whereby direct current is converted into three-phase alternating current. The three-phase alternating current drives the load 32a at.

<Main Features and Effects of This Embodiment>

The semiconductor device 1 of the first or the second embodiment can be used as any of the switching elements 37u , 37v , 37w , 37x , 37y and 37z of the power module 35a used in the power converter 31a the third embodiment is included.

Accordingly, in the same manner as the first embodiment, forward voltage deterioration is prevented or suppressed in the semiconductor device 1 occurs when a forward current through the body diode 23 in the semiconductor device 1 flows. This reduces the loss of performance that is suffered at the time of power conversion. Since there is no need, synchronous rectification with high accuracy using the control circuit 36a the design tolerance of the power module 35a and the power converter 31a expanded. This leads to improving the performance of the power module 35a and that of the power converter 31a . And since there is no need for additional diodes in a way outside of the body diode 23 to be attached are the power module 35a and the power converter 31a decreased in size.

Fourth embodiment

A vehicle as a fourth embodiment of the present invention will be described below. The vehicle of the fourth embodiment includes the power converter of the third embodiment. Typically the vehicle is a hybrid car or an electric vehicle.

24 Fig. 13 is a schematic view showing a structure of an electric vehicle as a fourth embodiment of the present invention. 25th Fig. 13 is a circuit diagram of a boost converter for use in the vehicle of the fourth embodiment.

As in 24 shown is the vehicle 40 an electric vehicle that has a three phase motor 43 capable of delivering power from and into a drive shaft 42 output and enter those with drive wheels 41a and 41b is coupled to an inverter device 44 to drive the three-phase motor 43 and a battery 45 includes. The vehicle 40 further comprises a boost converter device 48 , a relay 49 and an electronic control unit 50 . The boost converter device 48 is with a power line 46 associated with the inverter device 44 connected, and with a power line 47 that came with the battery 45 connected, connected.

The three-phase motor 43 is a synchronous generator-motor that has a rotor embedded with permanent magnets and a stator around which three-phase coils are wound. The power converter described above in connection with the third embodiment 31a (please refer 23 ) can be used as an inverter device 44 be used.

As in 25th shown is the boost converter device 48 configured to be an inverter device 53 having that with an inductor 51 and a smoothing capacitor 52 connected is. The inverter device 53 is substantially the same as a part of the inverter circuit used in the power module described above in connection with the third embodiment 35a is included. A MISFET 55 and a body diode 56 that are in a switching element 54 in the inverter device 53 are essentially the same as the MISFET 38 and the body diode 39 described above in connection with the third embodiment.

The electronic control unit 50 includes a microprocessor, a memory device and an input / output port. The electronic control unit 50 receives, among other things, signals from sensors that determine the position of the rotor in the three-phase motor 43 detect, and charge and discharge values from the battery 45 . The electronic control unit 50 also outputs signals that the inverter device 44 , the boost converter device 48 and the relay 49 steer.

<Main Features and Effects of This Embodiment>

The power converter 31a the third embodiment (see 23 ) can be used as an inverter device 44 of the vehicle 40 can be used as the fourth embodiment. The semiconductor device 1 the first or the second embodiment (see 2 or 18th ) can be used as any of the switching elements 37u , 37v , 37w , 37x , 37y and 37z be used. The semiconductor device 1 the first or the second embodiment can also be used as a switching element 54 used in the inverter device 53 in the boost converter device 48 of the vehicle 40 is included as a fourth embodiment.

Accordingly, in the same manner as the first embodiment, forward voltage deterioration is prevented or suppressed in the semiconductor device 1 occurs when a forward current through the body diode 23 in the semiconductor device 1 flows. This reduces the loss of performance that is suffered at the time of power conversion. Since there is no need, synchronous rectification with high accuracy using the control circuit 36 the construction tolerance of the power module is to be carried out 35a and the power converter 31a expanded. This leads to improving the performance of the power module 35a and that of the power converter 31a . And since there is no need for additional diodes in a way outside of the body diode 23 to be attached are the power module 35a and the power converter 31a decreased in size.

Because the vehicle 40 The fourth embodiment reduces the power loss suffered during the power conversion performed by the inverter device 44 and the boost converter device 48 is performed as described above, there is no need that the vehicle 40 has a large-sized cooling device. Accordingly, when the cooling device is reduced in size, the inverter device becomes 44 and the boost converter device 48 slightly reduced in cost, size or weight. Consequently, the volume of the propulsion system that the vehicle 40 occupied as an electric vehicle, reduced. This in turn slightly reduces the cost, size, or weight of the vehicle 40 as an electric vehicle. The flexibility in designing the vehicle 40 as an electric vehicle is also being improved, allowing the interior of the vehicle 40 is continued.

The fourth embodiment has been described above using an example in which a vehicle is provided with the power converter 31a of the third embodiment is applied to an electric vehicle. Alternatively, the vehicle can use the power converter 31a of the third embodiment can be applied to a hybrid car that also uses an internal combustion engine. The hybrid car to which the vehicle with the power converter 31a The third embodiment is applied, offers substantially the same effects as the electric vehicle to which the power converter of the third embodiment is applied.

Fifth embodiment

<Railroad vehicle>

A railway vehicle as a fifth embodiment of the present invention will be described below. The railway vehicle of the fifth embodiment includes the power converter of the third embodiment.

26th Fig. 13 is a schematic view showing a structure of a railroad vehicle as a fifth embodiment of the present invention.

As in 26th shown has a railroad vehicle 60 a pantograph 61 that acts as a pantograph, a transformer 62 , a power converter 63 , a burden 64 which is formed by an AC motor and wheels 65 on. The power converter 63 includes a Converter device 66 , a capacity 67 such as B. a capacitor and an inverter device 68 .

The converter device 66 has switching elements 69 and 70. The switching element 69 is arranged on the side of the upper branch, that is to say on the high-voltage side. The switching element 70 is arranged on the side of the lower branch, that is to say on the low-voltage side. In 26th the switching elements 69 and 70 are shown for one of several phases involved.

The inverter device 68 has switching elements 71 and 72. The switching element 71 is arranged on the side of the upper branch, that is to say on the high-voltage side. The switching element 72 is arranged on the side of the lower branch, that is to say on the low-voltage side. In 26th the switching elements 71 and 72 for one of three phases U, V and W are shown.

One end of the primary side of the transformer 62 is with an overhead line 61a over the pantograph 61 tied together. The other end of the primary side of the transformer 62 is with a rail 65a about the wheels 65 tied together. One end of the secondary of the transformer 62 is with a terminal of the side of the upper branch of the converter device 66 on the opposite side of the load 64 tied together. The other end of the secondary of the transformer 62 is connected to a terminal of the lower branch side of the converter device 66 on the opposite side of the load 64 tied together.

A connection of the side of the upper branch of the converter device 66 on the side of the burden 64 is to a terminal of the side of the upper branch of the inverter device 68 on the opposite side of the load 64 tied together. A connection of the side of the lower branch of the inverter device 66 on the side of the burden 64 is connected to a terminal of the lower branch of the inverter device 68 on the opposite side of the load 64 tied together. Furthermore, the capacity 67 intermediate between the terminal of the side of the upper branch of the inverter device 68 on the opposite side of the load 64 on the one hand and the connection of the side of the lower branch of the inverter device 68 on the opposite side of the load 64 on the other hand connected. Although in 26th not shown are three terminals of the output side of the inverter device 68 representing the U, V and W phases with the load 64 tied together.

In the fifth embodiment, the power converter 31a the third embodiment (see 23 ) as an inverter device 68 be used.

The alternating current supplied by the pantograph 61 from the overhead line 61a is removed is through the transformer 62 transformed in voltage before passing through the converter device 66 is converted into the desired direct current. The one through the converter device 66 converted direct current is determined by the capacitance 67 smoothed in tension. The direct current, its voltage through the capacitance 67 is smoothed by the inverter device 68 converted into alternating current. The one by the inverter device 68 converted alternating current becomes a load 64 delivered. Weight 64 , which is fed with the alternating current, drives the wheels 65 to rotate, thereby accelerating the railway vehicle.

<Main Features and Effects of This Embodiment>

The power converter 31a the third embodiment (see 23 ) can be used as an inverter device 68 in the railway vehicle 60 of the fifth embodiment can be used. The semiconductor device 1 the first or the second embodiment (see 2 or 18th ) can be used as any of the switching elements 37u , 37v , 37w , 37x , 37y and 37z that are in the power converter 31a are included.

Accordingly, in the same manner as the first embodiment, forward voltage deterioration is prevented or suppressed in the semiconductor device 1 occurs when a forward current through the body diode 23 in the semiconductor device 1 flows. This reduces the loss of performance that is suffered at the time of power conversion. Since there is no need, synchronous rectification with high accuracy using the control circuit 36 the design tolerance of the power module 35a and the power converter 31a expanded. This leads to improving the performance of the power module 35a and that of the power converter 31a . And since there is no need for additional diodes in a way outside of the body diode 23 to be attached, the power module 35a and the power converter 31a decreased in size.

As the railroad vehicle 60 The fifth embodiment reduces the power loss suffered during the power conversion performed by the inverter device 68 is performed as described above, there is no need for the railway vehicle 60 has a large-sized cooling device. When the cooling device is reduced in size, the inverter device also becomes 68 easily reduced in cost, size or weight. Consequently, the cost of the railway vehicle becomes 60 with the inverter device 68 easy and the energy efficiency of rail operations is improved.

Alternatively, the semiconductor device 1 the first or the second embodiment (see 2 or 18th ) can be used as each of the switching devices 69 and 70 included in the converter device 66 are included. In this case too, the power loss that occurs during power conversion by the converter device becomes 66 is suffered, decreased. This in turn reduces the converter device 66 easy in terms of cost, size or weight. Consequently, the cost of the railway vehicle becomes 60 with the inverter device 68 slightly reduced and the energy efficiency of railway operations is improved.

Industrial applicability

The present invention can be effectively applied to semiconductor devices, power modules, and power converters

List of reference symbols

1

Semiconductor device

10

^{N +} type SiC substrate

10a

upper surface

10b

lower surface

11

Buffer layer

12th

^{N -} -type epitaxial layer

13, 13a

P-type body region

14th

Source area of the n ⁺ type

15th

^{P +} -type body contact area

15a

Contact area

16

JFET area

17th

Canal area

18th

Gate insulation film

18a

Insulation film

19th

Gate electrode

19a

conductive layer

20th

Interlayer insulation film

20a, 20b

Contact hole

21

Source electrode

21a

Contact electrode

22nd

Drain electrode

23, 23a

Body diode

24, 24a, 25, 25a, 26, 26a

^{N -} -type semiconductor region

30th

Engine system

30a

Three-phase motor system

31, 31a

Power converter

32, 32a

load

33

DC power source

34

capacity

35, 35a

Power module

36, 36a

Control circuit

37u, 37v, 37w, 37x, 37y, 37z

Switching element

38

MISFET

39

Body diode

40

vehicle

41a, 41b

drive wheel

42

drive shaft

43

Three phase motor

44

Inverter device

45

battery

46, 47

Power management

48

Boost converter device

49

relay

50

Electronic control unit

51

Inductor

52

Smoothing capacitor

53

Inverter device

54

Switching element

55

MISFET

56

Body diode

60

Railway vehicle

61

pantograph

61a

Overhead line

62

transformer

63

Power converter

64

load

65

wheel

65a

rail

66

Converter device

67

capacity

68

Inverter device

69 to 72

Switching element

AR1

Active area

AR2

Graduation area

CL1

cell

Dimp

depth

Dpb

thickness

Dx

distance

LE1

lower end

OP1, OP11, OP2, OP3

opening

OP4, OP41, OP5, OP51

opening

PD1

Point defect

PR1

section

RF1 to RF5

Resist film

RP1, RP11, RP2, RP3

Resist pattern

RP4, RP41, RP5, RP51

Resist pattern

SS1 to SS3

Side section

TC1 to TC6

Control connection

TI1, TI2

Input connector

TO1 to TO3

Output connector

UE1

top end

WD1, WD11, WD12, WD2

broad

WP5, WP51

Opening width

θ

angle

Claims (14)

A semiconductor device (1) comprising: a semiconductor substrate (10) of a first conductivity type having a first main plane (10a) and a second main plane (10b) on the opposite side of the first main plane (10a); a semiconductor layer (12) of the first conductivity type formed over the first main plane (10a) of the semiconductor substrate (10); a first semiconductor region (13) formed in an upper layer of the semiconductor layer (12), the first semiconductor region (13) having a second conductivity type different from the first conductivity type; a second semiconductor region (14) of the first conductivity type formed in an upper layer of the first semiconductor region (13); a third semiconductor region (15) of the second conductivity type formed in the upper layer of the first semiconductor region (13); a gate electrode (19) formed over an upper surface of a portion of the first semiconductor region (13) sandwiched between the second semiconductor region (14) and the semiconductor layer (12) with a gate insulating film (18) therebetween is inserted; a source electrode (21) formed over the second semiconductor region (14) and over the third semiconductor region (15); a drain electrode (22) formed over the second main plane (10b) of the semiconductor substrate (10); and a fourth semiconductor region (24) of the first conductivity type formed in a portion of the semiconductor layer (12) underlying the first semiconductor region (13); wherein the semiconductor substrate (10), the semiconductor layer (12), the first semiconductor region (13), the second semiconductor region (14), the third semiconductor region (15) and the fourth semiconductor region (24) consist of silicon carbide; wherein the semiconductor layer (12) comprises a first semiconductor section (16) formed from an upper layer of the semiconductor layer adjacent to the first semiconductor region (13); wherein the fourth semiconductor region (24) is doped with elements for forming crystal defects; and wherein either the first semiconductor section (16) is doped with the elements for forming crystal defects in such a manner that the concentration of the elements for forming crystal defects in the first semiconductor section (16) is lower than the concentration of the elements for forming crystal defects in the fourth semiconductor region (24) or the first semiconductor portion (16) is not doped with the elements for forming crystal defects, characterized in that the fourth semiconductor region (24) is in contact with a lower surface of the first semiconductor region (13). Semiconductor device (1) according to Claim 1 , wherein a first side section (SS1) of the fourth semiconductor region (24) lies on the side of the first semiconductor section (16) in a plan view on the opposite side of the first semiconductor section (16), wherein a second side section (SS2) of the first semiconductor region (13 ) is interposed on the side of the first semiconductor section (16). Semiconductor device (1) according to Claim 2 wherein a lower end of the first side portion (SS1) is arranged on the opposite side of the second side portion (SS2) in plan view, with an upper end of the first side portion (SS1) interposed therebetween. Semiconductor device (1) according to Claim 3 wherein the first side portion (SS1) is inclined in such a way that the lower end of the first side portion (SS1) is located on the opposite side of the second side portion (SS2) in plan view, the upper end of the first side portion (SS1 ) is inserted in between. Semiconductor device (1) according to Claim 1 wherein the semiconductor layer (12) is formed in a first region and in a second region over the first main plane (10a) of the semiconductor substrate (10), the second region lying on the outer peripheral side of the first region over the semiconductor substrate (10); wherein the first semiconductor region (13) is formed in an upper layer of the semiconductor layer (12) in the first region; the semiconductor device (1) further comprising: a fifth semiconductor region of the second conductivity type formed in an upper layer of the semiconductor layer (12) in the second region; a sixth semiconductor region of the second conductivity type formed in an upper layer of the fifth semiconductor region; a contact electrode formed over the sixth semiconductor region; and a seventh semiconductor region of the first conductivity type formed in a portion of the semiconductor layer (12) underlying the fifth semiconductor region; wherein the fifth semiconductor region, the sixth semiconductor region and the seventh semiconductor region are made of silicon carbide; wherein the seventh semiconductor region is doped with the elements for forming crystal defects; and wherein either the first semiconductor section (16) is doped with the elements for forming crystal defects in such a manner that the concentration of the elements for forming crystal defects in the first semiconductor section (16) is lower than the concentration of the elements for forming crystal defects in the fourth semiconductor region (24) and the concentration of the elements for forming crystal defects in the seventh semiconductor region, or the first semiconductor section (16) is not doped with the elements for forming crystal defects. Semiconductor device (1) according to Claim 1 wherein the elements for forming crystal defects are helium or argon. Semiconductor device (1) according to Claim 1 wherein the concentration of the elements for forming crystal defects in the fourth semiconductor region (24) is 1 x 1015 to 1 x 1022 cm-3. Power module with the semiconductor device (1) according to Claim 1 . Power converter with the power module Claim 8 . A semiconductor device manufacturing method comprising: (a) a step of forming a semiconductor layer (12) of a first conductivity type over a first main plane (10a) of a semiconductor substrate (10) of the first conductivity type having the first main plane (10a) and a second main plane (10b) on the opposite side of the first main plane (10a); (b) a step of forming a first semiconductor region (13) in an upper layer of the semiconductor layer (12), the first semiconductor region (13) having a second conductivity type different from the first conductivity type; (c) a step of forming a second semiconductor region (14) of the first conductivity type in an upper layer of the first semiconductor region (13); (d) a step of forming a third semiconductor region (15) of the second conductivity type in the upper layer of the first semiconductor region (13); (e) a step of forming a gate electrode (19) over an upper surface of a portion of the first semiconductor region (13) interposed between the second semiconductor region (14) and the semiconductor layer (12), wherein a gate insulating film ( 18) is inserted in between; (f) a step of forming a source electrode (21) over the second semiconductor region (14) and over the third semiconductor region (15); and (g) a step of forming a drain electrode (22) over the second major plane (10b) of the semiconductor substrate (10); wherein step (b) forms a fourth semiconductor region (24) of the first conductivity type in a portion of the semiconductor layer (12) underlying the first semiconductor region (13), the fourth semiconductor region (24) being doped with elements for forming crystal defects; wherein the semiconductor substrate (10), the semiconductor layer (12), the first semiconductor region (13), the second semiconductor region (14), the third semiconductor region (15) and the fourth semiconductor region (24) consist of silicon carbide; and wherein either a first semiconductor portion formed from an upper layer of the semiconductor layer (12) adjacent to the first semiconductor region (13) is doped with the elements for forming crystal defects in such a manner that the concentration of the elements for Formation of crystal defects in the first semiconductor section (16) is lower than the concentration of the elements for forming crystal defects in the fourth semiconductor region (24), or the first semiconductor section (16) is not doped with the elements for forming crystal defects, characterized in that the fourth semiconductor region (24) is in contact with a lower surface of the first semiconductor region (13). Semiconductor device manufacturing method according to Claim 10 wherein step (b) comprises: (h) a step of forming a first film over the semiconductor layer (12); (i) a step of forming openings penetrating the first film to reach the semiconductor layer (12); (j) a step of forming the fourth semiconductor region (24) in the semiconductor layer (12) by implanting the elements for forming crystal defects in a portion of the semiconductor layer (12) exposed through the openings; and (k) after step (j), a step of forming the first semiconductor region (13) in the upper layer of the semiconductor layer (12) overlying the fourth semiconductor region (24) by implanting impurities of the second conductivity type in the portion of the Semiconductor layer (12) exposed through the openings. Semiconductor device manufacturing method according to Claim 11 wherein step (b) further comprises: (I) after step (j) a step of widening an opening width of each of the openings; wherein after step (1), step (k) forms the first semiconductor region (13) by implanting the impurities of the second conductivity type in the portion of the semiconductor layer (12) exposed through the openings; and wherein step (b) forms the fourth semiconductor region (24) in such a manner that a first side portion (SS1) of the fourth semiconductor region (24) on the side of the first semiconductor portion (16) is on the opposite side of the first semiconductor portion in plan view (16) is arranged with a second side portion (SS2) of the first semiconductor region (13) on the side of the first semiconductor portion (16) is interposed therebetween. Semiconductor device manufacturing method according to Claim 12 wherein step (j) comprises: (j1) a step of forming a fifth semiconductor region associated with the elements for forming crystal defects in the semiconductor layer (12) by implanting the elements for forming crystal defects in the portion of the semiconductor layer (12) that is exposed through the openings is doped; and (j2) after step (j1), a step of forming a sixth semiconductor region associated with the elements for forming crystal defects in a portion of the semiconductor layer (12) overlying the fifth semiconductor region by implanting the elements for forming crystal defects in the portion of the semiconductor region exposed through the openings whose opening widths are widened is doped; wherein the step (j) forms the fourth semiconductor region (24) consisting of the fifth semiconductor region and the sixth semiconductor region; and wherein step (b) forms the fourth semiconductor region (24) in such a manner that a lower end of the first side portion (SS1) is on the opposite side of the second side portion (SS2) in plan view, with an upper end of the first Page section (SS1) is inserted in between. Semiconductor device manufacturing method according to Claim 10 wherein step (a) forms the semiconductor layer (12) in a first region and in a second region over the first main plane (10a) of the semiconductor substrate (10), the second region on the outer peripheral side of the first region over the semiconductor substrate ( 10) lies; and wherein step (b) forms the first semiconductor region (13) in the upper layer of the semiconductor layer (12) in the first region; the semiconductor device manufacturing method further comprising: (m) a step of forming a seventh semiconductor region of the second conductivity type in an upper layer of the semiconductor layer (12) in the second region; (n) a step of forming an eighth semiconductor region of the second conductivity type in an upper layer of the seventh semiconductor region; and (o) a step of forming a contact electrode over the eighth semiconductor region; wherein step (m) forms a ninth semiconductor region of the first conductivity type in a portion of the semiconductor layer (12) underlying the seventh semiconductor region, the ninth semiconductor region being doped with the elements for forming crystal defects; wherein the seventh semiconductor region, the eighth semiconductor region, and the ninth semiconductor region are made of silicon carbide; and wherein either the first semiconductor portion (16) is doped with the elements for forming crystal defects in such a manner that the The concentration of the elements for forming crystal defects in the first semiconductor section (16) is lower than the concentration of the elements for forming crystal defects in the fourth semiconductor region (24) and the concentration of the elements for forming crystal defects in the ninth semiconductor region, or the first semiconductor section (16) is not doped with the elements for forming crystal defects.

Images