DE112010001895T5 - High-quality contact structure of a TCO silicon interface for highly efficient thin-film silicon solar cells - Google Patents

Abstract

There is provided a method and apparatus for forming solar cells. In one embodiment, a photovoltaic device includes a first TCO layer disposed on a substrate, a second TCO layer disposed on the first TCO layer, and a p-type silicon-containing layer disposed on the second TCO layer. Layer is formed. In another embodiment, a method of forming a photovoltaic device includes forming a first TCO layer on a substrate, forming a second TCO layer on the first TCO layer, and forming a first pin junction on the second TCO layer ,

Description

BACKGROUND OF THE INVENTION

Field of the invention

Embodiments of the present invention generally relate to solar cells and methods of making the same. In particular, embodiments of the present invention relate to an interface layer (interface layer) formed in thin-film and crystalline solar cells.

Description of the Prior Art

Crystalline silicon solar cells and thin-film solar cells are two types of solar cells. Crystalline silicon solar cells typically use either monocrystalline substrates (i.e., single crystal single crystal substrates) or multicrystalline silicon substrates (i.e., polycrystalline substrates or polysilicon). Additional film layers are deposited on the silicon substrates to improve light detection, to form the electrical circuits, and to protect the devices. Thin-film solar cells use thin layers of material deposited on suitable substrates to form one or more p-n junctions. Suitable substrates include glass, metal and polymer substrates.

To increase the economic benefits of solar cells, the efficiency must be improved. The efficiency of solar cells is related to the proportion of incident radiation that is converted into usable electricity. To be useful for multiple applications, the efficiency of solar cells must be improved beyond the current best performance of about 15%. In view of increasing energy costs, there is a need for improved thin film solar cells and methods and apparatus for making same in an industrial environment.

The above-mentioned problems of the prior art are solved by devices according to the invention according to claims 1 and 8 and a method according to the invention according to claim 12.

BRIEF SUMMARY OF THE INVENTION

Embodiments of the invention provide methods of manufacturing solar cells. Some embodiments provide a method for making an interface layer between a transparent conductive oxide (TCO) layer and a solar cell junction. In one embodiment, a photovoltaic device includes a first TCO layer disposed on a substrate, a second TCO layer disposed on the first TCO layer, and a p-type silicon-containing layer disposed on the second TCO layer. Layer is formed.

In another embodiment, a photovoltaic device includes a TCO layer disposed on a substrate, an interface layer disposed on the TCO layer, the interface layer being a p-type silicon-containing layer comprising carbon, and a p Silicon-containing layer disposed on the interface layer.

In yet another embodiment, a method of forming a photovoltaic device includes forming a first TCO layer on a substrate, forming a second TCO layer on the first TCO layer, and forming a first pin junction on the second TCO layer. Layer.

Preferred embodiments and particular aspects of the invention will become apparent from the dependent claims.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that the manner in which the above-mentioned features of the present invention are achieved will be understood in detail, a detailed description of the invention briefly presented above will be given with reference to the embodiments thereof shown in the accompanying drawings.

1 shows a schematic side view of a tandem junction thin-film solar cell according to an embodiment of the invention;

2 shows a schematic side view of a tandem junction thin-film solar cell with an interface layer disposed between a TCO layer and a cell junction, according to an embodiment of the invention;

3 - 10 show schematic side views of a tandem junction thin film solar cell with an interface layer disposed between a TCO layer and a cell junction, according to an embodiment of the invention;

11 shows a sectional view of a device according to an embodiment of the invention;

12 is a plan view of a device according to another embodiment of the invention; and

13 FIG. 10 is a plan view of a portion of a production line with integrated devices thereof. FIG 11 and 12 according to an embodiment of the invention.

To facilitate understanding, identical reference numerals have been used as far as possible to designate identical elements that are common to the figures. It is conceivable that elements and features of one embodiment may be advantageously incorporated into other embodiments without being mentioned again.

It is to be noted, however, that the appended drawings illustrate only exemplary embodiments of this invention and, therefore, are not to be considered as limiting the scope thereof, for the invention may admit to other equally effective embodiments.

DETAILED DESCRIPTION

Thin-film solar cells are generally made up of numerous types of films or layers that are joined together in many different ways. Most of the films used in such devices contain a semiconductor element which may include silicon, germanium, carbon, boron, phosphorus, nitrogen, oxygen, hydrogen, and the like. The characteristics of the various films include degrees of crystallinity, type of dopant, dopant concentration, refractive index of the film, extinction coefficient of the film, film transparency, film absorption, and conductivity. Most of these films can be made by employing a chemical vapor deposition method which may have some degree of ionization or plasma formation.

Charge generation during a photovoltaic process is generally provided by a bulk semiconductor layer, such as a silicon-containing layer. The bulk layer is sometimes called an "intrinsic layer" to distinguish it from the various doped layers present in the solar cell. The intrinsic layer may have any desired degree of crystallinity which influences its light absorbing properties. For example, an amorphous intrinsic layer, such as amorphous silicon, generally absorbs light at other wavelengths, such as intrinsic layers with other degrees of crystallinity, such as microcrystalline or nanocrystalline silicon. For this reason, it is advantageous to use both types of layers in order to produce the broadest possible spectrum of absorption properties.

Silicon and other semiconductors can be formed into solids having different degrees of crystallinity. Solids that have substantially no crystallinity are amorphous and silicon of negligible crystallinity is called amorphous silicon. Fully crystalline silicon is referred to as crystalline, polycrystalline or monocrystalline silicon. Polycrystalline silicon is crystalline silicon which has numerous crystal grains separated by grain boundaries. Monocrystalline silicon is a single crystal of silicon. Solids having a partial crystallinity, that is, a crystal content ranging from about 5% to about 95%, are referred to as nanocrystalline or microcrystalline, which generally refers to the size of the crystal grains suspended in an amorphous phase. Solids with larger crystal grains are called microcrystalline, while those with smaller crystal grains are nanocrystalline. It should be noted that the term "crystalline silicon " may refer to any form of silicon having a crystal phase, including microcrystalline and nanocrystalline silicon.

1 is a schematic representation of an embodiment of a solar cell with multiple transitions (multi-junction solar cell) 100 on a light or solar radiation 101 is aligned. The solar cell 100 contains a substrate 102 , Typically, a first transparent conductive oxide layer (TCO layer) 104 is above the substrate 102 formed, a first pin transition 122 is above the first TCO layer 104 educated. A second pin transition 124 is over the first pin transition 122 formed, a second TCO layer 118 is over the second pin transition 124 formed, and a metallic backing layer 120 is above the second TCO layer 118 educated. The substrate 102 may be a glass substrate, polymer substrate, metal substrate, or other suitable substrate with thin films formed thereover.

The first TCO layer 104 and the second TCO layer 118 may each comprise tin oxide, zinc oxide, indium tin oxide, cadmium stannate, combinations thereof, or other suitable materials. Of course, the TCO materials may also contain additional dopants and components. For example, zinc oxide may further contain dopants, such as tin, aluminum, gallium, boron, and other suitable dopants. In one embodiment, zinc oxide comprises 5 atomic% or less dopants, and more preferably comprises 2.5 atomic% or less of aluminum. In some cases, the substrate may 102 from the glass manufacturers with the first TCO coating already deposited on them 104 to be delivered.

In order to improve the light absorption by improving the light trapping (light trapping), the substrate can 102 and / or one or more. the thin films formed above may optionally be structured by wet, plasma, ion and / or other mechanical methods. For example, at the in 1 illustrated embodiment, the first TCO layer 104 sufficiently structured so that the topography of the surface is essentially transferred to the subsequent thin films deposited over it.

According to embodiments, the first pin transition 122 a p-silicon-containing layer 106 , an intrinsic silicon-containing layer 108 that over the p-silicon-containing layer 106 is formed, and a n-silicon-containing layer 110 that over the intrinsic silicon-containing layer 108 is formed include. In certain embodiments, the p-type silicon-containing layer is an amorphous p-type silicon layer 106 with a thickness between about 60 Å and about 300 Å. In certain embodiments, the intrinsic silicon-containing layer is 108 an amorphous intrinsic silicon layer having a thickness of between about 1,500 Å and about 3,500 Å. In certain embodiments, the n-type silicon-containing layer is a n-type microcrystalline silicon layer that may be formed to a thickness of between about 100 Å and about 400 Å.

According to embodiments, the second pin transition 124 a p-silicon-containing layer 112 , an intrinsic silicon-containing layer 114 that over the p-silicon-containing layer 112 is formed, and a n-silicon-containing layer 116 that over the intrinsic silicon-containing layer 114 is formed include. In certain embodiments, the p-type silicon containing layer 112 a microcrystalline p-type silicon layer 112 with a thickness between about 100 Å and about 400 Å. In certain embodiments, the intrinsic silicon-containing layer is 114 a microcrystalline intrinsic silicon layer having a thickness between about 10,000 Å and about 30,000 Å. In certain embodiments, the n-silicon containing layer is 116 an amorphous silicon layer having a thickness of between about 100 Å and about 500 Å.

The metallic backing layer 120 may include, among others, a material selected from the group consisting of Al, Ag, Ti, Cr, Au, Cu, Pt, alloys thereof, and combinations thereof. Other processes may be performed to form the solar cell, such as laser scribing processes. There may be other films, materials, substrates, and / or packaging over the metallic backing layer 120 be provided to complete the solar cell device. The formed solar cells can be connected together to form modules, which in turn can be connected to form arrays.

solar radiation 101 is primarily of the intrinsic layers 108 . 114 the pin transitions 122 . 124 is absorbed and converted into electron-hole pairs. That between the p-layer 106 . 112 and the n-layer 110 . 116 generated electric field which spreads over the intrinsic layer 108 . 114 extends, causing electrons in the direction of the n-layers 110 . 116 flow and holes in the direction of the p-layers 106 . 112 flow, creating a current. The first pin transition 122 can be an intrinsic amorphous silicon layer 108 include, and the second pin transition 124 can be an intrinsic microcrystalline silicon layer 114 to take advantage of the properties of amorphous silicon and microcrystalline silicon, which have different wavelengths of solar radiation 101 absorb. Therefore, the formed solar cell 100 more efficient as it captures a larger fraction of the spectrum of solar radiation. The intrinsic layer 108 . 114 of amorphous silicon and the intrinsic layer of microcrystalline silicon are stacked in such a way that the solar radiation 101 first on the intrinsic amorphous silicon layer 108 and then the intrinsic microcrystalline silicon layer 114 because amorphous silicon has a larger bandgap than microcrystalline silicon. Solar radiation, which is not from the first pin junction 122 is absorbed, becomes the second pin junction 124 transfer.

In an embodiment wherein the intrinsic silicon-containing layer 108 is an intrinsic amorphous silicon layer, the intrinsic amorphous silicon layer may be 108 are deposited by supplying a gas mixture of hydrogen gas and silane gas having a volume flow ratio of about 20: 1 or less. Silane gas can be supplied at a flow rate between about 0.5 sccm / l and about 7 sccm / l. Hydrogen gas may be supplied at a flow rate between about 5 sccm / l and 60 sccm / l. The showerhead, for example, RF energy between 15 mW / cm ² and about 250 mW / cm ^{2 are} supplied. The pressure of the chamber may be maintained between about 0.1 Torr and 20 Torr, such as between about 0.5 Torr and about 5 Torr. The deposition rate of the intrinsic amorphous silicon layer 108 is then about 100 Å / min or more. In an exemplary embodiment, the intrinsic amorphous silicon layer becomes 108 at a volumetric flow ratio of hydrogen to silane of about 12.5: 1.

In embodiments where the intrinsic silicon-containing layer 114 is an intrinsic microcrystalline silicon layer, the intrinsic amorphous silicon layer can 114 depositing a gas mixture of silane gas and hydrogen gas in a volume flow ratio of hydrogen to silane between about 20: 1 and about 200: 1. Silane gas can be supplied at a flow rate between about 0.5 sccm / l and about 5 sccm / l. Hydrogen gas may be supplied at a flow rate between about 40 sccm / l and about 400 sccm / l. In certain embodiments, the flow rate of silane during deposition may be ramped from a first flow rate to a second flow rate. In certain embodiments, the flow rate of hydrogen during deposition may be ramped down from a first flow rate to a second flow rate. The supply of RF energy of about 300 mW / cm ² or more, such as 600 mW / cm ² or more, at a chamber pressure between about 1 Torr and about 100 Torr, such as between about 3 Torr and about 20 Torr or between about 4 Torr and about 12 Torr, generally causes the deposition of an intrinsic microcrystalline silicon layer having a crystalline fraction between about 20 percent and about 80 percent, such as between 55 percent and about 75 percent, at a rate of about 200 Å / min or more, such as about 500 Å / min. In some embodiments, it may be advantageous to ramp the power density of the supplied RF energy during deposition from a first power density to a second power density.

In another embodiment, the intrinsic microcrystalline silicon layer 114 are deposited in several steps, wherein the deposited during the individual steps portions of the layer have different hydrogen dilution ratios, which can provide different crystal fractions of the deposited thin films. For example, in one embodiment, the volume flow ratio of hydrogen to silane may be reduced in four steps from 100: 1 to 95: 1, to 90: 1, and then to 85: 1. In one embodiment, silane gas may be supplied at a flow rate between about 0.1 sccm / l and about 5 sccm / l, such as about 0.97 sccm / l. Hydrogen gas may be supplied at a flow rate between about 10 sccm / l and about 200 sccm / l, such as between about 80 sccm / l and about 105 sccm / l. In an exemplary embodiment in which the deposition process has multiple steps, such as four steps, the flow rate of the hydrogen gas may begin at about 97 sccm / l in the first step and gradually in the subsequent process steps to about 92 sccm / l, 88 sccm / l or 83 sccm / l can be reduced. The supply of RF energy of about 300 mW / cm ² or more, such as about 490 mW / cm ² , at a chamber pressure between about 1 Torr and about 100 Torr, such as between about 3 Torr and about 20 Torr For example, such as between about 4 Torr and about 12 Torr, such as about 9 Torr, deposition of an intrinsic microcrystalline silicon layer will occur at a rate of about 200 Åmin or greater, such as 400 Åmin.

Charge accumulation generally occurs through doped semiconductor layers, such as silicon layers doped with p or n dopants. P-type dopants are generally Group III elements, such as boron or aluminum. N-type dopants are generally Group V elements such as phosphorus, arsenic or antimony. In most embodiments, boron is used as the p-type dopant and phosphorus as the n-type dopant. These dopants can be added to the p and n layers described above 106 . 110 . 112 . 116 be added by boron-containing or phosphorus-containing compounds are added to the reaction mixture. Suitable boron and phosphorus compounds generally include substituted and unsubstituted lower borane and phosphine oligomers. Some suitable boron compounds include trimethylboron (B (CH ₃ ) ₃ or TMB), diborane (B ₂ H ₆ ), boron trifluoride (BF ₃ ) and triethylboron (B (C ₂ H ₅ ) ₃ or TEB). Phosphine is the most common phosphorus compound. The dopants are generally supplied with a carrier gas, such as hydrogen, helium, argon or other suitable gas. When hydrogen is used as the carrier gas, the total content of hydrogen in the reaction mixture increases. The abovementioned hydrogen components therefore also contain the amount of hydrogen which is contributed by the carrier gas used for the supply of the dopants.

Dopants are generally supplied as a dilating agent in an inert gas or carrier gas. For example, dopants having molar concentrations or volume concentrations of about 0.5% may be supplied in a carrier gas. When a dopant having a volume concentration of about 0.5% is supplied in a carrier gas flowing at 1.0 sccm / l, the resulting flow rate of the dopant is 0.005 sccm / l. Dopants may be fed to a reaction chamber at flow rates between about 0.0002 sccm / l and about 0.1 sccm / l, depending on the desired degree of doping. In general, the concentration of the dopant between about 1018 atoms / cm ³ and about 10 ²⁰ atoms / cm ³ held.

In an embodiment wherein the p-type silicon containing layer 112 is a microcrystalline p-type silicon layer, the microcrystalline p-type silicon layer 112 by adding a gas mixture of hydrogen gas and silane gas having a volumetric flow ratio of hydrogen to silane of about 200: 1 or greater, such as 1000: 1 or less, for example between about 250: 1 and about 800: 1, and in one another example of about 601: 1 or about 401: 1. Silane gas may be supplied at a flow rate between about 0.1 sccm / l and about 0.8 sccm / l, such as between about 0.2 sccm / l and about 0.38 sccm / l. Hydrogen gas may be supplied at a flow rate between about 60 sccm / l and about 500 sccm / l, such as about 143 sccm / l. TMB may be supplied at a flow rate between about 0.0002 sccm / l and about 0.0016 sccm / l, such as about 0.00115 sccm / l. If TMB is supplied in a molar concentration or volume concentration of 0.5% in a carrier gas, the dopant-carrier gas mixture may flow at a flow rate between about 0.04 sccm / l and about 0.32 sccm / l, such as 0, 23 sccm / l. The supply of RF energy is between about 50 mW / cm ² and about 700 mW / cm ² , such as between about 290 mW / cm ² and about 440 mW / cm ² , at a chamber pressure between about 1 Torr and about 100 Torr such as between about 3 torr and about 20 torr, between 4 torr and about 12 torr or about 7 torr or about 9 torr, the deposition of a microcrystalline p-layer having a crystalline fraction between about 20 percent and about 80 percent, such as between 50 percent and about 70 percent for a microcrystalline layer, at a rate of about 10 Å / min or greater, such as about 143 Åmin or greater.

In an embodiment wherein the p-type silicon containing layer 106 is an amorphous p-type silicon layer, the amorphous p-type silicon layer 106 may be deposited by supplying a mixed gas of hydrogen gas and silane gas at a volumetric flow ratio of about 20: 1 or less. Silane gas can be supplied at a flow rate between about 1 sccm / l and about 10 sccm / l. Hydrogen gas may be supplied at a flow rate between about 5 sccm / l and about 60 sccm / l. Trimethylboron may be supplied at a flow rate between about 0.005 sccm / l and about 0.05 sccm / l. If trimethylboron is supplied in a molar concentration or volume concentration of 0.5% in a carrier gas, the dopant-carrier gas mixture may be supplied at a flow rate between about 1 sccm / l and about 10 sccm / l. The application of RF energy between about 15 mW / cm ² and about 200 mW / cm ² at a chamber pressure between about 0.1 torr and 20 torr, such as between about 1 torr and about 4 torr, becomes the deposition of an amorphous p-type silicon layer at a rate of about 100 Åmin or more. The addition of methane or other carbon containing compounds such as CH ₄ , C ₃ H ₈ , C ₄ H ₁₀ or C ₂ H ₂ can be used to form a carbon-containing amorphous p-type silicon layer 106 which absorbs less light than other silicon-containing materials. In other words, in the configuration where the formed amorphous p-type silicon layer 106 Containing alloying elements such as carbon, the formed layer then has improved light transmission properties, or windowing properties (eg, to reduce the absorption of solar radiation). The extra amount of solar radiation passing through the amorphous p-type silicon layer 106 is allowed to be absorbed by the intrinsic layers, thereby increasing the efficiency of the solar cell. In the embodiment wherein trimethylboron is used to form boron dopants in the amorphous p-type silicon layer 106 The concentration of boron dopants is maintained between about 1 × 10 ¹⁸ atoms / cm ² and about 1 × 10 ²⁰ atoms / cm ² . In an embodiment wherein methane gas is added and used to form a carbon-containing amorphous p-type silicon layer 106 The carbon concentration in the carbon-containing amorphous p-type silicon layer is controlled to be between about 10 atomic% and about 20 atomic%. In one embodiment, the amorphous p-type silicon layer 106 a thickness between about 20 Å and about 300 Å, such as between about 80 Å and about 200 Å.

In an embodiment in which the n-silicon-containing layer 110 is a microcrystalline n-type silicon layer, the microcrystalline n-type silicon layer 110 by adding a gas mixture of hydrogen gas and silane gas having a volumetric flow ratio of about 100: 1 or more, such as about 500: 1 or less, such as between about 150: 1 and about 400: 1, for example, about 304 : 1 or about 203: 1, is supplied. Silane gas may flow at a flow rate between about 0.1 sccm / l and about 0.8 sccm / l, such as between about 0.32 sccm / l and about 0.45 sccm / l, for example, about 0.35 sccm / l, are supplied. Hydrogen gas may be supplied at a flow rate between about 30 sccm / l and about 250 sccm / l, such as between about 68 sccm / l and about 143 sccm / l, for example, of about 71.43 sccm / l. Phosphine can be at a flow rate between about 0.0005 sccm / l and about 0.006 sccm / l, such as between about 0.0025 sccm / l and about 0.015 sccm / l, for example, of about 0.005 sccm / l. In other words, if phosphine is supplied in a molar concentration or volume concentration of 0.5% in a carrier gas, the dopant-carrier gas mixture may flow at a flow rate between about 0.1 sccm / l and about 5 sccm / l, such as between about 0.5 sccm / l and about 3 sccm / l, for example between about 0.9 sccm / l and about 1.088 sccm / l. A supply of RF energy between about 100 mW / cm ² and about 900 mW / cm ² , such as from about 370 mW / cm ² , at a chamber pressure between about 1 Torr and about 100 Torr, such as between about 3 Torr and about 20 torr, more preferably between 4 torr and about 12 torr, for example about 6 torr or about 9 torr, the deposition of a n-type microcrystalline silicon layer having a crystalline fraction between about 20 percent and about 80 percent, as for Example between 50 percent and about 70 percent, at a rate of about 50 amine or more, such as effect of about 150 Åmin or more.

In an embodiment in which the n-silicon-containing layer 116 is an amorphous n-type silicon layer, the amorphous n-type silicon layer 116 may be deposited by mixing a mixed gas of hydrogen gas and silane gas at a volumetric flow ratio of about 20: 1 or less, such as about 5.5: 1 or 7.8: 1, is supplied. Silane gas may be at a flow rate between about 0.1 sccm / l and about 10 sccm / l, such as between about 1 sccm / l and about 10 sccm / l, between about 0.1 sccm / l and 5 sccm / l or between about 0.5 sccm / l and about 3 sccm / l, for example, about 1.42 sccm / l or 5.5 sccm / l. Hydrogen gas may flow at a flow rate between about 1 sccm / l and about 40 sccm / l, such as between about 4 sccm / l and about 40 sccm / l, or between about 1 sccm / l and about 10 sccm / l, for example about 6.42 sccm / l or about 27 sccm / l. Phosphine can flow at a flow rate between about 0.0005 sccm / l and about 0.075 sccm / l, such as between about 0.0005 sccm / l and about 0.0015 sccm / l, or between about 0.015 sccm / l and about 0, 03 sccm / l, for example, from about 0.0095 sccm / l or about 0.023 sccm / l. If phosphine is supplied in a molar concentration or volume concentration of 0.5% in a carrier gas, the dopant-carrier gas mixture may flow at a flow rate between about 0.1 sccm / l and about 15 sccm / l, such as between about 0 , 1 sccm / l and about 3 sccm / l, between about 2 sccm / l and about 15 sccm / l or between about 3 sccm / l and about 6 sccm / l, for example about 1.9 sccm / l or about 4.71 sccm / l. The supply of RF energy between about 25 mW / cm ² and about 250 mW / cm ² , such as from about 60 mW / cm ² or about 80 mW / cm ² , at a chamber pressure between about 0.1 Torr and about 20 Torr, such as between about 0.5 Torr and about 4 Torr, or about 1.5 Torr, becomes the deposition of an amorphous n-type silicon layer at a rate of about 100 Å / min or more, such as about 200 Or more, such as from about 300 Å / min or about 600 Å / min.

In some embodiments, alloys of silicon with other elements such as oxygen, carbon, nitrogen, hydrogen, and germanium may be useful. These other elements can be added to silicon films by adding sources of the respective elements to the mixture of reaction gases. Alloys of silicon may be used in any type of silicon layers, including interfacial layers, p-type layers, n-type layers, PIB (pi-buffer) layers, wavelength selective reflector layers (WSR layers), or silicon layers of the intrinsic type. For example, carbon may be added to the silicon films by adding a carbon source such as methane (CH ₄ ) to the gas mixture. In general, most C ₁ -C ₄ hydrocarbons can be used as carbon sources. Alternatively, organosilicon compounds such as organosilanes, organosiloxanes, organosilanols, and the like can serve as both silicon and carbon sources. Germanium compounds, such as germanium and organogermane, may serve as germanium sources in addition to silicon and germanium containing compounds, such as silyl germanes or germyl silanes. Oxygen gas (O ₂ ) can serve as an oxygen source. Other oxygen sources include oxides of nitrogen (nitrous oxide - N ₂ O, nitric oxide - NO, dinitrogen trioxide - N ₂ O ₃ , nitrogen dioxide - NO ₂ , dinitrogen tetroxide - N ₂ O ₄ , dinitrogen pentoxide - N ₂ O ₅ and nitrogen trioxide - NO ₃ ) , Hydrogen peroxide (H ₂ O ₂ ), carbon monoxide or dioxide (CO or CO ₂ ), ozone (O ₃ ), oxygen atoms, oxygen radicals and alcohols (ROH, where R is any organic or heteroorganic radical group). Nitrogen sources may include nitrogen gas (N ₂ ), ammonia (NH ₃ ), hydrazine (N ₂ H ₂ ), amines (R _x NR ' _3-x , where x is 0 to 3, and R and R' are each independently one are any organic or heteroorganic radical group), amides ((RCO) _x NR ' _3-x , where x is 0 to 3 and R and R' are each independently any organic or heteroorganic radical group), imides (RCONCOR ', where R and R 'independently of one another are each an organic or heteroorganic radical group), enamines (R ₁ R ₂ C =CR ₃ NR ₄ R ₅ , wherein R ₁ -R ₅ independently of one another are each an organic or heteroorganic radical group) and nitrogen atoms and be radical.

In order to increase the conversion efficiency and reduce the contact resistance, an interface layer may be formed at the interface of the TCO layer 104 and the p-type silicon-containing layer 106 be formed. 2 shows an example of an interface layer 202 that exist between the TCO layer 104 and the p-type silicon-containing layer 106 is arranged. The interface layer 202 provides a good interface that can improve the adhesion between the films formed thereon and the TCO substrate. In some embodiments, the interface layer 202 may be a highly doped or degeneratively doped silicon-containing layer formed by delivering doping compounds at high rates, for example, at speeds in the upper range of the formulations described above. It is believed that degenerative doping improves charge collection by providing low resistance contact junctions. It is also believed that degenerative doping improves the conductivity of some layers, such as amorphous layers.

In one embodiment, the interface layer is 202 a degeneratively doped p-type amorphous silicon layer (a highly doped p-type amorphous silicon layer, p ++ silicon layer). The degenerative (eg high) doped amorphous p ++ silicon layer 202 has a higher doping concentration of Group III elements than the p-type silicon containing layer 106 , The degenerative (eg high) doped amorphous p ++ silicon layer 202 has a doping concentration equivalent to a layer formed using TMB and silane at a volumetric flow ratio of the mixture of between about 2: 1 and about 6: 1 at a pressure between about 2 and about 2.5 torr, the precursor of TMB comprises a molar concentration or volume concentration of TMB of about 0.5%. The degenerative (eg high) doped amorphous p ++ silicon layer 202 is formed at a plasma power of between about 45 milliwatts / cm ² (2400 watts) and about 91 milliwatts / cm ² (4800 watts). In one example, the degeneratively doped amorphous p ++ silicon layer 202 Formed by adding silane at a flow rate between about 2.1 sccm / l (eg 6000 sccm) and about 3.1 sccm / l (eg 9000 sccm), hydrogen gas at such a flow rate that the mixing ratio from hydrogen gas to silane gas is about 6.0, and a dopant precursor having a volume flow ratio of the mixture of TMB gas (eg, molar concentration or volume concentration of TMB of about 0.5%) to silane gas of 6: 1 is supplied during the substrate support temperature is maintained at about 200 ° C, the plasma power is controlled to be about 57 milliwatts / cm ² (3287 watts), and the chamber pressure is maintained at about 2.5 torr for about 2-10 seconds to form a film of about 10-50 Å, such as a film of 20 Å. In one embodiment, the highly doped amorphous silicon layer 202 a doping concentration of Group III elements formed in the amorphous silicon layer between about 1020 atoms / cm ³ and about 10 ²¹ atoms / cm ³ .

In one embodiment, the interface layer is 202 a degeneratively doped amorphous p-type silicon carbide layer (a highly doped amorphous p-type silicon carbide layer, p ++ layer). The carbon elements may be provided by forming during the formation of the highly doped p-type amorphous silicon carbide layer 202 the gas mixture is supplied with a carbon-containing gas. In one embodiment, the addition of methane or other carbonaceous compounds, such as CH ₄ , C ₃ H ₈ , C ₄ H _10, or C ₂ H ₂ , may be used to form a highly doped p-type silicon carbide layer 202 which absorbs less light than other silicon-containing materials. It is believed that the introduction of the carbon atoms into the interface layer 202 the light transmission of the interface layer 202 can improve, so that during the transmission through the film layers less light is absorbed or consumed, whereby the conversion efficiency of the solar cell is improved. In one embodiment, the carbon concentration in the highly doped p-type amorphous silicon carbide layer 202 controlled to be between about 1 atomic percent and about 50 atomic percent. In one embodiment, the amorphous p-type silicon carbide layer 202 the interface has a thickness between about 20 Å and about 300 Å, such as between about 10 Å and about 200 Å, for example between about 20 Å and about 100 Å.

At the in 2 shown special embodiment, since the interface layer 202 is formed so that it is a highly doped p-type amorphous silicon layer or a highly doped p-type amorphous silicon carbide layer, the p-type silicon-containing layer 106 may be formed to be an amorphous p-type silicon layer or an amorphous p-type silicon carbide layer (an amorphous silicon alloy layer) to satisfy various process requirements. In one embodiment, the interface layer is 202 a highly doped amorphous p-type silicon layer, and the p-type silicon-containing layer 106 is an amorphous p-type silicon layer or an amorphous p-type silicon carbide layer. In another embodiment, the interface layer is 202 a highly doped amorphous p-type silicon carbide layer, and the p-type silicon-containing layer 106 is an amorphous p-type silicon carbide layer.

Furthermore, a wavelength selective reflective layer (WSR layer) may be used. 206 between the first pin transition 212 and the second pin junction 214. The WSR layer 206 is formed so as to have film properties which the light scattering and the power generation in the formed solar cell 100 improve. In addition, the WSR layer 206 Also, to ensure a good pn tunnel junction, which has a high electrical conductivity and a tailor-made bandgap area, which affects their transmission and reflection properties in such a way that the efficiency of light conversion of the solar cell formed is improved. The WSR layer 206 may actively serve as an intermediate reflector having a desired refractive index or ranges of refractive indices to reflect light from the light incident side of the solar cell 100 Will be received. The WSR layer 206 may also serve as a transition layer which measures the absorption of the short to medium wavelengths of light (e.g., 280 nm to 800 nm) in the first pin junction 212 amplifies and improves the short circuit current, resulting in increased photon yield and improved conversion efficiency. The WSR layer 206 also has high film transparency for medium to long wavelengths of light (eg, 500 nm to 1100 nm) to reduce the transmission of light to those in the second transition 214 to facilitate trained layers. Furthermore, it is generally desirable that the WSR layer 206 absorbs as little light as possible while maintaining desirable wavelengths of light (eg, shorter wavelengths) back to the layers in the first pin junction 212 reflect and desirable wavelengths of light (eg, longer wavelengths) to the layers in the second pin junction 214 transfers. In addition, the WSR layer 206 have a desirable band gap and high film conductivity so that it effectively conducts the generated current and allows electrons from the first pin junction 212 to the second pin transition 214 to flow, and avoids blocking the generated electricity. In one embodiment, the WSR layer 206 a microcrystalline silicon layer in which n- or p-type dopants within the WSR layer 206 are arranged. In an exemplary embodiment, the WSR layer is 206 an n-type crystalline silicon alloy in which n-type dopants are contained within the WSR layer 206 are arranged. Different dopants in the WSR layer 206 can also affect the optical and electrical properties of the WSR film layer, such as the bandgap, the crystalline fraction, the conductivity, the transmission, the refractive index of the film, the extinction coefficient, and the like. In some cases, one or more dopants may be in different areas of the WSR layer 206 be doped to effectively control and adjust the band gap of the film, the work function (s), the conductivity, the permeability and so werter. In one embodiment, the WSR layer becomes 206 controlled to have a refractive index between about 1.4 and about 4, a bandgap of at least about 2 eV, and a conductivity greater than about 10 ^-6 S / cm.

In one embodiment, the WSR layer 206 an n-doped silicon alloy layer such as silicon oxide (SiO _x , SiO ₂ ), silicon carbide (SiC), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxy carbide (SiOC), silicon oxycarbonitride (SiOCN) or the like. In an exemplary embodiment, the WSR layer is 206 an n-doped SiON or SiC layer.

Further, between the p-silicon-containing layer 112 and the intrinsic silicon-containing layer 114 in the second pin transition 214 optionally an intrinsic pi-type amorphous buffer silicon layer (pi-buffer, PIB) 208 be educated. It is believed that the PIB layer 208 can effectively ensure transfer film properties between the film layers, so that the overall conversion efficiency is improved. In one embodiment, the PIB layer 208 by adding a gas mixture of hydrogen gas and silane gas having a volumetric flow ratio of about 50: 1 or less, for example less than about 30: 1, for example between about 20: 1 and about 30: 1, such as 25: 1; is supplied. Silane gas may be supplied at a flow rate between about 0.5 sccm / l and about 5 sccm / l, such as about 2.3 sccm / l. Hydrogen gas may be supplied at a flow rate between about 5 sccm / l and 80 sccm / l, such as between about 20 sccm / l and about 65 sccm / l, for example, about 57 sccm / l. The showerhead can be supplied with RF energy between 15 mW / cm ² and about 250 mW / cm ² , such as 30 mW / cm ² . The pressure of the chamber may be maintained between about 0.1 Torr and 20 Torr, such as between about 0.5 Torr and about 5 Torr, or at about 3 Torr. The deposition rate of the PIB layer 206 may be about 100 Å / min or more.

Furthermore, a degeneratively doped amorphous n-type silicon layer 210 may be formed primarily as the highly doped n-type amorphous silicon layer for improved ohmic contact with the second TCO layer 118 to ensure. In one embodiment, the highly doped amorphous n-type silicon layer 210 a dopant concentration between about 10 ²⁰ atoms per cubic centimeter and about 10 ²¹ atoms per cubic centimeter.

3 shows an enlarged view of another embodiment of an interface layer between the TCO layer 104 and the p-type silicon-containing layer 106 is arranged. In addition to the interface layer 202 that in conjunction with 2 may be described, a second interface layer 304 between the first interface layer 202 and the p-type silicon-containing layer 106 be arranged. The second interface layer 304 may have a film property that is different from the first interface layer 202 is different to compensate for certain electrical properties that the first interface layer 202 not completely ready. For example, a film that has higher conductivity often has comparatively lower film transparency, which may adversely absorb or reduce the amount of light passing through it on its way to the solar cell junctions, or vice versa. Using this dual layer configuration allows a greater amount of light of different wavelengths to pass through and to the first transition 212 and on to the second transition 214 passes, while maintaining a desired film conductivity, so that a larger amount of electricity is generated.

In one embodiment, the second interface layer is 304 an amorphous p-type silicon layer having a similar dopant concentration of Group III elements as in the p-type silicon-containing layer 106 but of a different type of film (eg with other dopants or alloying elements) like these. For example, if the p-silicon-containing layer 106 is formed as an amorphous p-type silicon layer, the second interface layer 304 be formed as an amorphous p-type silicon carbide. The first interface layer 202 may be either a highly doped p-type amorphous silicon layer or a highly doped p-type silicon carbide p-type layer. The second interface layer 304 may be formed to have a concentration of p-type dopant lower than that of the first interface layer 202 (ie, the highly doped p-type layer), but similar to that of the p-type silicon-containing layer 106 , At the in 3 The illustrated embodiment is the first interface layer 202 a high doped amorphous silicon carbide layer having a thickness between about 10 Å and about 200 Å, and the second interface layer is an amorphous p-type silicon carbide layer having a thickness between about 50 Å and about 200 Å. The p-type silicon-containing layer 106 is an amorphous p-type silicon layer.

4 FIG. 12 shows another embodiment of an interface structure having multiple layers sandwiched between the TCO layer. FIG 104 and the p-type silicon-containing layer 106 are formed. In addition to the in the 2 - 3 illustrated interface layer 202 can be another TCO layer 302 between the lower TCO layer 104 and the interface layer 202 be inserted. In one embodiment, while the lower TCO layer 104 as a tin oxide layer (SnO ₂ ) may be formed, the additional TCO layer 302 be formed as a zinc oxide layer (ZnO). It is believed that the additional TCO layer 302 ensures better chemical resistance to the plasma treatment, which is later performed to form subsequent layers thereon. Good chemical resistance of the additional TCO layer 302 ZnO allows good control of the surface structure while performing a plasma or etching process, thereby improving light trapping ability. Furthermore, the additional TCO layer 302 Also, high film transparency, low film resistivity, and high film conductivity are effective to maintain a high conversion efficiency for the transitional solar cells formed later on. Accordingly, if the additional TCO layer 302 on the lower TCO layer 104 These film properties are controlled in a manner which can improve conversion efficiency, reduce the specific contact resistance and can ensure a high chemical resistance to the plasma as well as a good surface texture desired for the capture of light.

In one embodiment, the additional TCO layer 302 a zinc oxide layer (ZnO) having a dopant concentration of zinc between about 5% and about 5% by weight. The additional TCO layer 302 may have a dopant concentration of aluminum between about 5 percent by weight and about 5 percent by weight. The additional TCO layer 302 may have a thickness controlled between about 50 Å and about 500 Å. The ZnO layer 302 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or any other suitable deposition technique.

After forming the additional TCO layer 302 on the lower TCO layer 104 can be the interface layer 202 and the p-type silicon-containing layer 106 successively formed to form the desired transitions. In an exemplary embodiment the interface layer 202 a highly doped amorphous silicon layer, and the p-type silicon-containing layer 106 is a p-type silicon carbide layer.

5 shows another embodiment of an interface structure between the TCO layer 104 and the p-type silicon-containing layer 106 is trained. An additional TCO layer 302 , similar to the one in 4 shown additional TCO layer 302 , is on the lower TCO layer 104 arranged. Subsequently, the p-silicon-containing layer 106 on the additional TCO layer 302 arranged. In this particular embodiment, the p-type silicon containing layer 106 be formed as a microcrystalline / nanocrystalline p-type silicon or p-type silicon carbide. It should be noted that a nanocrystalline silicon layer has a grain size of about 300 Å or less, and a microcrystalline silicon layer has a grain size of about 300 Å or more. It is believed that a microcrystalline p-type silicon layer or n-type p-type silicon crystalline layer may have lower contact resistance as compared with an amorphous p-type silicon layer. At the in 5 Illustrated exemplary embodiment is the TCO layer 104 a tin oxide (SnO 2) containing TCO layer. The additional TCO layer 302 is a zinc oxide (ZnO) -containing TCO layer, and the p-type silicon-containing layer 106 is a nanocrystalline p-type silicon carbide layer.

6 shows still another embodiment of an interface structure between the TCO layer 104 and the p-type silicon-containing layer 106 is trained. An additional TCO layer 302 , similar to the one in the 4 - 5 shown additional TCO layer 302 , is on the lower TCO layer 104 arranged. Subsequently, an intermediate interface layer 602 on the additional TCO layer 302 arranged. It is assumed that the intermediate interface layer 602 can help create a strong electric field between the extra TCO layer 302 and the amorphous p-type silicon layer to be deposited 106 thereby effectively improving the conversion efficiency of the solar cells. In one embodiment, the intermediate interface layer is 602 a microcrystalline / nanocrystalline p-type silicon layer or microcrystalline / nanocrystalline p-type silicon carbide layer having a thickness between about 10 Å and about 200 Å. Subsequently, the p-silicon-containing layer 106 on the intermediate interface layer 602 arranged. At the in 6 Illustrated exemplary embodiment is the TCO layer 104 a tin oxide (SnO 2) containing TCO layer. The additional TCO layer 302 is a zinc oxide (ZnO) containing TCO layer. The intermediate interface layer 602 is a microcrystalline / nanocrystalline p-type silicon carbide layer, and the p-type silicon-containing layer 106 is an amorphous p-type silicon carbide layer.

7 shows another embodiment of an interface structure between the TCO layer 104 and the p-type silicon-containing layer 106 is trained. In this embodiment, a triple film structure between the TCO layer 104 and the p-type silicon-containing layer 106 be educated. The triple film structure contains an additional TCO layer 302 , a first intermediate layer 702 and a second intermediate layer 704 , The additional TCO layer is the one in the 4 - 6 shown additional TCO layer 302 similar. It is believed that a silicon-based layer (eg, without carbon dopants) may have a relatively higher conductivity, while a silicon alloy layer (eg, with carbon or other alloy dopants) will have high film transparency, which may allow that a large amount of light passes through them and reaches the transitional cells. Accordingly, by using the triple film structure, high film conductivity, high film transparency for high conversion efficiency, and low specific contact resistance can be achieved. At the in 7 illustrated embodiment, the first intermediate layer 702 a microcrystalline / nanocrystalline p-type silicon layer having a thickness between about 10 Å and about 200 Å. The second intermediate layer 704 may be a microcrystalline / nanocrystalline p-type silicon carbide layer having a thickness between about 40 Å and about 200 Å. After the threefold film structure, the p-type silicon-containing layer 106 be formed on the triple film structure. In one embodiment, the p-type silicon containing layer formed on the triple film structure 106 be an amorphous p-type silicon carbide layer.

8th shows another embodiment of an interface structure between the TCO layer 104 and a p-silicon-containing layer 802 is trained. In this particular embodiment, the TCO layer is 104 is selected to be made of a zinc oxide (ZnO) -containing layer. The p-type silicon-containing layer formed thereon 802 is a microcrystalline / nanocrystalline p-type silicon carbide layer having a thickness between about 10 Å and about 200 Å. It is believed that the use of a ZnO-based TCO layer 104 can ensure a good chemical resistance during a plasma treatment for the deposition of the subsequent film layers. Alternatively, the TCO layer 104 also be formed as an n-doped aluminum-zinc oxide (AZO) layer. N-type dopants may be boron, aluminum, gallium and the like. In this particular embodiment, the ZnO-containing TCO layer 104 have a thickness between about 100 Å and about 10000 Å.

9 shows another embodiment of an interface structure between the TCO layer 104 and the p-type silicon-containing layer 106 is trained. In this particular embodiment, the TCO layer 104 be selected so as to be made of a zinc oxide (ZnO) -containing layer similar to that used in conjunction with 8th described TCO layer 104 , An interface layer 602 , such as the in 6 illustrated intermediate interface layer 602 , then on top of the TCO layer 104 arranged. It is assumed that the interface layer 602 can help create a strong electric field between the extra TCO layer 104 and the amorphous p-type silicon layer to be deposited 106 thereby effectively improving the conversion efficiency of the solar cells. In one embodiment, the interface layer is 602 a microcrystalline / nanocrystalline p-type silicon carbide layer having a thickness of between about 10 Å and about 200 Å. Subsequently, the p-silicon-containing layer 106 on the interface layer 602 arranged. At the in 9 Illustrated exemplary embodiment is the TCO layer 104 a zinc oxide (ZnO) containing TCO layer, the interface layer 602 is a microcrystalline / nanocrystalline p-type silicon carbide layer, and the p-type silicon-containing layer 106 is an amorphous p-type silicon carbide layer.

10 shows still another embodiment of an interface structure between the TCO layer 104 and the p-type silicon-containing layer 106 is trained. At the in 10 illustrated embodiment is a double film structure between the TCO layer 104 and the p-type silicon-containing layer 106 educated. In this particular embodiment, the TCO layer 104 be selected so that it is made of a zinc oxide (ZnO) containing layer, similar to those in connection with the 7 - 9 described TCO layer 104 , The double film structure contains a first intermediate layer 702 and a second intermediate layer 704 , similar to the first intermediate layer 702 and the second intermediate layer 704 , in the 7 are shown. The first intermediate layer 702 may be a microcrystalline / nanocrystalline p-type silicon layer having a thickness between about 10 Å and about 200 Å. The second intermediate layer 704 may be a microcrystalline / nanocrystalline p-type silicon carbide layer having a thickness between about 40 Å and about 200 Å. After the triple film structure on the TCO layer 104 has been formed, the p-silicon-containing layer 106 be formed on the triple film structure. In one embodiment, the p-type silicon containing layer formed on the triple film structure 106 be an amorphous p-type silicon carbide layer.

11 FIG. 4 is a schematic cross-sectional view of an embodiment of a plasma enhanced chemical vapor deposition (PECVD) chamber. FIG. 1100 in which one or more films of a thin-film solar cell, such as the solar cells of the 1 - 10 , can be deposited. A suitable plasma enhanced chemical vapor deposition chamber is available from Applied Materials, Inc. of Santa Clara, California. It is conceivable that other deposition chambers, including those from other manufacturers, may be used for the practice of the present invention.

The chamber 1100 generally has walls 1102 , a floor 1104 , a showerhead 1110 and a substrate carrier 1130 on which a process volume 1106 define. Access to the process volume is via a valve 1108 , such that the substrate enters the chamber 1100 can be introduced and removed from it. The substrate carrier 1130 has a substrate receiving surface 1132 for supporting a substrate and one with a lifting system 1136 coupled piston rod 1134 for lifting and lowering the substrate carrier 1130 on. A shading ring 1133 can be optional over the edge of the substrate 102 be attached. lifting bolts 1138 are through the substrate carrier 1130 movably disposed about a substrate to the substrate receiving surface 1132 to move her away from her. The substrate carrier 1130 can also be heating and / or cooling elements 1139 included to the substrate carrier 1130 to keep at a desired temperature. The substrate carrier 1130 can also ground straps 1131 to provide an RF ground at the edge of the substrate carrier 1130 to ensure.

The showerhead 1110 is at its edge by a suspension 1114 with a carrier plate 1112 coupled. The showerhead 1110 can also by one or more central supports 1116 coupled to the support plate to help prevent sagging and / or the straightness / curvature of the showerhead 1110 to control. A gas source 1120 is with the carrier plate 1112 coupled to gas through the carrier plate 1112 and through the showerhead 1110 through the substrate receiving surface 1132 supply. A vacuum pump 1109 is with the chamber 1100 coupled to the pressure in the process volume 1106 to regulate to a desired value. An RF energy source 1122 is with the carrier plate 1112 and / or the showerhead 1110 Coupled to the showerhead 1110 To supply RF energy, leaving an electric field between the showerhead and the substrate carrier 1130 is generated, allowing a plasma from the gases between the showerhead 1110 and the substrate carrier 1130 can be generated. Various RF frequencies may be used, such as a frequency between about 0.3 MHz and about 200 MHz. In one embodiment, the RF power source has a frequency of 13.56 MHz.

A remote plasma source 1124 , such as an inductively coupled remote plasma source, may also be coupled between the gas source and the carrier plate. Between the processing of the substrates, a cleaning gas of the remote plasma source 1124 are supplied so that a remote plasma is generated and is supplied to purify chamber components. The cleaning gas may be due to the RF energy source 1122 additionally energized, which supplies energy to the showerhead. Suitable cleaning gases include NF ₃ , F ₂ and SF ₆ .

The deposition processes for one or more layers, such as one or more of the layers of the 1 - 10 , the following deposition parameters in the process chamber of 11 or another suitable chamber. A substrate having a smooth surface of 10,000 cm ² or more, 40,000 cm ² or more, or 55,000 cm ² or more is supplied to the chamber. Of course, the substrate can be cut after processing to form smaller solar cells.

In one embodiment, the heating and / or cooling elements 1139 be set to have a substrate support temperature of about 400 ° C or less during deposition, for example between about 100 ° C and about 400 ° C, or between about 150 ° C and about 300 ° C, such as about 200 ° C, ensure.

The distance between the top of a substrate located on the substrate receiving surface 1132 is arranged, and the showerhead 1110 during deposition may be between 400 mils and about 1,200 mils, for example between 400 mils and about 800 mils.

12 is a schematic plan view of an embodiment of a process system 1200 that has several process chambers 1231 - 1237 of the type of PECVD chamber 1100 from 11 or other suitable chambers capable of depositing silicon films. The process system 1200 contains a transfer chamber 1220 that with a lock chamber 1210 and the process chambers 1231 - 1237 is coupled. The lock chamber 1210 allows substrates between the outside environment outside the system and the vacuum environment inside the transfer chamber 1220 and the process chambers 1231 - 1237 be transported. The lock chamber 1210 contains one or more evacuable areas which receive one or more substrates. The evacuable areas become during the introduction of substrates into the system 1200 pumped out during the removal of the substrates from the system 1200 ventilated. The transfer chamber 1220 has at least one vacuum robot arranged in it 1222 which is suitable for substrates between the lock chamber 1210 and the process chambers 1231 - 1237 tranship. Although in 12 With seven process chambers shown, no limitation of the scope of the invention to this configuration is intended, as the system may include any suitable number of process chambers.

In certain embodiments of the invention, the system is 1200 adapted to the first pin junction (eg reference numerals 122 . 212 ) to deposit a solar cell with multiple transitions. In one embodiment, one of the process chambers 1231 - 1237 configured to deposit the interface layer (s) and p-layer (s) of the first pin junction, while the remaining process chambers 1231 - 1237 are each designed to deposit both the intrinsic layer (s) and the n-layer (s). The intrinsic layer (s) and the n-layer (s) of the first pin junction may be deposited in the same chamber without any passivation process between the deposition steps. Therefore, in one configuration, a substrate passes through the lock chamber 1210 into the system, the substrate is then transferred by the vacuum robot into the special process chamber, which is designed to deposit the p-layer (s). Next, after the formation of the p-layer, the substrate is reloaded by the vacuum robot into one of the remaining process chambers, which is adapted to deposit both the intrinsic layer (s) and the n-layer (s). After the formation of the intrinsic layer (s) and the n-layer (s), the substrate is passed through the vacuum robot 1222 back to the lock chamber 1210 transported. In certain embodiments, processing a substrate in the process chamber to form the p-layer (s) is about 4 times as fast as about 6 times as fast as processing to form the intrinsic layer (s) and the n Layer (s) in a single chamber. Therefore, in certain embodiments of the system for depositing the first pin junction, the ratio of p-wells to i / n-wells is 1: 4 or more, such as about 1: 6 or more. The throughput of the system, including the time to perform the plasma cleaning of the process chambers, may be about 10 substrates / hr or more, such as about 20 substrates / hr or more.

In certain embodiments of the invention is a system 1200 adapted to the second pin junction (eg reference numerals 124 . 214 ) to deposit a solar cell with multiple transitions. In one embodiment, one of the process chambers 1231 - 1237 designed to deposit the p-layer (s) of the second pin junction, while the remaining process chambers 1231 - 1237 are each designed to deposit both the intrinsic layer (s) and the n-layer (s). The intrinsic layer (s) and the n-layer (s) of the second pin junction may be deposited in the same chamber without any passivation process between the deposition steps. In certain embodiments, processing a substrate in the process chamber to form the p-layer (s) is about 4 or more times as fast as forming the intrinsic layer (s) and n-layer (s). in a single chamber. Therefore, in certain embodiments of the system for depositing the second pin junction, the ratio of p-wells to i / n-wells is 1: 4 or more, such as about 1: 6 or more. The throughput of the system, including the time to perform the plasma cleaning of the process chambers, may be about 3 substrates / hr or more, such as 5 substrates / hr or more.

In certain embodiments, the throughput of a system is 1200 , which is designed to deposit the first pin junction comprising an intrinsic amorphous silicon layer, twice the throughput of a system 1200 which is used to deposit the second pin junction comprising an intrinsic microcrystalline silicon layer due to the difference in thickness between the intrinsic microcrystalline silicon layer (s) and the intrinsic amorphous silicon layer (s). Therefore, a single system 1200 , which is adapted to deposit the first pin junction comprising an intrinsic amorphous silicon layer, with two or more systems 1200 which are adapted to deposit a second pin junction comprising an intrinsic microcrystalline silicon layer. Accordingly, to efficiently control throughput, the process of depositing an ESC layer may be configured to be performed in the system configured to deposit the first pin junction. Once a first pin junction has been formed in a system, the substrate can be exposed to the outside environment (ie, break the vacuum) and delivered to the second system where the second pin junction is formed. Wet or dry cleaning of the substrate between the first system depositing the first pin junction and the second pin junction may be required. In one embodiment, the process of depositing the ESC layer may be configured such that deposition occurs in a separate system.

13 shows an arrangement of a section of a production line 1300 containing multiple deposition systems 1304 . 1305 . 1306 , or cluster tools, that has by automation facilities 1302 connected in a transfer-enabling manner. In one arrangement, the production line includes 1300 , as in 13 shown, several deposition systems 1304 . 1305 . 1306 which can be used to form one or more layers, to form a pin junction (transitions) or a complete solar cell device on a substrate 102 to build. The systems 1304 . 1305 . 1306 can the in 12 illustrated system 1200 however, are generally designed to have different layers or transitions on the substrate 102 deposit. In general, each of the deposition systems 1304 . 1305 . 1306 one lock each 1304F . 1305F . 1306F on which of the lock 1210 is similar, each lock in a transfer enabling communication with an automation device 1302 stands. The automation device 1302 is designed to be substrates between the deposition systems 1304 . 1305 and 1306 to move.

During the course of the process, a substrate generally becomes a system automation device 1302 to one of the systems 1304 . 1305 . 1306 transported. In one embodiment, the system 1306 several chambers 1306A - 1306H each configured to deposit or process one or more layers in the formation of an interface layer, a first pin junction; the system 1305 that has a variety of chambers 1305A - 1305H is configured to deposit the one or more WSR layers and the system 1304 that the multiplicity of chambers 1304A - 1304H is formed to deposit or process one or more layers in the formation of the second pin junction. It should be noted that the number of systems and the number of chambers configured to deposit the individual layers in each of the systems may be varied to suit different process requirements and configurations.

The automation device 1302 can generally be a handling device or a Conveyors which are adapted to move and position a substrate. In one example, the automation device is 1302 a series of conventional substrate conveyors (eg, roller conveyors) and / or handling devices (eg, six-axis robots, SCARA robots) adapted to support the substrate within the production line 1300 to move and position at will. In one embodiment, one or more automation devices include 1302 also one or more substrate sub-components or "drawbridge" conveyors used to enable substrates upstream of a desired system to pass past a substrate that would block its movement to another desired position within the production line 1300 be transported. In this way, movement of substrates to the various systems is not hampered by other substrates waiting to be fed to another system.

In one embodiment of the production line 1300 there is a structuring chamber 1350 in communication with one or more of the promoters 1302 and is configured to perform a patterning operation on one or more of the layers in the formed WSR layer or any layers used to form the transitional cells. It is also conceivable that the patterning process may also be used to etch one or more regions in one or more of the previously formed layers during the process of forming the solar cell devices. Although the configurations of the structuring chamber 1350 In general, for etch-type patterning operations, this configuration need not be limiting in view of the scope of the invention described herein. In one embodiment, the structuring chamber 1350 used to remove one or more regions in one or more of the formed layers and / or to deposit one or more material layers (eg, dopant-containing materials, metal pastes) on the one or more formed layers on the substrate surface.

Although the above relates to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and its scope will be determined by the following claims. For example, the process chamber of 11 shown in a horizontal position. Of course, in other embodiments of the invention, the process chamber may be in any non-horizontal, such as in a vertical position. Embodiments of the invention have been described with reference to the cluster tool with multiple process chambers in the 12 and 13 However, inline systems and inline / cluster hybrid systems can also be used. Embodiments of the invention have been described with reference to a first system configured to form a first pin junction and a second system configured to form a WSR layer and a third system formed therefor is to form a second pin junction, but the first pin junction, the WSR layer and a second pin junction can also be formed in a single system. Embodiments of the invention have been described with reference to a process chamber configured to deposit both a WSR layer and an intrinsic layer and an n-layer, but separate chambers may be configured to include the intrinsic layer and the n-layer and depositing a WSR layer, and a single process chamber may be configured to deposit both a p-layer and an ESC layer and an intrinsic layer. Finally, the embodiments described herein are pin configurations that are generally applicable to translucent substrates such as glass; however, other embodiments are contemplated in which nip junctions, singly or multiply stacked, are fabricated on opaque substrates such as stainless steel or polymer in a reverse deposition sequence.

Thus, an apparatus and method for fabricating an interface structure between a TCO layer and a solar cell junction is provided. The interface structure advantageously ensures low contact resistance, high film conductivity, and high film transparency, which can effectively improve the photoelectric conversion efficiency and device performance of the PV solar cell as compared with conventional methods.

The invention also relates to an apparatus for carrying out the disclosed method steps, which may include apparatus parts for performing each described method step. These process steps may be performed by hardware components, by a computer programmed with appropriate software, by any combination of the two, or in any other way. Furthermore, the invention also relates to methods by which the described devices are operated. It includes method steps for performing each function of the devices.

Although the above relates to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and its scope will be determined by the following claims.

Claims (15)

Photovoltaic device, comprising: a first TCO layer disposed on a substrate; a second TCO layer disposed on the first TCO layer; and a p-type silicon-containing layer formed on the second TCO layer. The photovoltaic device of claim 1, wherein the p-type silicon-containing layer comprises carbon. The photovoltaic device according to any one of the preceding claims, further comprising: a p-type silicon carbide layer disposed between the second TCO layer and the p-type silicon-containing layer, wherein the p-type silicon carbide layer is at least one of a microcrystalline silicon carbide layer, a nanocrystalline silicon carbide layer or an amorphous silicon carbide layer. The photovoltaic device of claim 3, further comprising: a nanocrystalline p-type silicon layer disposed between the second TCO layer and the p-type silicon carbide layer. The photovoltaic device according to any one of the preceding claims, further comprising: a degeneratively doped p-type amorphous silicon layer disposed between the second TCO layer and the p-type silicon-containing layer. The photovoltaic device according to any one of the preceding claims, wherein the first TCO layer is a tin oxide-containing layer and the second TCO layer is a zinc oxide-containing layer. The photovoltaic device according to any one of the preceding claims, further comprising: an intrinsic silicon-containing layer disposed on the p-silicon-containing layer; and an n-type silicon-containing layer disposed on the intrinsic silicon-containing layer. A photovoltaic device comprising: a TCO layer disposed on a substrate; an interface layer disposed on the TCO layer, the interface layer being a p-type silicon-containing layer comprising carbon; and a p-type silicon-containing layer disposed on the interface layer. The photovoltaic device of claim 8, wherein the interface layer is a degeneratively doped p-type amorphous silicon carbide layer or a p-type silicon carbide p-type crystalline layer. The photovoltaic device according to any of the preceding claims 8 to 9, further comprising: a nanocrystalline p-type silicon layer disposed between the interface layer and the TCO layer. The photovoltaic device according to any of the preceding claims 8 to 10, wherein the TCO layer is a zinc oxide-containing layer having an n-type doping element selected from aluminum, boron and gallium. A method of forming a photovoltaic device, comprising: Forming a first TCO layer on a substrate; Forming a second TCO layer on the first TCO layer; and Forming a first p-i-n junction on the second TCO layer, wherein the first p-i-n junction comprises: Forming a p-type silicon-containing layer over the second TCO layer, wherein the p-type silicon-containing layer is a microcrystalline silicon-based layer, a nanocrystalline silicon-based layer or an amorphous silicon-based layer; Forming an intrinsic silicon-containing layer over the p-type silicon-containing layer; and Forming an n-silicon containing layer over the intrinsic silicon containing layer. The method of claim 12, further comprising: Forming a p-type silicon carbide layer disposed between the second TCO layer and the first p-i-n junction, wherein the p-type silicon carbide layer is at least one of a microcrystalline silicon carbide layer, a nanocrystalline silicon carbide layer, or an amorphous silicon carbide layer. The method of claim 13, further comprising: Forming a nanocrystalline p-type silicon layer between the second TCO layer and the p-type silicon carbide layer. The method of any one of preceding claims 12 to 14, wherein the first TCO layer is a tin oxide-containing layer and the second TCO layer is a zinc oxide-containing layer.

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