DE112004002155T5 - A method of integrating a high-k gate dielectric in a transistor fabrication process - Google Patents

Abstract

A method of fabricating a field effect transistor on a substrate (104), the substrate (104) having a high-k dielectric layer disposed over the substrate (104) and a gate electrode layer disposed over the high-k dielectric layer, comprising, the method comprising the steps of:
Etching (202) the gate electrode layer and the high-k dielectric layer to form a gate stack (102), the gate stack (102) comprising a high-k dielectric segment (106) disposed over the substrate (104); a gate electrode segment (108) disposed over the high-k dielectric segment (106);
Performing (204) a nitriding process on the gate stack (102).

Description

technical area

The The present invention generally relates to the field of semiconductor devices and more particularly, the present invention relates to the field of Production of field effect transistors.

background

at the size reduction Field effect transistors ("FETs"), such as PFETs and NFETs, use semiconductor manufacturers Gate dielectrics with a high dielectric constant ("large ε") to the performance and the reliability from FET's to improve. Gate dielectrics with large ε are in Technologies with small feature sizes desirable because conventional Gate dielectrics, such as silicon dioxide, are too thin and these to one high tunnel current as well as other problems that cause the performance and the reliability of FETs. However, you can Problems during the integration of a high-k gate dielectric in a transistor fabrication process occur.

In a conventional transistor fabrication process with a gate dielectric with big ε can one Gate stack can be made by a gate electrode layer and a high-k dielectric layer overlying the gate electrode layer and a substrate, are etched in a gate etching process. The gate electrode layer, which is a conductive material, such as polysilicon, and the high-k dielectric layer, zirconia, Hafnium oxide, or other high ε material, may be typical by plasma in a plasma etching chamber etched. While the plasma etching process However, the plasma may be the sidewalls of the gate stack, the exposed one Contains areas of the gate electrode and segments with dielectric with high ε damage. For example For example, the plasma can etch away a portion of the high-k dielectric material can influence the chemical structure of the dielectric with high ε. After the gate etching process In general, a wet cleaning process is performed on the gate stack executed to remove contaminants. However, also the wet cleaning process can damage the dielectric with high ε by a certain proportion of the high-k dielectric material is removed becomes. Furthermore, oxygen can be introduced laterally into the gate dielectric with big ε during the subsequent process steps diffuse and the properties of the high-k dielectric material and the transistor gate.

It There is therefore a need for an efficient method for integrating a gate radius with big ε in one Transistor manufacturing process.

overview

The The present invention addresses this problem and solves the problem in the prior art with regard to an efficient method of integration a gate dielectric with large ε in one Transistor manufacturing process.

According to one illustrative embodiment comprises a method for producing a field effect transistor on a substrate, wherein the substrate is a dielectric layer with big ε over the Substrate is arranged, and has a gate electrode layer, the above the high-k dielectric layer is disposed, the step of the etching the gate electrode layer and the high-k dielectric layer around one Form gate stack, wherein the gate stack is a segment of dielectric includes with large ε, the above the substrate is arranged, and has a gate electrode segment, the above the segment of dielectric is arranged with a large ε. The segment made of high-k dielectric, for example Hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate or aluminum oxide and the gate electrode segment may be polysilicon.

According to this illustrative embodiment The method further comprises performing a nitriding process at the gate stack. The nitration process can, for example, under Application of a plasma performed be sidewalls of the Nitrate gate stack, wherein the plasma has nitrogen. The nitration process can cause the nitrogen in the segment made of dielectric with a high ε occurs and, for example, an oxygen diffusion barrier in the segment made of dielectric with a high ε. The step of etching the Gate electrode layer and the high-k dielectric layer may be in executed a process chamber The process chamber is also applied to the nitriding process for example, to execute on the gate stack. In one embodiment becomes the step of etching the gate electrode layer and the high-k dielectric layer in one executed first process chamber and the step of performing the nitriding process on the gate stack becomes in a second process chamber executed. Other features and advantages of the present invention will become apparent for the expert in the study of the following detailed description and the accompanying Drawings obvious.

Short description the drawings

1 shows a cross-sectional view of a structure with an exemplary transistor gate stack according to an embodiment of the present invention.

2 FIG. 10 is a flowchart corresponding to example method steps according to an embodiment of the present invention. FIG.

detailed Description of the invention

The The present invention is directed to a method of integration a gate dielectric with large ε in one Transistor manufacturing process. The following description contains special Information that pertains to the implementation of the present Relate invention. The person skilled in the art recognizes that the present invention be implemented in a different way than that specifically in the explained in the present application is. Furthermore, some of the specific details of the invention are not explains not unnecessary to the invention to darken.

The Drawings in the present application and the associated detailed Description is directed to exemplary embodiments only the invention. The brevity half are other embodiments of the present invention not specifically in the present application and are not specific in the present drawings shown.

1 FIG. 12 shows a cross-sectional view of an exemplary structure with an exemplary gate stack according to one embodiment of the present invention. FIG. A structure 100 includes a gate stack 102 standing on a substrate 104 is arranged. The gate stack 102 contains a dielectric segment 106 with large ε and a gate electrode segment 108 and further includes sidewalls 110 on. In an embodiment, the gate stack comprises 102 an intermediate layer (in 1 not shown) interposed between the high-k dielectric segment 106 and the substrate 104 is arranged. The structure 100 FIG. 12 illustrates an intermediate step in a transistor fabrication process that is used to form a FET, such as an NFET or a PFET, covering the gate stack 102 contains.

As in 1 is shown is the dielectric segment 106 with large ε above the substrate 104 arranged and may have a dielectric with high ε, such as hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate or aluminum oxide. It should be noted that the high-k dielectrics mentioned above or referred to in other parts of the present application are merely specific examples, although other high-k dielectrics may be used, and the present invention. The invention is not limited by the use of only those high-k dielectrics previously mentioned. For example, the dielectric segment with large ε 106 have a thickness of from about 20.0 angstroms to about 100.0 angstroms. As in 1 is shown is the gate electrode segment 108 over the dielectric segment with large ε 106 arranged and may comprise polysilicon. For example, the gate electrode segment 108 have a thickness of about 500.0 angstroms to about 1500.0 angstroms.

The gate stack 102 containing the dielectric segment with large ε 106 and the gate electrode segment 108 may be formed by etching a high-k dielectric layer and a gate electrode layer in a gate etching process, respectively. Before the gate etching process, the high-k dielectric layer becomes over the substrate 104 and the gate electrode layer may be formed over the high-k dielectric layer in a manner known per se. For example, in the gate etching process, the high-k dielectric layer and the gate electrode layer in a process chamber may be etched by using a plasma etching process. In this transistor fabrication process flow of the present invention, after the fabrication of the gate stack 102 a nitration process on the gate stack 102 executed. The nitriding process may be carried out by applying a plasma with nitrogen, ie, a nitrogen plasma, to exposed surfaces of the gate stack 102 like the side walls 110 , to nitrate or to install in nitrogen. The nitriding process can be carried out in the same process chamber used to stack the gate 102 in the gate etching process explained above. In one embodiment, the nitriding process is performed in a process chamber other than the chamber (ie, the process chamber) used to perform the gate etching process. In such an embodiment, after the gate etching process, the gate stack becomes 102 Removed disc removed from the process chamber, which was used to perform the gate etching process, and it is carried out a wet cleaning process on the disc in a wet cleaning system. The the gate stack 102 having disc is then placed in a further process chamber, in which the nitriding process on the gate stack 102 is carried out. In one embodiment, the nitriding process on the gate stack 102 executed immediately after performing the gate etching process.

By performing the nitriding process, around the sidewalls 110 of the gate pack 102 to Upon performing the gate etch process with nitrogen, the process flow of the present invention may utilize the nitriding process to repair damage to the gate stack 102 may have occurred during the gate etching process. Further, during the nitriding process, nitrogen may be introduced into the high-k dielectric segment 106 be introduced. As a result, the nitrogen that enters the dielectric segment with high ε 106 introduced, form a barrier, which unwanted lateral oxygen diffusion into the dielectric segment with large ε 106 during the subsequent process steps can prevent. In an embodiment of the present invention in which a gate stack having an interlayer is used wherein the interlayer comprises nitride, the nitriding process may replace nitride consumed in the interlayer during the gate etch process.

After performing the nitriding process, the transistor fabrication process flow of the present invention proceeds in a manner similar to a conventional transistor fabrication process. For example, source / drain regions in the substrate 104 adjacent to the gate stack 102 can be implanted, it can spacers adjacent to the side walls 110 of the gate pack 102 can be formed, a fast thermal cal treatment and other process steps can be performed, which are required to complete a transistor, such as a FET's.

2 FIG. 12 is a flowchart illustrating an example method according to an embodiment of the present invention. FIG. Certain details and features are from the flow chart 200 omitted, which are familiar to those skilled in the art. For example, a step may consist of several substeps or may require special equipment or materials, as is known in the art. In step 202 of the flowchart 200 For example, a high-k dielectric layer disposed over a substrate and a gate electrode layer disposed over the high-k dielectric layer are etched to form a gate stack. For example, the gate stack 102 containing the dielectric segment with large ε 106 that over a substrate 104 is arranged, and the gate electrode segment 108 , which is above the dielectric segment with large ε 106 is formed by appropriately etching the gate electrode layer and the high-k dielectric layer using a plasma etching method in a gate etching process.

In step 204 For example, a nitriding process is performed on the gate stack after performing the gate etching process. For example, the nitration process on the gate stack 102 after the gate etching process using a nitrogen plasma to nitride the sidewalls 110 of the gate pack 102 be executed. For example, the nitriding process may be carried out in the same process chamber that is also used to perform the gate etching process. In one embodiment, a process chamber different from that (ie, the process chamber) used to perform the gate etch process is used to perform the nitridation process. In step 206 the transistor process flow is continued by performing process steps necessary to complete transistor fabrication. For example, source / drain regions in the substrate 104 adjacent to the gate stack 102 can be implanted, it can spacers adjacent to the side walls 110 of the gate pack 102 and other suitable process steps may be performed to complete the fabrication of a transistor such as a FET.

As previously explained can, therefore, by running of the nitriding process after a gate etching process according to the invention, the nitriding process be applied to damage to repair that on sidewalls of the gate stack during the gate etching process may occur. Furthermore, by the nitration process according to the invention nitrogen introduced into the high-k dielectric segment of the gate stack, see FIG that the nitrogen forms a barrier that is an undesirable lateral Oxygen diffusion into the high-k dielectric segment during the following Can prevent process steps.

Out the foregoing description of exemplary embodiments It will be apparent from the present invention that various techniques used to implement the concepts of the present invention can be without departing from its scope. Although the invention with Reference to certain embodiments is described, the skilled artisan recognizes that changes in form and detail carried out can be without deviate from the spirit and scope of the invention. The described exemplary embodiments are in each Regard as vivid and not restrictive. It should It should be noted that the invention is not limited to the specific examples described embodiments limited is, but that many other arrangements, modifications and substitutions possible are without departing from the scope of the invention.

Consequently discloses a method of integrating a high-k gate dielectric into a Transistor manufacturing process described.

202

Ätzen der Gateelektrode und der dielektrischen Schicht mit großem ε, die über dem

Substrat angeordnet sind, um einen Gatestapel zu bilden

204

Ausführen des Nitrierungsprozesses an dem Gatestapel nach dem Gateätzprozess

206

Fortsetzen des Transistorprozessablaufs durch Ausführen von Prozessschritten, die

zur Vollendung der Transistorherstellung erforderlich sind

Fig. 2

202

Etching the gate electrode and the high-k dielectric layer over the

Substrate are arranged to form a gate stack

204

Performing the nitriding process on the gate stack after the gate etching process

206

Continue the transistor process flow by performing process steps that

necessary to complete the transistor fabrication

Summary

According to one illustrative embodiment, a method of fabricating a field effect transistor on a substrate ( 104 ), which has a high-k dielectric layer overlying the substrate ( 104 ), and a gate electrode layer disposed over the high-k dielectric layer has a step of etching (FIG. 202 ) of the gate electrode layer and the high-k dielectric layer around a gate stack ( 102 ), the gate stack ( 102 ) a dielectric segment with high ε ( 106 ) above the substrate ( 104 ), and a gate electrode segment (FIG. 108 ) across the high-k dielectric segment ( 106 ) is arranged. According to this exemplary embodiment, the method further comprises executing ( 204 ) of a nitration process on the gate stack ( 102 ). The nitriding process can be carried out, for example, by using a plasma for nitriding sidewalls (US Pat. 110 ) of the gate stack ( 102 ), the plasma containing nitrogen. The nitriding process may cause the nitrogen to enter the high-k dielectric segment (FIG. 106 ) and, for example, an oxygen diffusion barrier in a high-k dielectric segment ( 106 ).

Claims (10)

Method for producing a field effect transistor on a substrate ( 104 ), the substrate ( 104 ) a high-k dielectric layer overlying the substrate ( 104 ), and a gate electrode layer disposed over the high-k dielectric layer, the method comprising the steps of: etching ( 202 ) of the gate electrode layer and the high-k dielectric layer around a gate stack ( 102 ), the gate stack ( 102 ) a dielectric segment with high ε ( 106 ) above the substrate ( 104 ), and a gate electrode segment (FIG. 108 ), which is above the high-k dielectric segment (FIG. 106 ) is arranged; To run ( 204 ) of a nitration process on the gate stack ( 102 ). The method of claim 1, wherein the step of executing ( 204 ) of the nitration process on the gate stack ( 102 ) comprises: using a plasma to add nitrogen to sidewalls ( 110 ) of the gate stack ( 102 ), wherein the plasma has nitrogen. The method of claim 1, wherein the step of executing ( 204 ) of the nitration process on the gate stack ( 102 ) causes the nitrogen in the high-k dielectric segment ( 106 nitrogen penetrates an oxygen diffusion barrier in the high-k dielectric segment (FIG. 106 ). Method for producing a field effect transistor on a substrate ( 104 ), the substrate ( 104 ) a high-k dielectric layer overlying the substrate ( 104 ), and a gate electrode layer disposed over the high-k dielectric layer, the method comprising the step of etching (FIG. 202 ) of the gate electrode layer and the high-k dielectric layer for producing a gate stack (US Pat. 102 ), wherein the gate stack ( 102 ) a dielectric segment with high ε ( 106 ) above the substrate ( 104 ), and a gate electrode segment (FIG. 108 ), which is above the high-k dielectric segment (FIG. 106 ), the method being characterized by: executing ( 204 ) of a nitration process on the gate stack ( 102 ). The method of claim 4, wherein the step of executing ( 204 ) of the nitration process on the gate stack ( 102 ) Using a plasma for nitriding sidewalls ( 110 ) of the gate stack ( 102 ), wherein the plasma contains nitrogen. The method of claim 4, wherein the step of executing ( 204 ) of the nitration process on the gate stack ( 102 ) causes nitrogen to enter the high-k dielectric ( 106 ), wherein the nitrogen has an oxygen diffusion barrier in the high-k dielectric segment (FIG. 106 ). Method for producing a field effect transistor on a substrate ( 104 ), wherein the substrate is a high-k dielectric layer above the substrate ( 104 ), and a gate electrode layer disposed over the high-k dielectric layer, the method comprising the steps of: etching ( 202 ) of the gate electrode layer and the high-k dielectric layer to form a gate pel ( 102 ), the gate stack ( 102 ) a dielectric segment with high ε ( 106 ) above the substrate ( 104 ), and a gate electrode segment (FIG. 108 ), which is above the high-k dielectric segment (FIG. 106 ), and wherein the gate stack ( 102 ) Side walls ( 110 ) having; Use ( 204 ) of a nitrogen plasma around the sidewalls ( 110 ) of the gate stack ( 102 ) to nitride. The method of claim 7, wherein the step of using ( 204 ) of the nitrogen plasma for nitriding the side walls ( 110 ) of the gate stack ( 102 ) causes the nitrogen in the high-k dielectric segment ( 106 ), wherein the nitrogen has an oxygen diffusion barrier in the high-k dielectric segment (FIG. 106 ). The method of claim 7, wherein the step of etching ( 202 ) of the gate electrode layer and the high-k dielectric layer for producing the gate stack (US Pat. 102 ) is carried out in a process chamber, the process chamber being used to perform the step of using ( 204 ) of a nitrogen plasma for nitriding the side walls ( 110 ) of the gate stack ( 102 ) is used. The method of claim 7, wherein the step of etching ( 202 ) of the gate electrode layer and the high-k dielectric layer for producing the gate stack (US Pat. 102 ) is performed in a first process chamber, and wherein the step of using ( 204 ) of a nitrogen plasma for nitriding the side walls ( 110 ) of the gate stack ( 102 ) is performed in a second process chamber.