DE1035787B - A method for producing a semiconductor device with several UEbergaengen, e.g. B. surface transistors - Google Patents

A method for producing a semiconductor device with several UEbergaengen, e.g. B. surface transistors

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Publication number
DE1035787B
DE1035787B DES44639A DES0044639A DE1035787B DE 1035787 B DE1035787 B DE 1035787B DE S44639 A DES44639 A DE S44639A DE S0044639 A DES0044639 A DE S0044639A DE 1035787 B DE1035787 B DE 1035787B
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Prior art keywords
alloying
semiconductor base
doped
alloy
activator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DES44639A
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German (de)
Inventor
Dr Heinz Henker
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Siemens AG
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Siemens AG
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Filing date
Publication date
Priority to DES40325A priority Critical patent/DE1036393B/en
Application filed by Siemens AG filed Critical Siemens AG
Priority to DES44639A priority patent/DE1035787B/en
Priority to FR1131582D priority patent/FR1131582A/en
Priority to CH346617D priority patent/CH346617A/en
Priority to FR70726D priority patent/FR70726E/en
Priority to GB2108756A priority patent/GB841195A/en
Publication of DE1035787B publication Critical patent/DE1035787B/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B31/00—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor
    • C30B31/04—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor by contacting with diffusion materials in the liquid state
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/228—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Bipolar Transistors (AREA)

Description

DEUTSCHESGERMAN

Es ist bekannt, p-n-Übergänge in Halbleitern durch Einlegierung eines Donators oder Akzeptors in einem hochgereinigten oder anders dotierten Halbleiterkörper herzustellen. Durch Einlegierung von beiden Seiten entstehen auf diese Weise die sogenannten Legierungs- oder Diffusionstransistoren. Eine bekannte Ausführungsform dieser Art besteht aus einem n-leitenden, dünnen Germaniumstück, auf dessen beide Oberflächen je eine gewisse Menge p-Leitung erzeugendes Indium auflegiert ist. Das dünne Germaniumstück ist auf diese Weise von zwei p-n-Übergängen eingeschlossen und es können die so entstandenen drei Zonen in bekannter Weise als Transistor geschaltet werden.It is known to create p-n junctions in semiconductors by alloying a donor or acceptor in one to produce highly purified or otherwise doped semiconductor bodies. By alloying from both sides In this way, the so-called alloy or diffusion transistors are created. An acquaintance Embodiment of this type consists of an n-type, thin piece of germanium, on both of which Surfaces are alloyed with a certain amount of indium which generates p-conduction. The thin piece of germanium is enclosed in this way by two p-n junctions and the resulting three can Zones are switched in a known manner as a transistor.

Zur Herstellung einer Halbleiteranordnung mit mehreren Übergängen zwischen Zonen unterschiedlichen Leitungstyps ist bereits ein Verfahren vorgeschlagen worden, bei dem die einlegierte Substanz einen Aktivator mit höherem Diffusionskoeffizienten bei kleinerem Verteilungskoeffizienten und einem anderen antipolaren Aktivator mit niederem Diffusionskoeffizienten bei höherem Verteilungskoeffizienten enthält, um auf diese Weise eine Folge von p- und η-Schichten zu erzeugen, die beispielsweise als Hakenkollektor Verwendung finden können.For the production of a semiconductor arrangement with several transitions between zones different Conduction type has already been proposed a method in which the alloyed substance an activator with a higher diffusion coefficient with a smaller partition coefficient and a another antipolar activator with a lower diffusion coefficient and a higher partition coefficient contains, in order to produce a sequence of p- and η-layers in this way, for example as a hook collector Can be used.

Der Nachteil dieser Anordnung besteht darin, daß sich die untere Zone, welche an das Grundmaterial des Halbleiterkörpers angrenzt, schwer kontaktieren läßt.The disadvantage of this arrangement is that the lower zone, which is attached to the base material of the semiconductor body is adjacent, difficult to contact.

Gemäß der Erfindung wird dieser Nachteil dadurch vermieden, daß bei dem Verfahren zur Herstellung einer Halbleiteranordnung mit mehreren Übergängen zwischen Zonen unterschiedlichen Leitungstyps, vorzugsweise Flächentransistoren, die durch Einlegierung von Aktivatormaterialien unterschiedlichen Verteilungs- und/oder Diffusionskoeffizienten hergestellt werden, die Oberfläche des Halbleitergrundkristalls vor dem Einlegieren der Aktivatormaterialien mit einem Donator oder einem Akzeptor, vorzugsweise durch Diffusion oder Legierung dotiert wird, und dieses Aktivatormaterial so gewählt ist, daß es sich bei Rekristallisation zunächst bevorzugt abscheidet.According to the invention, this disadvantage is avoided in that in the method of manufacture a semiconductor arrangement with several transitions between zones of different conductivity types, preferably Surface transistors, which by alloying activator materials with different distribution and / or diffusion coefficients are produced, the surface of the semiconductor base crystal before alloying the activator materials with a donor or an acceptor, preferably is doped by diffusion or alloy, and this activator material is chosen so that it initially preferentially precipitates upon recrystallization.

Hierdurch wird der Vorteil erreicht, daß die untere Zone seitlich über die Legierungszone des Gemisches hinausragt und infolgedessen leicht kontaktiert werden kann.This has the advantage that the lower zone laterally over the alloy zone of the mixture protrudes and can therefore be easily contacted.

Bei Dotierung der Oberfläche durch gerichtete Strahlen, beispielsweise durch Atomstrahlen oder mittels einer Gasentladung, welche an der zu dotierenden Oberfläche des Halbleitergrundkristalls ansetzt, läßt sich eine Zone gewünschter Größe dotieren. Zweckmäßigerweise wird jedoch die ganze Oberfläche des Halbleitergrundkristalls mindestens auf der einen Seite vorwegdotiert. Gegebenenfalls ist es sogar Verfahren zur HerstellungWhen doping the surface by directed rays, for example by atomic beams or by means of a gas discharge, which attaches to the surface of the semiconductor base crystal to be doped, a zone of the desired size can be doped. Appropriately, however, the entire surface of the semiconductor base crystal doped in advance at least on one side. It may even be Method of manufacture

einer Halbleiteranordnung mit mehreren Übergängen, z.B. Flächen-Transistorena semiconductor device with multiple junctions, e.g. area transistors

Anmelder:
Siemens & Halske Aktiengesellschaft,Applicant:
Siemens & Halske Aktiengesellschaft,

Berlin und München,
München 2, Wittelsbacherplatz 2Berlin and Munich,
Munich 2, Wittelsbacherplatz 2

Dr. Heinz Henker, München,
ist als Erfinder genannt wordenDr. Heinz Henker, Munich,
has been named as the inventor

zweckmäßig, den Halbleitergrundkristall allseitig in der angegebenen Weise zu dotieren, besonders dann, wenn die Dotierung aus der Gasphase oder aus einer Flüssigkeit, beispielsweise mittels Elektrolyse, durchgeführt wird. In diesem Fall muß die gegenüberliegende Seite zunächst wieder abgetragen werden, bis das Halbleitergrundmaterial mit der ursprünglichen Dotierung, beispielsweise Intrinsicleitung, wieder freigelegt ist, bevor dort die Gegenelektrode, insbesondere der Kollektor, z. B. durch Legierung und/oder in Form einer Sperr-Randschicht aufgebracht wird.It is advisable to dope the semiconductor base crystal on all sides in the specified manner, especially if if the doping is carried out from the gas phase or from a liquid, for example by means of electrolysis will. In this case, the opposite side must first be removed again, until the semiconductor base material with the original doping, e.g. intrinsic line, is exposed again before there the counter electrode, in particular the collector, z. B. by alloy and / or is applied in the form of a barrier edge layer.

An Hand der Zeichnung, in der eine Ausführungsform der nach dem Verfahren nach der Erfindung hergestellten Halbleiteranordnung beispielsweise dargestellt ist, sei der Erfindungsgedanke näher erläutert.With reference to the drawing, in which an embodiment of the method according to the invention Manufactured semiconductor arrangement is shown for example, the inventive concept will be explained in more detail.

1 bedeutet einen Halbleitergrundkristall aus intrinsic-leitendem Germanium oder Silizium. Dieser wird in einem ersten Arbeitsgang aus der Gasphase mit Bor dotiert. Hierdurch entsteht allseits auf dem Halbleitergrundkristall eine p-Schicht. In einem zweiten Arbeitsgang wird die untere Oberfläche 2 des Halbleitergrundkristalls abgeschliffen und/oder abgeätzt, so daß die p-leitende Zone verschwindet und die i-leitende Grundsubstanz wieder freigelegt ist. In einem anderen Arbeitsgang wird auf der p-leitenden Oberfläche 3 eine Legierungspille aus dem Grundmaterial, entweder Germanium oder Silizium, mit Bor und Antimon einlegiert. Hierbei löst sich die p-Zone 3 an der Legierungsstelle zunächst wieder auf. Beim langsamen Abkühlen scheidet sie sich als p-Zone (wegen des großen Verteilungskoeffizienten des Bors) wieder aus, wobei sie sich räumlich in das Innere des Halbleitergrundkristalls hinein verlagert.1 means a semiconductor base crystal made of intrinsic conductive Germanium or silicon. This is removed from the gas phase in a first step Boron doped. This creates a p-layer on all sides of the semiconductor base crystal. In a second In the process, the lower surface 2 of the semiconductor base crystal is ground and / or etched off, so that the p-conductive zone disappears and the i-conductive basic substance is exposed again. In In another operation, an alloy pill is made from the base material on the p-conductive surface 3, either germanium or silicon, alloyed with boron and antimony. The p-zone 3 initially reappears at the alloy site. During slow cooling, it separates as a p-zone (because of the large distribution coefficient of boron), whereby they are spatially located in the interior of the Semiconductor base crystal shifted into it.

8O9 5W4358O9 5W435

Sobald die Zone p' die gewünschte Dicke erreicht hat und außerdem das Bor weitgehend verbraucht ist, wird der übrige Teil der Legierungspille schneller abgekühlt, wobei ein vorwiegend mit Antimon dotierter und infolgedessen η-leitender Teil entsteht. Zum Schluß wird in bekannter Weise eine ringförmige Basiselektrode 5 aus Gold auf die p-leitende, mit Bor dotierte Oberfläche, besonders durch Legieren, aufgebracht. Auf der gegenüberliegenden Oberfläche 2 wird in bekannter Weise Antimon einlegiert, so daß dort eine n-Zone 6 entsteht. Man erhält auf diese Weise einen n-p-i-Transistor. Damit die einzelnen Dotierungszonen, insbesondere die Zone p', eine gewünschte Ausdehnung und außerdem eine gewünschte Höhe der Dotierung bekommt, ist es erforderlich, der Legierungspille 4 von vornherein eine entsprechende Zusammensetzung der Teile Halbleitergrundmaterial, Bor und Antimon zu geben. Unter Umständen kann hierbei das Akzeptormaterial, im vorliegenden Fall Bor, auch ganz fehlen, so daß auch mit einem Donatormaterial allein zu legieren ist.As soon as the zone p 'has reached the desired thickness and the boron has also been largely used up, the remaining part of the alloy pill is cooled more quickly, with one predominantly doped with antimony and as a result η-conductive part arises. Finally, in a known manner, an annular Base electrode 5 made of gold on the p-conductive, boron-doped surface, especially by alloying, applied. On the opposite surface 2 antimony is alloyed in a known manner, so that an n-zone 6 arises there. In this way an n-p-i transistor is obtained. So that the individual Doping zones, in particular the zone p ', a desired extent and also a desired one The amount of doping, it is necessary to give the alloy pill 4 a corresponding one from the outset Composition of the parts to give semiconductor base material, boron and antimony. May be here the acceptor material, in the present case boron, is also completely absent, so that even with a donor material is to be alloyed alone.

Claims (4)

Patentansprüche:Patent claims: 1. Verfahren zur Herstellung einer Halbleiteranordnung mit mehreren Übergängen zwischen Zonen unterschiedlichen Leitungstyps, z. B. Flächentransistoren, durch Einlegierung von Aktivatormaterialien mit unterschiedlichem Verteilungs- und/oder Diffusionskoeffizienten, dadurch gekennzeichnet, daß die Oberfläche des Halbleitergrundkri stalls vor dem Einlegieren der Aktivatormaterialien mit Donator- oder Akzeptormaterial, insbesondere durch Diffusion oder Legierung, dotiert wird und dieses Aktivatormaterial so gewählt wird, daß es sich bei Rekristallisation zunächst bevorzugt abscheidet.1. A method of manufacturing a semiconductor device with multiple junctions between Zones of different line types, e.g. B. surface transistors, by alloying activator materials with different distribution and / or diffusion coefficients, characterized in that that the surface of the semiconductor base stalls before the alloying of the activator materials with donor or acceptor material, in particular by diffusion or alloy, is doped and this activator material is chosen so that it occurs during recrystallization initially preferentially separates. 2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Einlegierung des Donator-Akzep tor-Gemisches mit verschiedener Abkühlungsgeschwindigkeit, insbesondere einer langsamen und darauffolgenden schnelleren Abkühlungsgeschwindigkeit vor sich geht, so daß auf Grund der Verschiedenheit der Verteilungskoeffizienten deren Komponenten eine Entmischung der Komponenten erzielt wird.2. The method according to claim 1, characterized in that the alloy of the donor acceptance tor mixture with different cooling rates, especially a slow one and subsequent faster cooling rate going on, so that due to the difference in the distribution coefficients of their components results in a segregation of the components is achieved. 3. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß der Halbleitergrundkristall zunächst allseitig einheitlich mit der einen Störstellenart dotiert wird und dann anschließend die auf diese Weise dotierte Schicht an den unerwünschten Stellen durch mechanische und/oder chemische und/oder elektrochemische Mittel wieder entfernt wird, so daß an dieser Stelle bzw. diesen Stellen die ursprüngliche Halbleitergrundsubstanz wieder freigelegt ist und in gewünschter Weise mit einem Kollektor od. dgl. versehen werden kann, beispielsweise durch Legierung und/oder Erzeugung einer sperrenden Randschicht.3. The method according to claim 1 or 2, characterized in that the semiconductor base crystal is initially doped uniformly on all sides with one type of impurity and then subsequently the in this way doped layer at the undesired locations by mechanical and / or chemical and / or electrochemical agent is removed again, so that at this point or this Make the original semiconductor base substance is exposed again and in the desired manner Can be provided with a collector or the like, for example by alloying and / or Creation of a blocking surface layer. 4. Verfahren nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, daß zur Erzeugung der Zonenfolge n-p-i Bor, Aluminium und/oder Gallium als Akzeptor benutzt wird.4. The method according to any one of claims 1 to 3, characterized in that for generating the Zone sequence n-p-i boron, aluminum and / or gallium is used as an acceptor. Hierzu 1 Blatt Zeichnungen1 sheet of drawings © 809 580/435 7.58© 809 580/435 7.58
DES44639A 1954-08-05 1955-07-06 A method for producing a semiconductor device with several UEbergaengen, e.g. B. surface transistors Pending DE1035787B (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
DES40325A DE1036393B (en) 1954-08-05 1954-08-05 Process for the production of two p-n junctions in semiconductor bodies, e.g. B. area transistors
DES44639A DE1035787B (en) 1954-08-05 1955-07-06 A method for producing a semiconductor device with several UEbergaengen, e.g. B. surface transistors
FR1131582D FR1131582A (en) 1954-08-05 1955-08-05 Semiconductor arrangement with p-n passage, preferably transitor
CH346617D CH346617A (en) 1954-08-05 1956-05-02 Process for the production of a semiconductor arrangement with a plurality of junctions between zones of different conductivity types
FR70726D FR70726E (en) 1954-08-05 1956-06-25 Semiconductor arrangement with p-n passage preferably transitor
GB2108756A GB841195A (en) 1954-08-05 1956-07-06 Improvements in or relating to semi-conductor crystals and processes in the production thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DES40325A DE1036393B (en) 1954-08-05 1954-08-05 Process for the production of two p-n junctions in semiconductor bodies, e.g. B. area transistors
DES44639A DE1035787B (en) 1954-08-05 1955-07-06 A method for producing a semiconductor device with several UEbergaengen, e.g. B. surface transistors

Publications (1)

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DE1035787B true DE1035787B (en) 1958-08-07

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DES40325A Pending DE1036393B (en) 1954-08-05 1954-08-05 Process for the production of two p-n junctions in semiconductor bodies, e.g. B. area transistors
DES44639A Pending DE1035787B (en) 1954-08-05 1955-07-06 A method for producing a semiconductor device with several UEbergaengen, e.g. B. surface transistors

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DES40325A Pending DE1036393B (en) 1954-08-05 1954-08-05 Process for the production of two p-n junctions in semiconductor bodies, e.g. B. area transistors

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CH (1) CH346617A (en)
DE (2) DE1036393B (en)
FR (2) FR1131582A (en)
GB (1) GB841195A (en)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1093021B (en) * 1959-01-24 1960-11-17 Telefunken Gmbh Pnip or npin drift transistor for high frequencies
DE1094886B (en) * 1958-08-27 1960-12-15 Siemens Ag Semiconductor arrangement with collector electrode, especially transistor for high frequencies and high power dissipation
DE1104070B (en) * 1959-01-27 1961-04-06 Siemens Ag Method for producing a semiconductor triode having an intrinsic or nearly intrinsic zone
DE1124155B (en) * 1959-07-04 1962-02-22 Telefunken Patent Method of manufacturing a nipin transistor
DE1130932B (en) * 1959-05-29 1962-06-07 Shockley Transistor Corp Process for the production of small-area pn junctions in semiconductor bodies of a conductivity type of semiconductor arrangements, e.g. B. diodes or transistors
DE1149460B (en) * 1959-10-19 1963-05-30 Rca Corp Electrical semiconductor arrangement with an intrinsic crystal made of cadmium sulfide, cadmium selenide, zinc sulfide, zinc selenide or zinc oxide
DE1153460B (en) * 1959-01-28 1963-08-29 Siemens Ag Method for manufacturing and contacting a semiconductor device
DE1158179B (en) * 1956-09-05 1963-11-28 Int Standard Electric Corp Drift transistor and method for making it
DE1166936B (en) * 1960-11-01 1964-04-02 Philips Nv Method for manufacturing a semiconductor device
DE1173188B (en) * 1959-12-21 1964-07-02 Hitachi Ltd Method for manufacturing a semiconductor component
DE1184869B (en) * 1957-11-29 1965-01-07 Comp Generale Electricite Controlled semiconductor power rectifier with four zones of alternating conductivity types
DE1208012B (en) * 1959-08-06 1965-12-30 Telefunken Patent Flat transistor for high frequencies with a limitation of the emission of the emitter and method of manufacturing
DE1232264B (en) * 1961-02-20 1967-01-12 Philips Nv Method for manufacturing a semiconductor component
DE1258983B (en) * 1961-12-05 1968-01-18 Telefunken Patent Method for producing a semiconductor arrangement with an epitaxial layer and at least one pn junction
DE1288687B (en) * 1957-06-06 1969-02-06 Ibm Deutschland Process for the production of a surface transistor with an alloyed electrode pill, from which, during alloying, contaminants of different diffusion coefficients are diffused into the basic semiconductor body
DE1489031B1 (en) * 1963-11-08 1972-01-05 Ibm Transistor having a wafer-shaped semiconductor body and method for its manufacture

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE569934A (en) * 1958-12-18
NL298354A (en) * 1963-03-29

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1158179B (en) * 1956-09-05 1963-11-28 Int Standard Electric Corp Drift transistor and method for making it
DE1288687B (en) * 1957-06-06 1969-02-06 Ibm Deutschland Process for the production of a surface transistor with an alloyed electrode pill, from which, during alloying, contaminants of different diffusion coefficients are diffused into the basic semiconductor body
DE1184869B (en) * 1957-11-29 1965-01-07 Comp Generale Electricite Controlled semiconductor power rectifier with four zones of alternating conductivity types
DE1094886B (en) * 1958-08-27 1960-12-15 Siemens Ag Semiconductor arrangement with collector electrode, especially transistor for high frequencies and high power dissipation
DE1093021B (en) * 1959-01-24 1960-11-17 Telefunken Gmbh Pnip or npin drift transistor for high frequencies
DE1104070B (en) * 1959-01-27 1961-04-06 Siemens Ag Method for producing a semiconductor triode having an intrinsic or nearly intrinsic zone
DE1153460B (en) * 1959-01-28 1963-08-29 Siemens Ag Method for manufacturing and contacting a semiconductor device
DE1130932B (en) * 1959-05-29 1962-06-07 Shockley Transistor Corp Process for the production of small-area pn junctions in semiconductor bodies of a conductivity type of semiconductor arrangements, e.g. B. diodes or transistors
DE1124155B (en) * 1959-07-04 1962-02-22 Telefunken Patent Method of manufacturing a nipin transistor
DE1208012C2 (en) * 1959-08-06 1966-10-20 Telefunken Patent Flat transistor for high frequencies with a limitation of the emission of the emitter and method of manufacture
DE1208012B (en) * 1959-08-06 1965-12-30 Telefunken Patent Flat transistor for high frequencies with a limitation of the emission of the emitter and method of manufacturing
DE1149460B (en) * 1959-10-19 1963-05-30 Rca Corp Electrical semiconductor arrangement with an intrinsic crystal made of cadmium sulfide, cadmium selenide, zinc sulfide, zinc selenide or zinc oxide
DE1173188B (en) * 1959-12-21 1964-07-02 Hitachi Ltd Method for manufacturing a semiconductor component
DE1166936B (en) * 1960-11-01 1964-04-02 Philips Nv Method for manufacturing a semiconductor device
DE1232264B (en) * 1961-02-20 1967-01-12 Philips Nv Method for manufacturing a semiconductor component
DE1258983B (en) * 1961-12-05 1968-01-18 Telefunken Patent Method for producing a semiconductor arrangement with an epitaxial layer and at least one pn junction
DE1489031B1 (en) * 1963-11-08 1972-01-05 Ibm Transistor having a wafer-shaped semiconductor body and method for its manufacture

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DE1036393B (en) 1958-08-14
FR70726E (en) 1959-07-10
GB841195A (en) 1960-07-13
CH346617A (en) 1960-05-31
FR1131582A (en) 1957-02-25

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