DE1544205C3 - Method for doping semiconductor material - Google Patents

Description

3 4

Doped layers produced by pyrolytic decomposition are particularly suitable. For the tin, zinc or tin-doped silicon dioxide layers doping of gallium arsenide platelets, it proves to be provided. As a result of the mixing ratio, this can be particularly advantageous if the tin or zinc level of the doping is varied. Since it is used in the doped silicon dioxide layers, 5 mixture of zinc diethyl with silicon tetraethyl ester, which can result from pyrolytic decomposition of a suitable compound (zinc diethyl ester), ver silicon tetraethyl ester produced and on the ( Hl) - to store the zinc diet, the gallium arsenide platelet is deposited and the silicon tetraethyl ester is stored in two separate recipes. io patients. If different amounts of nitrogen These measures allow production to flow through both liquids in a controlled manner, then doped silicon dioxide layers are trolled. The desired mixing ratio is only obtained in the reaction vessel. In this context, zinc diethyl / silicon tetraethyl ester is prepared, beat, for the production of zinc-doped silicon dioxide diethyl in n-heptane and silicon tetraethyl ester in. To form a carefully dried vessel. This measure prevents gas, for example 92% N ₂ + 8% H ₂ , from being mixed with silicon when zinc diethyl is mixed with silicon 20 tetraethyl ester [Si (C ₂ H ₅ O) ₄ ] at a temperature of tetraethyl ester as a result of a positive heat tone 21 ⁰ C saturated. This mixture is then passed over the gallium of a solid zinc compound (zinc diethyl ester), which is heated to a temperature of about 700 ° C, or arsenide platelets for the separation of moisture. With a gas flow rate and thus no zinc in the pyrolytic silicon of about 125 l / min, a layer of about a layer of dioxide is built in. 25 120 Å / min on the gallium arsenide platelet-the fissured doped layer can be considered as deposited. Tin doping of the deposited mask for subsequent diffusions from the gaseous layer is obtained when a phase is used in the gas flow. The variety of possible uses of the process according to the invention is small amounts (for example 0.5%) tin tetraethyl [Sn (C ₂ H ₅ )]. Zinc-doped layers are obtained by increasing the gaps in 30 by adding n-heptane, which contains some (e.g. 0.1%) of the doped layer as a limit for subsequent zinc diet.

Metallization processes are used. In addition, in FIG. 1 is a gallium arsenide chip 1 darkann the gap-containing, doped layer as provided. The surface of the gallium arsenide plate Mask used for subsequent masked epitaxy is oriented in the (Hl) plane. The gallium arsenide becoming. The invention is coated in the following on the basis of a doped silicon dioxide layer 2. Drawing explained in more detail. It shows the thickness of the layer is about 5000 Å. The SiIi-F i g. 1 is a pyrolytic with a doped silicon dioxide layer 2 is in the (H2) direction of the silicon dioxide layer coated semiconductor body, interspersed with column 3. As shown in the figure too For example, a gallium arsenide crystal, in which 40 can be seen, the plotted columns 3 are in Columns were formed, parallel to each other or each other under a fig. 2 a method for the targeted generation of the angles of 60 ° intersecting directions, both Column in a silicon dioxide layer, with the crystallographic (H2) directions of the F i g. 3 a semiconductor body in which gallium arsenide lamina 1 according to the invention collapse. The very according to two closely adjacent, similarly doped 45 straight and regularly running gaps 3 Zones were created, approximately 0.1μ wide. These gaps arise in FIG. 4 the principle according to the invention of the silicon dioxide layer by sudden heating, used to produce a lateral mung of the arrangement shown to about 800 ° C and pn transistor, are due to the different thermal F i g. 5 the basic procedure based on a 50 expansion coefficient of gallium arsenide and Field effect transistor and silicon dioxide. The gaps also arise when the F i g. 6 to 8 the method according to the invention, on the thickness of the deposited silicon dioxide layer turned to manufacture a unipolar transistor. about 6000 to 7000 Ä reached.

Doped silicon dioxide layers, such as those used in the Die F i g. 2 again shows a gallium arsenide

According to the method according to the invention are used, 55 platelets 1, whose surface is in the (III) plane

is at the same time oriented as an erosion-binding surface cover and that with a silicon dioxide layer 2

layers and is covered as a source material for impurity diffusion. The exaggerated wide in the representation

sion. The doping of the silicon dioxide layer is carried out, channels 4 drawn serve to keep the silicon dioxide

in an apparatus for the pyrolytic decomposition of ziumdioxydschicht occurring column 3 on the

Tetraethyl silicate. For the production of 60 base areas of these channels to be limited. on

Gallium arsenide transistors are particularly zinc, this way, for example, a selection can be made

and layers containing tin as dopants, at which points gaps in the SiIi-

needed. They will be created by adding the appropriate ziumdioxydschicht.

Alkyls produced. The vapor pressures of the metallorga- The F i g. 3 shows, for example, a p-doped

niche compounds of zinc and tin as well as 65 gallium arsenide 5, which is doped with a tin

of the silicon tetraethyl ester are not noticeably covered. Silicon dioxide layer 6 is covered. At the pyro-

divorced. If you add to the silicon tetraethyl lytic deposition, this layer has become a part of it

ester the corresponding organometallic connec- tion gap 7 is formed. With thermal post-treatment

5 6

tin atoms diffuse from silicon dioxide layer 6 between the connections for source 10 and drain 11.

into the semiconductor die 5. Only in the area This structure can also be used according to the invention

of the gap 7, the diffusion does not take place. As the gap 7 method can be made. First of all, the

is extremely narrow, arise in the p-type gallium arsenide platelets 5 again on pyrolytic

the gallium arsenide platelets 5, an Sn-doped silicon dioxide layer 6 extremely narrowly

adjacent, two η-conductive areas. applied with a gap 7. On the silica

In a corresponding manner, FIG. 4 the lower layer 6 is also a very thin insulating layer

position of a lateral npn transistor. It creates silicon dioxide layer 12, which is also weakly doped

by tin diffusion from the silicon dioxide layer 6 can be. Then the diffusion takes place

in which a gap 7 has formed. For a better con- io source 10 and sink 11. In another working

clocking of the base, which in this case consists of a single gear in the area of the gap 7 on the insulating

p-doped area, it is advisable, after silicon dioxide layer 12, the metallic control elec-

Trode 13 additionally vaporized a little zinc through the gap 7. Since the resulting silicon

the p-conductive gallium arsenide plate 5 diffuses dioxide layer only within the width of the gap 7

to have dated. In this way, when this 15 is thin, you get a low-capacitance control elec-

Place a p + -zone 8. trode. The mode of operation of the arrangement exists

In Fig. 5 shows a field effect transistor. now that with the help of an electric field Also in the production of field effect transistors between the control electrode 13 and the interior of the you need two regions doped in the same direction (additional free charge source for gallium arsenide platelets and sink), which are drawn a very small distance 20 carriers into the area of the current path own each other. It is in the present and thus its conductivity is increased. The elek trap around a so-called surface field effect- Irish field is generated by a corresponding voltage transistor, in which a current-increasing control voltage of the control electrode 13 against one with the Galliumnung is used. Connection for the source connected in the gallium arsenide plate arsenide plate Chen 5, two η-doped zones are diffused in. The 25 10 set up.

one η-doped zone is used as the source 10 and the other die F i g. 6 to 8 show another example for

used as sink 11. The current between source 10 manufacture of, unipolar transistors. First of all,

and sink 11 goes through two barrier layers as in FIG. 6 shown, on the gallium arsenide plate

through. The barrier layers are used here but 5 again an Sn-doped silicon dioxide

not to control the current. You only provide 30 layer 6 with a gap 7 applied. In one

the transitions between the not shown, as a subsequent epitaxial growth process

Connections used metal films and the gallium- this gap 7 with a on the gallium arsenide-

arsenide platelets. They result as such web 14 which only builds up platelets 5 and consists of GaI-

incidentally, due to the diffused η-doped lium arsenide, filled up. After the subsequent

Zones. These are necessary in order to obtain two n-doped diffusion (see FIG. 8) between the two

Connections used metal films and the gallium zones 15 and 16, their fronts in the epitaxial

Arsenide platelet barrier layer-free contacts to er web 14 have an extremely small mutual spacing

pass. The surface layer serves as the current path.

1 sheet of drawings

Claims (3)

1 2 Patent claims ^ of the gas phase, the impurity atoms can only in the area of the recesses in the basic semiconductor 1. Process for doping semiconductor bodies occur. In the case of dissusion from a doped material through diffusion of impurities from a protective layer, on the other hand, the impurity atoms diffuse applied to the semiconductor material, only in the area outside the recesses oriented layer, in the gap-shaped recesses in the semiconductor base body. The nature of the educated due to the fact that the dimensions of the masks are characterized by the fact that, as a doped layer, one with the doped and non-doped regions is relative a smaller coefficient of thermal expansion are large. Requires the structure of the as that of the semiconductor material io components masks with very small openings is chosen and the gap-shaped recesses through openings, d. H. Recesses of an order of magnitude sudden warming may be formed. of tenths of a μ, or correspondingly small distances 2. The method according to claim 1, characterized in that between the recesses, these can be characterized in that tin-doped or zinc-doped silicon 15 is not used at all or not with sufficient exact dioxide layers for tin-doping a gallium small dimensions with the known method arsenide platelets that produce through speed and reproducibility,
Pyrolytic decomposition of a suitable mixture For this reason, a process has already been proposed for the production of tin tetraethyl or zinc diethyl with silicon, and masks suitable for diffusion from the gas phase, which are very suitable for the gallium arsenide platelet. 20 narrow and elongated recesses. point. This method consists in that the 3. The method according to claim 2, characterized in that the semiconductor base body has a protective layer over- Λ ° \ draws that for the production of the zinc-doped is drawn, their thermal expansion coefficient Silicon dioxide layers, zinc diethyl and silicon, are smaller than that of the semiconductor crystal. With anschlietraäthylester stored in separate recipients and the desired mixed layer cracks, in the area of which there is a diffusion of ratio is only formed in the reaction vessel. Can meet impurity atoms. That way it is thus it is possible to produce extremely narrow, doped zones in a semiconductor base plate. 30 The diffusion of impurities from doped cover layers offers compared to diffusion from the gas phase some major advantages. The semiconductor upper The invention relates to a method for doping the surface is protected from harmful influences and changes in semiconductor material by diffusion of disturbances, in particular by the so-called outer fabrics from a surface erosion on the semiconductor material and the doping is easily applied, doped layer in the gap-shaped controllable. In many applications, however, recesses have to be formed. this diffusion process, in turn, has the disadvantage, a known process for the production of which also the verpn transitions in semiconductor crystals during diffusion from the gas phase consists in the turned masks. This disadvantage consists in diffusion of impurity atoms at an elevated temperature 40, as already indicated, in the fact that, for example, in the solid semiconductor crystal. What is essential in this smallest process, a doping in its area, is that a melting of the crystal or of the openings in the cover layer does not occur with a width of an alloy. The impurity atoms of the order of magnitude of a tenth of a μ and a length _r impurity in the semiconductor crystal of, for example, a few millimeters, are difficult to produce as so-called donors and 45. The accuracy and reproducibility acceptors of the semiconductor surface either as the availability of the method is in question. This gas is offered in a partial vacuum or problems turn out to be made up for, in particular with the masses in the form of a connection to the surface on the production of semiconductor components. The entire arrangement will be part for one. a certain period of time at temperatures below 50. The invention is now based on the object heated to the melting point of the semiconductor material. to specify a method that has the disadvantages mentioned In the process, the impurity atoms diffuse into the semiconductor and avoid the production of semiconductor building material one. The depth of diffusion depends on the elements with extremely small spacings alike Surface concentration, temperature and doped areas allowed. This task yields Exposure time. 55 are often involved in the manufacture of integrated semiconductor-offs the multitude of semiconductor components to be produced, especially if in a semiconductor arrangement the task results, in each case only in the base body with several similar components one or more specific areas of the similar DO semiconductor base body, separated according to a defined pattern a diffusion of disrupted areas should be formed. Continue to allow atoms. This task is known in the 60's this task is in making lateral tran-fashion solved in that the surface of the semisistors, unipolar transistors and in particular field conductor base body made with an appropriately trained effect transistor. Deten mask is provided. In order to produce the according to the invention, the object set is Masks, the surface of the semiconductor base is solved by using such a doped layer body with a suitable material 65 with a smaller coefficient of thermal expansion than Covered protective layer, which is chosen by photoetching that of the semiconductor material and with the corresponding to the desired mask shape the gap-shaped recesses by sudden Recesses is provided. Formed during diffusion from heating.