DE10345395A1 - Halbleitermodul und Verfahren zur Herstellung eines Halbleitermoduls - Google Patents

Halbleitermodul und Verfahren zur Herstellung eines Halbleitermoduls Download PDF

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Publication number
DE10345395A1
DE10345395A1 DE10345395A DE10345395A DE10345395A1 DE 10345395 A1 DE10345395 A1 DE 10345395A1 DE 10345395 A DE10345395 A DE 10345395A DE 10345395 A DE10345395 A DE 10345395A DE 10345395 A1 DE10345395 A1 DE 10345395A1
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Prior art keywords
semiconductor module
semiconductor
producing
provides
present
Prior art date
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Granted
Application number
DE10345395A
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DE10345395B4 (de
Inventor
Harry Hedler
Thorsten Meyer
Roland Irsigler
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Polaris Innovations Ltd
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Infineon Technologies AG
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Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10345395A priority Critical patent/DE10345395B4/de
Priority to PCT/EP2004/010893 priority patent/WO2005034235A2/de
Publication of DE10345395A1 publication Critical patent/DE10345395A1/de
Priority to US11/364,770 priority patent/US7646090B2/en
Application granted granted Critical
Publication of DE10345395B4 publication Critical patent/DE10345395B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

Die vorliegende Erfindung stellt ein Halbleitermodul bereit mit: einer Halbleitereinrichtung (10), welche eine Kontakteinrichtung (11) zur elektrischen Kontaktierung einer Anschlusseinrichtung (17; 20) über eine Umverdrahtungseinrichtung (15, 15', 15'') aufweist; und einer Trägereinrichtung (12, 13, 14) zur mechanischen Kopplung der Halbleitereinrichtung (10) an eine Anschlusseinrichtung (17), wobei die Trägereinrichtung (12, 13, 14) einen Gradienten zwischen einem ersten Elastizitätsmodul an der Halbleitereinrichtung (10) und einem zweiten, höheren Elastizitätsmodul an der Anschlusseinrichtung (17; 20) aufweist. Die vorliegende Erfindung stellt ebenfalls ein Verfahren zur Herstellung eines Halbleitermoduls bereit.
DE10345395A 2003-09-30 2003-09-30 Halbleitermodul und Verfahren zur Herstellung eines Halbleitermoduls Expired - Fee Related DE10345395B4 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE10345395A DE10345395B4 (de) 2003-09-30 2003-09-30 Halbleitermodul und Verfahren zur Herstellung eines Halbleitermoduls
PCT/EP2004/010893 WO2005034235A2 (de) 2003-09-30 2004-09-29 Halbleitermodul mit trägereinrichtung und verfahren zur herstellung des halbleitermoduls
US11/364,770 US7646090B2 (en) 2003-09-30 2006-02-28 Semiconductor module for making electrical contact with a connection device via a rewiring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10345395A DE10345395B4 (de) 2003-09-30 2003-09-30 Halbleitermodul und Verfahren zur Herstellung eines Halbleitermoduls

Publications (2)

Publication Number Publication Date
DE10345395A1 true DE10345395A1 (de) 2005-05-04
DE10345395B4 DE10345395B4 (de) 2006-09-14

Family

ID=34399073

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DE10345395A Expired - Fee Related DE10345395B4 (de) 2003-09-30 2003-09-30 Halbleitermodul und Verfahren zur Herstellung eines Halbleitermoduls

Country Status (3)

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US (1) US7646090B2 (de)
DE (1) DE10345395B4 (de)
WO (1) WO2005034235A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100834442B1 (ko) * 2007-01-16 2008-06-04 삼성전자주식회사 증가된 결합 신뢰성을 갖는 반도체 모듈들
JP4121543B1 (ja) * 2007-06-18 2008-07-23 新光電気工業株式会社 電子装置
US9030019B2 (en) 2010-12-14 2015-05-12 Infineon Technologies Ag Semiconductor device and method of manufacture thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6242799B1 (en) * 1997-11-18 2001-06-05 Shinko Electric Industries Co., Ltd. Anisotropic stress buffer and semiconductor device using the same
EP1143515A2 (de) * 2000-04-06 2001-10-10 Shinko Electric Industries Co. Ltd. Verdrahtungssubstrat, seine Herstellung und Halbleiterbauteil
US6313532B1 (en) * 1997-06-06 2001-11-06 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing the same
DE10059178A1 (de) * 2000-11-29 2002-06-13 Siemens Production & Logistics Verfahren zur Herstellung von Halbleitermodulen sowie nach dem Verfahren hergestelltes Modul
US20020079575A1 (en) * 2000-12-25 2002-06-27 Hiroshi Hozoji Semiconductor module
US6624504B1 (en) * 1999-10-29 2003-09-23 Hitachi, Ltd. Semiconductor device and method for manufacturing the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6211572B1 (en) * 1995-10-31 2001-04-03 Tessera, Inc. Semiconductor chip package with fan-in leads
JP4024958B2 (ja) * 1999-03-15 2007-12-19 株式会社ルネサステクノロジ 半導体装置および半導体実装構造体

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6313532B1 (en) * 1997-06-06 2001-11-06 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing the same
US6242799B1 (en) * 1997-11-18 2001-06-05 Shinko Electric Industries Co., Ltd. Anisotropic stress buffer and semiconductor device using the same
US6624504B1 (en) * 1999-10-29 2003-09-23 Hitachi, Ltd. Semiconductor device and method for manufacturing the same
EP1143515A2 (de) * 2000-04-06 2001-10-10 Shinko Electric Industries Co. Ltd. Verdrahtungssubstrat, seine Herstellung und Halbleiterbauteil
DE10059178A1 (de) * 2000-11-29 2002-06-13 Siemens Production & Logistics Verfahren zur Herstellung von Halbleitermodulen sowie nach dem Verfahren hergestelltes Modul
US20020079575A1 (en) * 2000-12-25 2002-06-27 Hiroshi Hozoji Semiconductor module

Also Published As

Publication number Publication date
WO2005034235A3 (de) 2005-11-24
DE10345395B4 (de) 2006-09-14
US20060177964A1 (en) 2006-08-10
WO2005034235A2 (de) 2005-04-14
US7646090B2 (en) 2010-01-12

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Owner name: QIMONDA AG, 81739 MUENCHEN, DE

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Owner name: INFINEON TECHNOLOGIES AG, DE

Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE

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R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee