DE10343084A1 - Halbleiterwafer und Verfahren zu dessen Vereinzelung - Google Patents

Halbleiterwafer und Verfahren zu dessen Vereinzelung Download PDF

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Publication number
DE10343084A1
DE10343084A1 DE2003143084 DE10343084A DE10343084A1 DE 10343084 A1 DE10343084 A1 DE 10343084A1 DE 2003143084 DE2003143084 DE 2003143084 DE 10343084 A DE10343084 A DE 10343084A DE 10343084 A1 DE10343084 A1 DE 10343084A1
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DE
Germany
Prior art keywords
trench
cavity
filled
electrically inactive
inactive material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE2003143084
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English (en)
Other versions
DE10343084B4 (de
Inventor
Markus Zundel
Rudolf Zelsacher
Hermann Peri
Dietmar Kotz
Achim Knapp
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE2003143084 priority Critical patent/DE10343084B4/de
Publication of DE10343084A1 publication Critical patent/DE10343084A1/de
Application granted granted Critical
Publication of DE10343084B4 publication Critical patent/DE10343084B4/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Abstract

Die Erfindung betrifft einen Halbleiterwafer (1), bei dem zu vereinzelnde Chips (3) längs ihres Randes (4) mit elektrisch nicht aktiven Trenches (5) versehen sind. Diese Trenches (5) werden vorzugsweise zusammen mit Trenches (13) des Zellenfeldes (6) hergestellt.
DE2003143084 2003-09-17 2003-09-17 Halbleiterwafer aus einer Vielzahl von durch Vereinzelungsrahmen voneinander zu trennenden Chips Expired - Lifetime DE10343084B4 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE2003143084 DE10343084B4 (de) 2003-09-17 2003-09-17 Halbleiterwafer aus einer Vielzahl von durch Vereinzelungsrahmen voneinander zu trennenden Chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2003143084 DE10343084B4 (de) 2003-09-17 2003-09-17 Halbleiterwafer aus einer Vielzahl von durch Vereinzelungsrahmen voneinander zu trennenden Chips

Publications (2)

Publication Number Publication Date
DE10343084A1 true DE10343084A1 (de) 2005-05-04
DE10343084B4 DE10343084B4 (de) 2006-07-06

Family

ID=34398786

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2003143084 Expired - Lifetime DE10343084B4 (de) 2003-09-17 2003-09-17 Halbleiterwafer aus einer Vielzahl von durch Vereinzelungsrahmen voneinander zu trennenden Chips

Country Status (1)

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DE (1) DE10343084B4 (de)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7816229B2 (en) 2008-09-30 2010-10-19 Infineon Technologies Austria Ag Semiconductor device with channel stop trench and method
US9484451B2 (en) 2007-10-05 2016-11-01 Vishay-Siliconix MOSFET active area and edge termination area charge balance
US9614043B2 (en) 2012-02-09 2017-04-04 Vishay-Siliconix MOSFET termination trench
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
US9882044B2 (en) 2014-08-19 2018-01-30 Vishay-Siliconix Edge termination for super-junction MOSFETs
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8803297B2 (en) 2012-08-10 2014-08-12 Infineon Technologies Ag Semiconductor device including a stress relief layer and method of manufacturing
US9508596B2 (en) 2014-06-20 2016-11-29 Vishay-Siliconix Processes used in fabricating a metal-insulator-semiconductor field effect transistor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4437581C2 (de) * 1994-10-20 1996-08-08 Siemens Ag Verfahren zur Herstellung einer Festwertspeicherzellenanordnung mit vertikalen MOS-Transistoren
US6368943B1 (en) * 1996-05-14 2002-04-09 Sony Corporation Semiconductor method of manufacture

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4437581C2 (de) * 1994-10-20 1996-08-08 Siemens Ag Verfahren zur Herstellung einer Festwertspeicherzellenanordnung mit vertikalen MOS-Transistoren
US6368943B1 (en) * 1996-05-14 2002-04-09 Sony Corporation Semiconductor method of manufacture

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10084037B2 (en) 2007-10-05 2018-09-25 Vishay-Siliconix MOSFET active area and edge termination area charge balance
US9484451B2 (en) 2007-10-05 2016-11-01 Vishay-Siliconix MOSFET active area and edge termination area charge balance
US8138581B2 (en) 2008-09-30 2012-03-20 Infineon Technologies Austria Ag Semiconductor device with channel stop trench and method
DE102009061851B3 (de) 2008-09-30 2022-01-20 Infineon Technologies Austria Ag Halbleiterbauelement mit Kanalstoppgraben
DE102009042711B4 (de) * 2008-09-30 2020-10-01 Infineon Technologies Austria Ag Halbleiterbauelemente mit Kanalstoppgraben und Verfahren
US7816229B2 (en) 2008-09-30 2010-10-19 Infineon Technologies Austria Ag Semiconductor device with channel stop trench and method
US9614043B2 (en) 2012-02-09 2017-04-04 Vishay-Siliconix MOSFET termination trench
US9935193B2 (en) 2012-02-09 2018-04-03 Siliconix Technology C. V. MOSFET termination trench
US10229988B2 (en) 2012-05-30 2019-03-12 Vishay-Siliconix Adaptive charge balanced edge termination
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
US10283587B2 (en) 2014-06-23 2019-05-07 Vishay-Siliconix Modulated super junction power MOSFET devices
US10340377B2 (en) 2014-08-19 2019-07-02 Vishay-Siliconix Edge termination for super-junction MOSFETs
US9882044B2 (en) 2014-08-19 2018-01-30 Vishay-Siliconix Edge termination for super-junction MOSFETs

Also Published As

Publication number Publication date
DE10343084B4 (de) 2006-07-06

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R071 Expiry of right