DE10338922A8 - Elektrische Diagnoseschaltung sowie Verfahren zum Testen und/oder zur Diagnose einer integrierten Schaltung - Google Patents

Elektrische Diagnoseschaltung sowie Verfahren zum Testen und/oder zur Diagnose einer integrierten Schaltung Download PDF

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Publication number
DE10338922A8
DE10338922A8 DE10338922A DE10338922A DE10338922A8 DE 10338922 A8 DE10338922 A8 DE 10338922A8 DE 10338922 A DE10338922 A DE 10338922A DE 10338922 A DE10338922 A DE 10338922A DE 10338922 A8 DE10338922 A8 DE 10338922A8
Authority
DE
Germany
Prior art keywords
diagnosis
testing
circuit
integrated circuit
electrical diagnostic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE10338922A
Other languages
English (en)
Other versions
DE10338922B4 (de
DE10338922A1 (de
Inventor
Andreas Leininger
Michael GÖSSEL
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10338922.9A priority Critical patent/DE10338922B4/de
Priority to PCT/DE2004/001799 priority patent/WO2005020075A1/de
Priority to US10/568,842 priority patent/US7814384B2/en
Publication of DE10338922A1 publication Critical patent/DE10338922A1/de
Publication of DE10338922A8 publication Critical patent/DE10338922A8/de
Application granted granted Critical
Publication of DE10338922B4 publication Critical patent/DE10338922B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE10338922.9A 2003-08-20 2003-08-20 Elektrische Diagnoseschaltung sowie Verfahren zum Testen und/oder zur Diagnose einer integrierten Schaltung Expired - Fee Related DE10338922B4 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE10338922.9A DE10338922B4 (de) 2003-08-20 2003-08-20 Elektrische Diagnoseschaltung sowie Verfahren zum Testen und/oder zur Diagnose einer integrierten Schaltung
PCT/DE2004/001799 WO2005020075A1 (de) 2003-08-20 2004-08-11 Elektrische diagnoseschaltung sowie verfahren zum testen und/oder zur diagnose einer integrierten schaltung
US10/568,842 US7814384B2 (en) 2003-08-20 2004-08-11 Electrical diagnostic circuit and method for the testing and/or the diagnostic analysis of an integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10338922.9A DE10338922B4 (de) 2003-08-20 2003-08-20 Elektrische Diagnoseschaltung sowie Verfahren zum Testen und/oder zur Diagnose einer integrierten Schaltung

Publications (3)

Publication Number Publication Date
DE10338922A1 DE10338922A1 (de) 2005-03-31
DE10338922A8 true DE10338922A8 (de) 2005-07-28
DE10338922B4 DE10338922B4 (de) 2016-07-14

Family

ID=34201966

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10338922.9A Expired - Fee Related DE10338922B4 (de) 2003-08-20 2003-08-20 Elektrische Diagnoseschaltung sowie Verfahren zum Testen und/oder zur Diagnose einer integrierten Schaltung

Country Status (3)

Country Link
US (1) US7814384B2 (de)
DE (1) DE10338922B4 (de)
WO (1) WO2005020075A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005046588B4 (de) 2005-09-28 2016-09-22 Infineon Technologies Ag Vorrichtung und Verfahren zum Test und zur Diagnose digitaler Schaltungen
US7941722B2 (en) * 2007-06-24 2011-05-10 Texas Instruments Incorporated Testing of integrated circuits using test module
US9766289B2 (en) 2015-10-06 2017-09-19 Nxp Usa, Inc. LBIST debug controller
CN113447799B (zh) * 2020-03-27 2022-06-14 阿里巴巴集团控股有限公司 集成电路、信息收集方法、设备
CN111948511A (zh) * 2020-05-27 2020-11-17 中核武汉核电运行技术股份有限公司 一种仪控卡件故障诊断系统及方法
WO2022042929A1 (de) 2020-08-28 2022-03-03 Sew-Eurodrive Gmbh & Co. Kg Programmierbare signalverarbeitungseinheit und verfahren zum betrieb einer programmierbaren signalverarbeitungseinheit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5574733A (en) * 1995-07-25 1996-11-12 Intel Corporation Scan-based built-in self test (BIST) with automatic reseeding of pattern generator
DE19929546C1 (de) * 1999-06-23 2000-09-07 Michael Goessel Multi-Mode Speicherelement
WO2001038889A1 (en) * 1999-11-23 2001-05-31 Mentor Graphics Corporation Method and apparatus for selectively compacting test responses

Family Cites Families (12)

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Publication number Priority date Publication date Assignee Title
US4503537A (en) * 1982-11-08 1985-03-05 International Business Machines Corporation Parallel path self-testing system
US4601034A (en) * 1984-03-30 1986-07-15 Texas Instruments Incorporated Method and apparatus for testing very large scale integrated memory circuits
US5081626A (en) * 1989-12-08 1992-01-14 Hughes Aircraft Company System for detection and location of events
US5230000A (en) * 1991-04-25 1993-07-20 At&T Bell Laboratories Built-in self-test (bist) circuit
US5831992A (en) * 1995-08-17 1998-11-03 Northern Telecom Limited Methods and apparatus for fault diagnosis in self-testable systems
US5745500A (en) * 1996-10-22 1998-04-28 The United States Of America As Represented By The Secretary Of The Army Built-in self testing for the identification of faulty integrated circuit chips in a multichip module
US5930270A (en) * 1997-07-23 1999-07-27 International Business Machines Corporation Logic built in self-test diagnostic method
US6055660A (en) * 1997-10-02 2000-04-25 International Business Machines Corporation Method for identifying SMP bus transfer errors
US6158033A (en) * 1998-05-08 2000-12-05 S3 Incorporated Multiple input signature testing & diagnosis for embedded blocks in integrated circuits
US6442723B1 (en) * 1999-05-12 2002-08-27 International Business Machines Corporation Logic built-in self test selective signature generation
US6510398B1 (en) * 2000-06-22 2003-01-21 Intel Corporation Constrained signature-based test
US7644333B2 (en) * 2001-12-18 2010-01-05 Christopher John Hill Restartable logic BIST controller

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5574733A (en) * 1995-07-25 1996-11-12 Intel Corporation Scan-based built-in self test (BIST) with automatic reseeding of pattern generator
DE19929546C1 (de) * 1999-06-23 2000-09-07 Michael Goessel Multi-Mode Speicherelement
WO2001038889A1 (en) * 1999-11-23 2001-05-31 Mentor Graphics Corporation Method and apparatus for selectively compacting test responses

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
GARNER,M., MÜLLER,B., SANDWEG,G.: Selbsttest digitaler Schaltungen. München (u.a.): Oldenbourg, 1990, S. 100-117, 140-151
GARNER,M., MÜLLER,B., SANDWEG,G.: Selbsttest digitaler Schaltungen. München (u.a.): Oldenbourg,1990, S. 100-117, 140-151 *
Internetseite "http://www.adobe.com/products/acrobat/readstep2. html" vom 17.12.2001 (rekonstruiert mittels http: 77www.archive.org) *

Also Published As

Publication number Publication date
WO2005020075A1 (de) 2005-03-03
DE10338922B4 (de) 2016-07-14
DE10338922A1 (de) 2005-03-31
US7814384B2 (en) 2010-10-12
US20080263421A1 (en) 2008-10-23

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Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8181 Inventor (new situation)

Inventor name: G?SSEL, MICHAEL, 15831 MAHLOW, DE

Inventor name: LEININGER, ANDREAS, 80469 MUENCHEN, DE

8196 Reprint of faulty title page (publication) german patentblatt: part 1a6
OP8 Request for examination as to paragraph 44 patent law
R016 Response to examination communication
R018 Grant decision by examination section/examining division
R082 Change of representative

Representative=s name: WESTPHAL, MUSSGNUG & PARTNER PATENTANWAELTE MI, DE

R020 Patent grant now final
R082 Change of representative
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee