DE10326804A1 - Method for forming semiconductor chip(s) provides one or more independent semiconductor circuits on semiconductor wafer, with at least one conductive track, extending up to rim of semiconductor circuit - Google Patents

Abstract

Production of semiconductor chip(s) starts with semiconductor wafer (1) with one or more independent semiconductor circuits (2) with at least one conductor track (3) and contact region (13) in rim of circuit, electrically coupled to conductive track. Then wafer is divided into semiconductor chips, each containing independent circuits, so as to expose side face (16) of contact region, which, toether with contact track, are simultaneously structured. Forming of contact region is specified. Independent claims are included for semiconductor chip.

Description

The The present invention relates to a method for producing at least a semiconductor chip and a semiconductor chip.

In usual Semiconductor chips are the contacts through which signals are between different chips exchanged, mounted on top of the chip, on which also the electronic circuits are arranged. Usually The chips are applied to a board so that this Top rests on the board. Depending on the type of package used For example, the chip contacts are provided with a suitable interlayer (e.g. Interposer or intermediate board) on corresponding mating contacts soldered in a circuit board. The signal transmission take over between the chips then embedded in the board printed conductors. All connections between semiconductor circuits thus run on a board embedded Trace.

in this connection is every chip with a different area of the board or circuit board connected. For Each semiconductor chip thus requires at least as large a board surface. on which the semiconductor chip is mounted and electrically contacted. Each area of the board surface can only be used once, if necessary twice under consideration the back of the board.

It would be desirable a more compact, possibly also easier to make connection between semiconductor chips and to achieve a printed circuit board and a more versatile electrical Connection of several building blocks, e.g. Semiconductor chips or printed circuit boards to allow each other.

Of the present invention is based on the object, a contact to enable semiconductor chips from their side edges. In particular, several semiconductor chips are also intended to be directly connected to one another can be connected i.e. without the interposition of a printed circuit board. There are several stacked semiconductor chips also near each other at their side edges be connectable.

• – Bereitstellen eines Halbleiterwafers mit einer oder mit mehreren voneinander unabhängigen Halbleiterschaltungen, mit mindestens einer einer Halbleiterschaltung zugeordneten Leiterbahn sowie mit einem mit der Leiterbahn elektrisch verbundenen Kontaktbereich in einem Randbereich der Halbleiterschaltung und
• – Zerteilen des Wafers in Halbleiterchips, die jeweils die voneinander unabhängigen Halbleiterschaltungen enthalten, wodurch eine Seitenfläche des Kontaktbereichs freigelegt wird.

This object is achieved by a method according to claim 1, comprising the following steps:

• - Providing a semiconductor wafer with one or more independent semiconductor circuits, with at least one conductor circuit associated with a semiconductor circuit and with a contact area electrically connected to the conductor in an edge region of the semiconductor circuit and
• - Dicing the wafer in semiconductor chips, each containing the independent semiconductor circuits, whereby a side surface of the contact area is exposed.

According to the invention, it is provided that a semiconductor chip made with a contact in a side surface, the existence already existing contact area, for contact in a later formed Sidewall of the chip is used when separating a semiconductor chip is partially removed, leaving its remaining part in a side wall of the Semiconductor chips exposed. The exposed side surface of this Contact area can be used for direct electrical connection with another semiconductor chip or with a printed circuit board can be used. conventional a contacting of a manufactured on a semiconductor chip integrated circuit exclusively from the top of the chip ago, on which the circuit was made. An application of planar Techniques even from a side edge is unimaginable. Therefore, lateral contacts occur in semiconductor integrated circuits a not considered.

According to the invention, however is an already made contact area, located on the edge of a for a Semiconductor chip provided portion of a wafer part surface, when singulating, i. Sawing the Wafers cut. The contact is electrically conductive via the conductor track connected to the semiconductor integrated circuit of the chip. The Track leads thus from the centrally located semiconductor circuit to the edge of the chip, where it is electrically connected to the contact area. The conductor track will be like any other conductor of the semiconductor circuit with the help made of planar techniques from the top of the wafer; Even the contact area itself is using conventional Planartechniken made and only when separating the wafer integrated component the chip side surface.

recordable manner is provided that the Contact area and the conductor track are structured at the same time. Hereby, the trace and the contact area become the same Process steps deposited and structured.

• – Ätzen eines Kontaktlochs, das an die Leiterbahn angrenzt, in einer Oberseite des Halbleiterwafers,
• – Aufbringen einer Isolationsschicht, die innerhalb des Kontaktlochs Seitenwände des Kontaktlochs bedeckt, und
• – Einbringen eines elektrisch leitenden Kontaktmaterials in das Kontaktloch.

Alternatively, it is contemplated that the step of fabricating a contact area comprises:

• Etching a contact hole adjacent to the trace in an upper surface of the semiconductor wafer,
• Applying an insulating layer covering inside the contact hole sidewalls of the contact hole, and
• - Introducing an electrically conductive contact material in the contact hole.

in this connection the contact area is made only after production of the conductor track.

Preferably is provided that the Insulating layer is applied so that they are the side walls of the Contact hole, but not the trace in the contact hole covered. In this case, the contact material is selective to the material of the conductor track grown on the substrate material on the inner wall of the contact hole.

• – die Isolationsschicht so aufgebracht wird, daß sie innerhalb des Kontaktlochs Material des Halbleiterwafers und die Leiterbahn bedeckt,
• – daß die Isolationsschicht in einem Bereich der Seitenwand des Kontaktlochs, an den die Leiterbahn angrenzt, rückgeätzt wird und
• – daß in dem rückgeätzten Bereich eine Kontaktfüllung auf das elektrische Kontaktmaterial aufgebracht wird.

Alternatively, it is provided that

• The insulating layer is applied in such a way that it covers material of the semiconductor wafer and the conductor track within the contact hole,
• - That the insulating layer is etched back in a region of the side wall of the contact hole, to which the conductor track, and
• - That in the back-etched area a contact filling is applied to the electrical contact material.

there the deposition of the insulating layer is not selective, so that after the introduction of the electrically conductive contact material initially no conductive connection to the track exists. That's why subsequently the insulating layer in that region of the side wall, to the the track adjoins, etched back. Out viewed from the top view of the wafer, this means that the contact area over a Part of its area cross section until at most is etched back to the underside of the conductor track, wherein the etched back cross section the side edge of the contact area only cuts and surmounted there, where at a greater depth in the substrate through the etching back the Track is exposed again and partially etched. On the thus exposed, to the main area of the wafer parallel surface the etched trace and the etched back contact area then becomes one Contact filling applied, and at most until in height or depth of the top of the track. This ensures that that in vertical direction the contact filling do not reconnect the trace with the surrounding substrate material shorts.

Preferably is provided that on this contact filling an insulation layer is applied. This can be used to replenish the re-etched areas up to the height serve the Waferobersei te. Because the unetched area of the contact area extends to the top of the wafer, the contact area after separating the wafer into the semiconductor chips also to the immediate electrical contacting of the chip to which he belongs, about the Chip top with serve further semiconductor chips or a printed circuit board.

A first preferred embodiment sees before that Contact hole is etched to a bottom of the semiconductor wafer. This will help with the filling the contact hole created a contact area, which also at the Bottom of the chip used for direct contacting of other semiconductor chips can be.

A sees alternative preferred embodiment before that Semiconductor wafer later thinned from its underside is until the contact area from a top of the semiconductor wafer until extends to a bottom of the semiconductor wafer. This embodiment allows a simultaneous vertical contacting of the isolated chip simultaneously on its top and bottom by one and the same Contact area, at the same time a clean filling of the first bottom closed contact hole is made possible. The introduced Contact hole filling is during of thinning of the wafer exposed from below.

Preferably is provided that the Contact area in a sawing frame outside the semiconductor chip is produced and the semiconductor wafer in such a way is divided into semiconductor chips that the contact area when dividing preserved. The so-called saw frame is one on one Semiconductor chip provided frame, the wafer areas, for integrated Semiconductor circuits are provided, each encloses and individually in apart from substrate areas, which are later sawn, also adjustment structures or other structures of the semiconductor circuits may be provided can, which are no longer needed with the isolated chip.

in this connection is preferably provided that a Etched back in a part of the saw frame is made, which is carried out until the contact area protruding from a chip side surface.

alternative it is envisaged that the Contact region made in an edge region of a semiconductor chip partially within and partly outside the framework lies.

The The problem underlying the invention is further achieved by a semiconductor chip according to claim 12 solved. This chip has at least one track, which is up extends to an edge region of the semiconductor chip, as well as at least one Contact area in a side area the semiconductor chip in contact with the conductor track, wherein the contact area from a top of the semiconductor wafer to a bottom of the semiconductor wafer.

alternative The contact area may be from the side surface either only up to Extending top or only to the bottom of the semiconductor chip and a subarea take the top or bottom. Such a chip is from side out and from either the top or the bottom contactable.

Preferably is provided that the Contact area a partial area in a top of the semiconductor chip einnimmmt.

Preferably can also be provided that the Contact area a partial area in a lower side of the semiconductor chip.

Of the Contact area can protrude from the side surface of the chip.

The Conductor of the semiconductor chip is preferably connected to the semiconductor circuit electrically connected to the semiconductor chip. This circuit can be a Logic circuit or a memory circuit, in particular a dynamic random access memory.

The The present invention will be described below with reference to FIGS Figures closer explained. It demonstrate:

the 1 to 8th a method according to the invention according to a first embodiment;

9 a semiconductor chip according to the first embodiment according to the invention;

10 a modification of the first embodiment;

11 the singulation of a semiconductor wafer into a plurality of semiconductor chips;

the 12 to 19 a method according to the invention according to a second embodiment; and

20 a semiconductor chip according to the second embodiment;

the 21 and 22 two alternatives with regard to the deposition of the insulating layer;

the 23 and 24 two alternatives regarding the depth of the contact area and

the 25 and 26 two alternatives regarding the lateral position of the contact area.

In 1 denotes the reference numeral 1 a wafer with fully processed, independent semiconductor circuits 2 which will be included in various semiconductor chips after the wafer is later split. A buried in the substrate trace 3 for example, in 2 is shown, is guided for the corresponding signals to the later chip edge.

The on-chip tracks are already in the design and layout of the Considered semiconductor chips. If necessary, the ESD structures usually provided on contacts and others are also used Circuits considered.

The conductor track 3 may be before, during or after the fabrication of the semiconductor circuit 2 be processed. Through the contact area 13 the manufacture of which will be described in the following and which is about the conductor track with the semiconductor circuit 2 is electrically connected, an uppermost metallization or even a deeper Metallisierungsebene can be contacted electrically. This is a significant advantage of lateral contacts compared to conventional contacts on the chip top, all of which must be led out via via contacts to the topmost metallization layer.

According to the first embodiment, the contacts in the saw frame 4 (Kerf) of the semiconductor chip, that is, a region of approximately 100 μm to 1 mm wide outside the semiconductor active circuit region, which only contains test structures during processing and which is omitted after dicing the wafer. When manufacturing the contacts in this sawing frame, it should be noted that the portion of the sawing frame with the lateral contact will remain later during dicing.

thanks its shallow depth carries the contact on the side hardly. More precisely, its width is parallel to the chip edge, for example, 500 microns or less, in particular 140 μm or less, its length perpendicular to the chip edge 140 μm or less, for example, about 100 μm, and its depth 140 μm or less, for example, about 100 microns. Corresponding ver enlarged lateral contact does not affect the effective chip area. The production the contact is made from the wafer top.

First, an etch mask for etching the contact holes on the chip edge is produced by known methods. Depending on the depth of the contact hole to be etched, a photoresist layer, possibly a special photoresist for deep etch depths, is first applied and patterned photolithographically by known methods. At deeper etch depths, it may be necessary to apply a hard mask material, such as Si ₃ N ₄ , SiO ₂ , SiON, BSG (borosilicate glass) or other known materials of appropriate thickness, and pattern using a photolithographically patterned photoresist mask. For photolithographic structuring, a photoresist layer is first applied to the wafer surface or surface of the hard mask layer and cured. Subsequently, the contact holes on the wafer edge For example, exposed using a mask and a development step and possibly an additional curing step is performed. Subsequently, when using a hard mask layer, first the contact holes are etched into the hard mask layer by known methods.

Then, using conventional methods, contact holes 5 in the top 17 etched of the wafer, as in 2 is shown. It should be noted that in the drawings, only the part of the saw frame is shown, in which the contact area is made, ie the part that will not be removed later when separating the wafer into chips. Usually it extends depending on the width of the saw frame still up to about 900 microns in a direction perpendicular to the later chip side surface.

The depth of the contact holes is about 100 μm or less for horizontally connecting contacts. However, if the lateral contacts are also used for vertically connecting contacts sets, so must the finished contact areas 13 to the bottom 18 of the wafer. This can be done either by etching to the wafer bottom 18 or else be achieved by deep etching and subsequent thinning of the wafer from the bottom. According to the present invention, it is particularly preferred to thin the wafer from the bottom only when the contact areas 13 are completed and in particular with the electrically conductive contact material 9 have been filled.

After etching the contact holes 5 be like in 3 shown, a thin insulation layer 6 , For example, of SiO ₂ or Si 3 N ₄ , and optionally adhesion (intermediate) layers over the entire surface according to known methods deposited in the contact hole compliant.

Then, as in 4 shown, an electrically conductive contact material 9 such as A1 or W deposited until the contact hole is filled. Subsequently, the applied photoresist and optionally hard mask layers are removed again.

Since at the in 3 step shown also the edge of the trace 3 with the insulation layer 6 , That is, the contact surface was covered for the electrical contact between the conductor track and the lateral contact area to be produced, this area is etched free in a next step. For this purpose, first a photoresist layer is again applied to the wafer surface, which is then cured. Thereafter, the contact point between conductor track 3 and contact hole 5 covered with a suitable mask, the photoresist layer is exposed and developed, if necessary, an additional curing step is performed. Subsequently, as in 5 shown etched the vertical portions of the insulating layer and optionally applied adhesion-promoting (intermediate) layers according to known methods. In addition, some contact material is abgetra conditions to ensure that the insulation layer is completely removed in the contact area.

In a next step, as in 6 is shown using the mask used in the previous step, a contact filling 7 from an electrically conductive material such as W, Al or another metal or metal compound, optionally also with additional intermediate layers by known methods such as sputtering, CVD method or particularly deep contact holes also deposited a so-called Al force-fill method. The height and thickness of the contact filling 7 correspond to a maximum of the height and thickness of the metal sheet. This is achieved either by timed deposition or by abrading or re-etching after completion of the deposition step.

In the next step, as in 7 is shown, depending on further processing of the wafer, an insulating layer 8th be deposited on the contact area to electrically separate the bulk silicon material again from the contact and to produce a smooth surface within the contact area. However, this step may also be omitted depending on the subsequent processing steps.

Subsequently, will the wafer surface with the usual cover layers used (e.g., oxide and imide layers), around her shield oxygen and hydrogen contained in the ambient air.

Should the contact area to be produced 13 become a vertically connecting, it is now preferably, depending on the manufacturing process, the step of thinning the wafer 1 from the bottom 18 , This can be done, for example, by a chemical mechanical polishing (CMP) method using an etch stop layer, by abrading the wafer back, physical or wet chemical etching with timing. The wafer 1 is thinned so that with the contact material 9 filled contact areas 13 extend from the top to the bottom, as in 8th is illustrated. Alternatively, it is also possible for the production of vertically connecting contacts, the contact holes 5 Etch to the wafer bottom and then with the contact material 9 to fill. In this case it is expedient, before the Singulation of the semiconductor wafer 1 to polish the back of the wafer to remove remnants of the contact material 9 to remove on the back.

In one next Step, the wafer is cut into individual chips. Usually this is done with a suitable Sägemechanismus, for example a band saw. By correct sawing The contact area will provide a clean, smooth cut surface reaches a defined extent of the contact area. At the Cutting the chips becomes the sawing frame almost complete away. There remains only the area of the saw frame, in which the produced lateral contact area is located. This one can optionally removed in a subsequent re-etching step become, whereby exposed, that is, outstanding contacts be generated.

11 shows the process step of singulating a semiconductor wafer 1 in several semiconductor chips 12 each of which is an independent semiconductor circuit 2 comprising, via at least one conductor track with a contact area 13 connected to a chip side surface. The contact areas according to the invention 13 serve as side contacts of the semiconductor chips.

9 now shows the finished semiconductor chip 12 in which the lateral contact area 13 in the side area 11 of the semiconductor chip 12 is made. The remaining portion of the framework 4 was removed here by re-etching, so that the contact area 13 from the side surface 11 protrudes.

When the lateral contact area 13 is made as a vertical contact area, it preferably extends from the top 14 to the bottom 15 ,

The contact area 13 has a defined extent in all three spatial directions, it has a sufficiently large, contactable surface in all three spatial directions and it is electrically insulated from the surrounding bulk silicon, the non-contacted on-chip interconnects and other lateral contacts. In particular, the contact area 13 from the chip top 14 and the chip bottom 15 contactable. In addition, it is produced with the methods of planar technology such as lithography, etching, deposition and more, so that it meets all the requirements for a chip contact. The contact quality (eg the layer-conducting resistance) is determined by the deposition methods and is of the same quality as with conventional contacts on the chip top side. Is the contact area 13 not formed as a vertically connecting contact, it is located in 9 the bottom 15 of the semiconductor chip 12 below the lower edge of the contact area 13 ,

Become made several lateral contact areas and different Tracks at different heights electrically connected within the wafer, so the respective etching and Abscheideschritte adapted to the different heights.

According to a first modification of the first embodiment, in the in 3 shown step the insulation layer 6 applied so that the contact surface for the electrical contact between the conductor track 3 and the lateral contact area to be produced is not covered with the insulating layer. This is achieved either by a selective deposition method or by a first step to blanket deposition, as well as in 3 shown, and a subsequent step for re-etching, so that the contact surface for the electrical contact between the conductor track 3 and the lateral contact region to be produced even before the electrically conductive contact material has been deposited 9 is exposed.

According to a second modification of the first embodiment, the contact region is produced simultaneously with the associated conductor track after the at least one semiconductor circuit 2 has been produced. In this case, first, as in 10 illustrates, conductor and contact hole lithographically structured, then the insulating layer 6 deposited and then the electrically conductive contact material 9 both for the track 3 as well as the contact hole 13 deposited. In this case also eliminates the etching of the contact surface for the electrical contact between the conductor track 3 and contact area 13 , The in 7 illustrated step for depositing the insulating layer 8th can be performed in this case over the entire surface for both the trace and the contact area. But it can also be dispensed with depending on further processing of the wafer. Optionally, in the region of a lateral contact to be made before deposition, something deeper into the substrate material (such as bulk silicon) may be etched to achieve a greater contact height.

According to a second embodiment of the present invention, the lateral contact areas are worked into the chip, as in FIG 20 shown. Since when separating the wafer into chips, the entire sawing frame is removed, the lateral contact areas are exposed during the cutting, but not destroyed.

Also in this embodiment, a semiconductor wafer is formed 1 with completed, independent semiconductor circuits, which will be included in the various semiconductor chips after the later division of the wafer. As in 13 is shown buried in the substrate lei track 3 for the corresponding signals led to the later chip edge. Also in this embodiment, the production of the contact region takes place from the wafer surface.

First, an etch mask for etching the contact holes on the chip edge is produced by known methods. Depending on the depth of the contact hole to be etched, a photoresist layer, possibly a special photoresist for deep etch depths, is first applied and patterned photolithographically by known methods. At deeper etch depths, it may be necessary to apply a hard mask material, such as Si ₃ N ₄ , SiO ₂ , SiON, BSG (borosilicate glass) or other known materials of appropriate thickness, and pattern using a photolithographically patterned photoresist mask. For photolithographic structuring, a photoresist layer is first applied to the wafer surface or surface of the hard mask layer and cured. Subsequently, the contact holes are exposed at the wafer edge, for example using a mask, and a development step and possibly an additional curing step is performed. Subsequently, when using a hard mask layer, first the contact holes are etched into the hard mask layer by known methods.

In 12 denotes reference numeral 10 the area of the wafer surface in which a contact hole is made.

Then, using conventional methods, contact holes 5 etched, as in 13 is shown.

The depth of the contact holes is about 100 μm or less for horizontally connecting contacts. However, if the lateral contacts are also to be used for vertically connecting contacts, then the finished contact areas must be 13 to the bottom 15 of the wafer. This can be done either by etching to the wafer bottom 15 or else be achieved by deep etching and subsequent thinning of the wafer from the bottom. According to the present invention, it is particularly preferred to thin the wafer from the bottom only when the contact areas 13 are completed and in particular with the electrically conductive contact material 9 have been filled.

Subsequently, as in 14 shown, a thin insulation layer 6 , For example, of SiO ₂ or Si ₃ N ₄ and optionally adhesion-promoting (intermediate) layers over the entire surface conformally deposited by known methods.

Then, as in 15 shown, an electrically conductive contact material 9 such as Al or W deposited until the contact hole is filled up. Subsequently, the applied photoresist and optionally hard mask layers are removed again.

Since at the in 14 step shown also the edge of the trace 3 , ie the contact surface for the electrical contact between the conductor track and the lateral contact region to be produced, with the insulation layer 6 In a next step, this area is etched free. For this purpose, first a photoresist layer is again applied to the wafer surface, which is then cured. Thereafter, the contact point between conductor track 3 and contact hole 5 covered with a suitable mask, the photoresist layer is exposed and developed, and optionally an additional curing step is performed. Subsequently, as in 16 shown etched the vertical regions of the insulating layer and the optionally applied adhesion-promoting (intermediate) layers. In addition, some contact material is removed to ensure that the insulation layer is completely removed in the contact area.

In a next step, as in 17 shown using the mask used in the previous step, a contact filling 7 from an electrically conductive material such as W, Al or another metal or metal compound, optionally also with additional intermediate layers by known methods such as sputtering, CVD method or particularly deep contact holes also deposited a so-called Al force-fill method. The height and thickness of the contact filling 7 correspond to a maximum of the height and thickness of the metal sheet. This is achieved either by a timed deposition or by grinding or re-etching after completion of the deposition step.

In the next step, as in 18 shown, depending on further processing of the wafer, an insulating layer 8th be deposited on the contact area to electrically separate the bulk silicon material again from the contact and to produce a smooth surface within the contact area. However, this step may also be omitted depending on the subsequent processing steps.

Subsequently, will the wafer surface with the usual cover layers used (e.g., oxide and imide layers), around her shield oxygen and hydrogen contained in the ambient air.

Should the contact area to be produced 13 become a vertically connecting, it is now preferably, depending on the manufacturing process, the step of thinning the wafer 1 from the back. This can be done, for example, by a chemical-mechanical polishing (CMP) process using an etch-stop layer, by grinding the back of the wafer, or physical or wet-chemical etching with timing. The wafer 1 is thinned so that with the contact material 9 filled contact areas 13 extend from the top to the bottom, as in 19 is illustrated. Alternatively, it is also possible for the production of vertically connecting contacts, the contact holes 5 Etch to the wafer bottom and then with the contact material 9 to fill. In this case, it is expedient before separation of the semiconductor wafer 1 to polish the back of the wafer to remove remnants of the contact material 9 to remove on the back.

In a next step, the wafer is divided into the individual chips as described above with reference to FIG 11 has been explained.

20 shows the finished semiconductor chip 12 in which the lateral contact area 13 in the side area 11 of the semiconductor chip 12 is made and also part of the side surface 11 forms, so do not stick out of it. If a plurality of semiconductor chips of this type arranged side by side, it may be necessary to electrically isolate them by an insulating layer on the side surfaces of each other to avoid unwanted short circuits that occur, for example, when different chips with different substrate potential directly adjacent to each other.

The in 20 shown contact area 13 has a defined extent in all three spatial directions, it has a sufficiently large, contactable surface in all three spatial directions, and it is electrically insulated from the surrounding bulk silicon, the non-contacted on-chip interconnects and other lateral contacts. In particular, the contact area 13 from the chip top 14 and the chip bottom 15 contactable.

The contact quality (eg the layer-conducting resistance) is determined by the deposition methods and is of the same quality as with conventional contacts on the chip top side. Is the contact area 13 not formed as a vertically connecting contact, so extends into 20 the contact area 13 not to the chip bottom 15 , and there is bulk silicon below the bottom edge of the contact area 13 ,

Become made several lateral contact areas and different Tracks at different heights electrically connected within the wafer, so the respective etching and Abscheideschritte adapted to the different heights.

According to a first modification of the second embodiment, in the in 14 shown step the insulation layer 6 applied so that the contact surface for the electrical contact between the conductor track 3 and the lateral contact area to be produced is not covered with the insulating layer. This is achieved either by a suitable deposition method or by a first step to blanket deposition, as well as in 13 shown, and a subsequent step for re-etching, so that the contact surface for the electrical contact between the conductor track 3 and the lateral contact region to be produced even before the electrically conductive contact material has been deposited 9 is exposed.

According to a second modification of the second embodiment, the contact hole is made simultaneously with the associated trace analogous to the second modification of the first embodiment, as shown in FIG 10 has been explained. In this case, first conductor track and contact area are lithographically structured, then the insulation layer 6 deposited and then deposited the electrically conductive contact material for both the trace and the contact hole. In this case also eliminates the etching free of the contact surface for the electrical contact between the conductor track and contact area. The in 18 shown, optional step for depositing the Isola tion layer 8th is performed in this case over the entire area for both the track and the contact area.

The lateral contact surface the contact areas can otherwise through a prolonged and thereby deeper contact areas are increased.

21 shows with regard to the deposition of the insulating layer 6 a first alternative embodiment, in which this insulating layer 6 exclusively on the semiconductor material 1 , but not on the free etched side surface of the track 3 is deposited. Alternatively, by a non-selective deposition and the conductor track 3 covered in the contact hole, as in 22 shown.

Regarding the initial depth of the contact area 13 shows 23 a first alternative embodiment in which this area initially not to the bottom 17 of the wafer 1 extends. As indicated by the vertical arrows, the wafer can 1 thinned from the bottom be until, as in 24 shown, the contact area 13 to the bottom 18 extends. Alternatively, the contact area 13 or the contact hole provided for this purpose 5 also from the beginning to the bottom 18 of the wafer 1 be etched through.

The contact area 13 or the contact hole provided for this purpose 5 can, as in 21 represented, partly inside and partly outside a sawing frame 4 be arranged. In this case, when separating by sawing away the area 4 a side surface of the contact area 13 exposed, as in 23 or 24 shown. Alternatively, as in 25 shown, the contact area 13 also completely within a sawing frame 4 produced, but in an area that is not sawn. In a subsequent etching back from a side surface, as indicated by the arrows in FIG 25 indicated, may be a side surface of the contact area 13 be exposed. Preferably, the etching back is carried out until the contact area 13 over the etched back wall of the wafer 1 stands out as in 26 shown. The embodiments of 21 to 26 can with each of the embodiments of the 1 to 20 and the claims are combined.

1

Semiconductor wafer

2

Semiconductor circuit

3

conductor path

4

saw frame

5

contact hole

6

insulation layer

7

Contact filling

8th

insulation layer

9

Contact material

11

Wafer side face

12

Semiconductor chip

13

contact area

14

Chip top

16

Contact area

17

top

18

bottom

19

upper subarea

20

lower subarea

Claims (16)

Method for producing at least one semiconductor chip ( 12 ) comprising the steps: - providing a semiconductor wafer ( 1 ) with one or more independent semiconductor circuits ( 2 ), with at least one semiconductor circuit ( 2 ) associated conductor track ( 3 ) and one with the track ( 3 ) electrically connected contact area ( 13 ) in a peripheral area ( 4 ) of the semiconductor circuit ( 2 ) and - dicing the wafer ( 1 ) in semiconductor chips ( 12 ), each of the independent semiconductor circuits ( 2 ), whereby a side surface ( 16 ) of the contact area ( 13 ) is exposed. Method according to claim 1, characterized in that the contact area ( 13 ) and the track ( 3 ) at the same time. Method according to claim 1, characterized in that the step of manufacturing a contact area ( 13 ) comprises - etching a contact hole ( 5 ) connected to the track ( 3 ), in a top ( 17 ) of the semiconductor wafer ( 1 ), - applying an insulating layer ( 6 ) located within the contact hole ( 5 ) Covers side walls of the contact hole, and - introducing an electrically conductive contact material ( 9 ) into the contact hole ( 5 ). Method according to claim 3, characterized in that the insulating layer ( 8th ) is applied so that it the side walls of the contact hole ( 5 ), but not the trace ( 3 ) in the contact hole ( 5 ) covered. Method according to claim 3, characterized in that - the insulating layer ( 6 ) is applied so that they are within the contact hole ( 5 ) Material of the semiconductor wafer ( 1 ) and the track ( 3 ), that the insulating layer ( 6 ) in a region of the side wall of the contact hole ( 5 ), to which the conductor track ( 3 ), is etched back and that in the back-etched area a contact filling ( 7 ) on the electrical contact material ( 9 ) is applied. Method according to Claim 5, characterized in that the contact filling ( 7 ) an insulation layer ( 8th ) is applied. Method according to one of Claims 2 to 6, characterized in that the contact hole ( 5 ) to a bottom ( 18 ) of the semiconductor wafer is etched. Method according to one of Claims 2 to 6, characterized in that the semiconductor wafer ( 1 ) subsequently from its underside ( 18 ) is thinned until the contact area ( 13 ) from a top side ( 17 ) of the semiconductor wafer ( 1 ) to a bottom ( 18 ) of the semiconductor wafer ( 1 ). Method according to one of Claims 1 to 8, characterized in that the contact region ( 13 ) in a sawing frame ( 4 ) outside the semiconductor chip ( 12 ) and the semiconductor wafer ( 1 ) in semiconductor chips ( 12 ), that the contact area ( 13 ) is preserved during cutting. Method according to claim 9, characterized by an etch-back in a part of the saw frame ( 4 ) until the contact area ( 13 ) from a chip side surface ( 11 protruding). Method according to one of claims 1 to 10, characterized in that the contact area ( 13 ) in an edge region of a semiconductor chip ( 12 ) partially inside and partly outside the saw frame ( 4 ) lies. Semiconductor chip with at least one conductor track ( 3 ), which extend to a peripheral area ( 4 ) of the semiconductor chip ( 12 ) and at least one contact area ( 13 ) in a side surface ( 11 ) of the semiconductor chip ( 12 ) in contact with the conductor track ( 3 ). Semiconductor chip according to Claim 12, characterized in that the contact region ( 13 ) a partial area ( 19 ) in a top ( 17 ) of the semiconductor chip ( 12 ). Semiconductor chip according to Claim 12 or 13, characterized in that the contact region ( 13 ) a partial area ( 20 ) in a bottom ( 18 ) of the semiconductor chip ( 12 ). Semiconductor chip according to one of Claims 12 to 14, characterized in that the contact region ( 13 ) from the side surface ( 11 protruding). Semiconductor chip according to one of Claims 12 to 15, characterized in that the conductor track ( 3 ) with a semiconductor circuit ( 2 ) of the semiconductor chip ( 12 ), preferably connected to a dynamic random access memory.