DE102009036033A1 - Interlayer connection for semiconductor wafers, has base wafer with connection pad and cover wafer arranged on base wafer, where cover wafer has continuous opening over connection pad - Google Patents
Interlayer connection for semiconductor wafers, has base wafer with connection pad and cover wafer arranged on base wafer, where cover wafer has continuous opening over connection pad Download PDFInfo
- Publication number
- DE102009036033A1 DE102009036033A1 DE200910036033 DE102009036033A DE102009036033A1 DE 102009036033 A1 DE102009036033 A1 DE 102009036033A1 DE 200910036033 DE200910036033 DE 200910036033 DE 102009036033 A DE102009036033 A DE 102009036033A DE 102009036033 A1 DE102009036033 A1 DE 102009036033A1
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- Prior art keywords
- wafer
- cover
- connection pad
- base
- cover wafer
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/06102—Disposition the bonding areas being at different heights
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H01L2924/0001—Technical content checked by a classifier
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H01L2924/01082—Lead [Pb]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
Abstract
Description
Die vorliegende Erfindung betrifft eine Durchkontaktierung für Halbleiterwafer, die durch Wafer-Bonding miteinander verbunden werden, und ein zugehöriges Verfahren zur Herstellung einer solchen Durchkontaktierung.The The present invention relates to a via for Semiconductor wafers bonded together by wafer bonding and an associated method for producing such a via.
In
der
Aufgabe der vorliegenden Erfindung ist es, eine neuartige Durchkontaktierung für Halbleiterwafer anzugeben. Außerdem soll ein zugehöriges Herstellungsverfahren angegeben werden.task It is the object of the present invention to provide a novel via for semiconductor wafers. In addition, a should associated manufacturing process can be specified.
Diese
Aufgabe wird mit der Durchkontaktierung für Halbleiterwafer
mit den Merkmalen des Anspruches 1 beziehungsweise mit dem Verfahren
mit den Merkmalen des Anspruches 6 gelöst. Ausgestaltungen
ergeben sich aus den jeweiligen abhängigen Ansprüchen.These
Task is with the via for semiconductor wafers
with the features of
Bei der Durchkontaktierung wird ein Anschluss-Pad eines Basis-Wafers, auf dem ein Abdeck-Wafer angeordnet ist, mit einer Lotkugel (bump) versehen. Hierzu wird in dem Abdeck-Wafer, vor oder nach dem Verbinden mit dem Basis-Wafer, eine durchgehende Öffnung über dem Anschluss-Pad hergestellt, in der die Lotkugel angeordnet und elektrisch leitend mit dem Anschluss-Pad verbunden wird.at the via becomes a terminal pad of a base wafer, on which a cover wafer is arranged, provided with a solder ball (bump). This is done in the cover wafer, before or after the connection with the base wafer, a through opening over made the connection pad, in which the solder ball is arranged and electrically connected to the connection pad.
Der Anschluss-Pad kann als elektrischer Anschluss eines elektronischen Bauelementes oder einer integrierten Schaltung des Basis-Wafers vorgesehen sein. Weitere Ausführungsbeispiele können Seitenwände der durchgehenden Öffnung besitzen, die mit einer Passivierung aus dielektrischem oder elektrisch isolierendem Material versehen sind. Vorzugsweise überragt die Lotkugel den Abdeck-Wafer, so dass auf der von dem Basis-Wafer abgewandten Seite des Abdeck-Wafers ein weiterer Wafer oder zum Beispiel ein PCB (printed circuit board) angeordnet und ein darauf vorhandener Anschlusskontakt elektrisch leitend mit der Lotkugel verbunden werden kann.Of the Connection pad can be used as an electrical connection of an electronic Component or an integrated circuit of the base wafer be provided. Other embodiments may include side walls have the through opening, with a passivation made of dielectric or electrically insulating material are. Preferably, the solder ball protrudes beyond the cover wafer, so that on the side facing away from the base wafer side of the cover wafer another wafer or, for example, a PCB (printed circuit board) arranged and an existing terminal contact electrically can be conductively connected to the solder ball.
Der Abdeck-Wafer kann zum Beispiel ein Siliziumsubstrat sein und braucht insbesondere nicht mit elektrisch leitenden Verbindungen versehen zu sein. Der Abdeck-Wafer kann eine Struktur aufweisen, die für ein oder mehrere elektronische Bauelemente oder für eine integrierte Schaltung vorgesehen ist. Der Abdeck-Wafer kann oberseitig strukturiert sein, so dass insbesondere die dem Basis-Wafer zugewandte Seite mit Aussparungen oder dergleichen versehen sein kann. Auch die dem Abdeck-Wafer zugewandte und von dem Abdeck-Wafer abgedeckte Oberseite des Basis-Wafers kann mit einer Oberflächenstruktur versehen sein. Hiermit ist es insbesondere möglich, in den verbundenen Wafern einen Hohlraum auszubilden, in dem zum Beispiel ein bewegliches Teil eines mikroelektromechanischen Bauelementes angeordnet sein kann.Of the Cover wafer may be, for example, a silicon substrate and needs in particular not provided with electrically conductive connections to be. The cover wafer may have a structure suitable for one or more electronic components or for one integrated circuit is provided. The cover wafer can be on the top side be structured so that in particular those facing the base wafer Side can be provided with recesses or the like. Also the top wafer facing the cap wafer and covered by the cap wafer of the base wafer may be provided with a surface texture be. This makes it possible in particular in the connected Wafern to form a cavity in which, for example, a movable Be part of a microelectromechanical device arranged can.
Eine weitere Ausgestaltung besteht darin, auch ein Anschluss-Pad des Abdeck-Wafers freizulegen und auf der von dem Basis-Wafer abgewandten Seite des Anschluss-Pads des Abdeck-Wafers ebenfalls eine Lotkugel als elektrischen Anschluss anzuordnen und elektrisch leitend mit diesem Anschluss-Pad zu verbinden. Auf diese Weise ist es möglich, elektronische Bauelemente und integrierte Schaltungen beider Wafer auf derselben Seite des Abdeck-Wafers elektrisch anzuschließen.A Another embodiment is also a connection pad of the Cover wafers exposed and on the side facing away from the base wafer side the connection pad of the cover wafer also a solder ball as to arrange electrical connection and electrically conductive with this Connection pad to connect. In this way it is possible electronic components and integrated circuits of both wafers electrically connect on the same side of the cover wafer.
Die in dem Abdeck-Wafer vorgesehene durchgehende Öffnung oberhalb des Anschluss-Pads des Basis-Wafers kann durch ein an sich bekanntes Ätzverfahren unter Verwendung einer ebenfalls an sich bekannten Maskentechnik hergestellt werden. Es können auf diese Weise auch mehrere Öffnungen für mehrere Lotkugeln in dem Abdeck-Wafer vorgesehen werden. Da die Positionen dieser Öffnungen durch die Öffnungen einer geeignet strukturierten Maske festgelegt werden, ist es mit diesem Verfahren möglich, eine im Prinzip beliebige Anordnung von Anschluss-Pads des Basis-Wafers mit Lotkugeln als externen elektrischen Anschlüssen zu versehen.The in the cover wafer provided through opening above The connection pad of the base wafer can by a known per se etching using a well-known mask technique getting produced. It can in this way also several openings for a plurality of solder balls in the cover wafer. Because the positions of these openings through the openings a suitably structured mask, it is with this method possible, in principle, any arrangement from connection pads of the base wafer with solder balls as external electrical To provide connections.
Es
folgt eine genauere Beschreibung von Beispielen der Durchkontaktierung
und des Herstellungsverfahrens anhand der beigefügten
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Verbindung zwischen dem Basis-Wafer
Auf
dem Anschluss-Pad
Eine
Lotkugel
Auf
der von dem Basis-Wafer
Im
Folgenden werden Ausführungsbeispiele für die
Herstellung einer solchen Durchkontaktierung für Halbleiterwafer
anhand der
Die
Die
Die
mit der Aussparung
Die
Die
Die
Die
In
der ersten Variante gemäß
Bei
der Variante gemäß der
Die
In
einem weiteren Verfahrensschritt, zum Beispiel einem Trockenätzschritt
ohne Verwendung einer Maske, wird die weitere Passivierungsschicht
In
beiden Herstellungsvarianten kann dann, vorzugsweise in einem stromlosen
Verfahren, eine Metallschicht als Unterlotmetallisierung
Die
Auf
der Lotkugel
Die
Lotkugel
Die
Die
Dieses
Verfahren ist besonders geeignet in Verbindung mit der zweiten Herstellungsvariante
für die Durchkontaktierung. Die Aussparung für
die spätere durchgehende Öffnung
Die
Es
ist ein Vorteil der Durchkontaktierung und des zugehörigen
Herstellungsverfahrens, dass hiermit eine grundsätzlich
beliebige Anordnung solcher Durchkontaktierungen realisiert werden
kann. Durchgehende Öffnungen können mittels einer
geeigneten Maske an beliebigen Stellen des Abdeck-Wafers
BezugszeichenlisteLIST OF REFERENCE NUMBERS
- 11
- Basis-WaferBase wafer
- 22
- Abdeck-WaferCap wafer
- 33
- Anschluss-PadConnection pad
- 44
- UnterlotmetallisierungUnterlotmetallisierung
- 55
- Lotkugelsolder ball
- 66
- Metallisierungsebenemetallization
- 77
- Zwischenmetalldielektrikumintermetal
- 88th
- Opferschichtsacrificial layer
- 99
- Aussparungrecess
- 1010
- Schichtstruktur des Basis-Waferslayer structure of the base wafer
- 1111
- Aussparungrecess
- 1212
- Öffnungopening
- 1313
- Passivierungsschichtpassivation
- 1414
- Lackmaskeresist mask
- 1515
- weitere PassivierungsschichtFurther passivation
- 1616
- Lackmaskeresist mask
- 1717
- Verbindungsschichtlink layer
- 1818
- PCBPCB
- 1919
- Anschluss-PadConnection pad
- 2020
- Schichtstruktur des Abdeck-Waferslayer structure the cover wafer
- 2121
- Anschluss-Pad des Abdeck-WafersConnection pad the cover wafer
- 2222
- weitere LotkugelFurther solder ball
- 2323
- Biegebalkenbending beam
- 2424
- Kontur einer Öffnungcontour an opening
- 2525
- durchgehende Öffnungthrough opening
ZITATE ENTHALTEN IN DER BESCHREIBUNGQUOTES INCLUDE IN THE DESCRIPTION
Diese Liste der vom Anmelder aufgeführten Dokumente wurde automatisiert erzeugt und ist ausschließlich zur besseren Information des Lesers aufgenommen. Die Liste ist nicht Bestandteil der deutschen Patent- bzw. Gebrauchsmusteranmeldung. Das DPMA übernimmt keinerlei Haftung für etwaige Fehler oder Auslassungen.This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.
Zitierte PatentliteraturCited patent literature
- - US 2005/009246 A1 [0002] US 2005/009246 A1 [0002]
- - US 2004/099921 A1 [0002] - US 2004/099921 A1 [0002]
- - WO 2004/008522 [0002] WO 2004/008522 [0002]
- - EP 1962325 A1 [0002] EP 1962325 A1 [0002]
Claims (15)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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DE200910036033 DE102009036033B4 (en) | 2009-08-04 | 2009-08-04 | Through-hole for semiconductor wafers and manufacturing process |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE200910036033 DE102009036033B4 (en) | 2009-08-04 | 2009-08-04 | Through-hole for semiconductor wafers and manufacturing process |
Publications (3)
Publication Number | Publication Date |
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DE102009036033A1 true DE102009036033A1 (en) | 2011-02-17 |
DE102009036033A8 DE102009036033A8 (en) | 2011-06-01 |
DE102009036033B4 DE102009036033B4 (en) | 2012-11-15 |
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ID=43448133
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DE200910036033 Expired - Fee Related DE102009036033B4 (en) | 2009-08-04 | 2009-08-04 | Through-hole for semiconductor wafers and manufacturing process |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102011116409B3 (en) * | 2011-10-19 | 2013-03-07 | Austriamicrosystems Ag | Method for producing thin semiconductor components |
US11764543B2 (en) | 2020-04-23 | 2023-09-19 | Mellanox Technologies, Ltd. | Integration of modulator and laser in a single chip |
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US6429511B2 (en) * | 1999-07-23 | 2002-08-06 | Agilent Technologies, Inc. | Microcap wafer-level package |
WO2004008522A2 (en) | 2002-07-16 | 2004-01-22 | Austriamicrosystems Ag | Method for producing a component having submerged connecting areas |
US20040099921A1 (en) | 2002-01-25 | 2004-05-27 | Sony Corporation | MEMS package |
US6777263B1 (en) * | 2003-08-21 | 2004-08-17 | Agilent Technologies, Inc. | Film deposition to enhance sealing yield of microcap wafer-level package with vias |
US20050009246A1 (en) | 2002-09-25 | 2005-01-13 | Ziptronix, Inc. | Wafer bonding hermetic encapsulation |
US20050212132A1 (en) * | 2004-03-25 | 2005-09-29 | Min-Chih Hsuan | Chip package and process thereof |
WO2006061792A2 (en) * | 2004-12-10 | 2006-06-15 | Koninklijke Philips Electronics N.V. | Hermetically sealed integrated circuit package |
EP1962325A1 (en) | 2005-12-16 | 2008-08-27 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing bonded substrate |
US20080277771A1 (en) * | 2005-01-28 | 2008-11-13 | Matsushita Electric Industrial Co., Ltd. | Electronic Device Package Manufacturing Method and Electronic Device Package |
-
2009
- 2009-08-04 DE DE200910036033 patent/DE102009036033B4/en not_active Expired - Fee Related
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6429511B2 (en) * | 1999-07-23 | 2002-08-06 | Agilent Technologies, Inc. | Microcap wafer-level package |
US20040099921A1 (en) | 2002-01-25 | 2004-05-27 | Sony Corporation | MEMS package |
WO2004008522A2 (en) | 2002-07-16 | 2004-01-22 | Austriamicrosystems Ag | Method for producing a component having submerged connecting areas |
US20050009246A1 (en) | 2002-09-25 | 2005-01-13 | Ziptronix, Inc. | Wafer bonding hermetic encapsulation |
US6777263B1 (en) * | 2003-08-21 | 2004-08-17 | Agilent Technologies, Inc. | Film deposition to enhance sealing yield of microcap wafer-level package with vias |
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Cited By (4)
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DE102011116409B3 (en) * | 2011-10-19 | 2013-03-07 | Austriamicrosystems Ag | Method for producing thin semiconductor components |
WO2013056936A1 (en) | 2011-10-19 | 2013-04-25 | Ams Ag | Method for producing thin semiconductor components |
US9105645B2 (en) | 2011-10-19 | 2015-08-11 | Ams Ag | Method for producing thin semiconductor components |
US11764543B2 (en) | 2020-04-23 | 2023-09-19 | Mellanox Technologies, Ltd. | Integration of modulator and laser in a single chip |
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DE102009036033B4 (en) | 2012-11-15 |
DE102009036033A8 (en) | 2011-06-01 |
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