DE10230244B4 - Blower device for a cooking appliance - Google Patents

Abstract

Level conversion device (101a, 101b) for converting a signal (in) having a first voltage level (vint) into a signal (DatoV) which has a second voltage level (vddq) different from the first voltage level (vint), the level conversion Device (101a, 101b) has an amplifier device (102), and in addition to generating a signal (DatoV) having the second voltage level (vddq), in addition to a first output signal (out) of the amplifier device (102), a second, different amplifier device Output signal (bout) is used, characterized in that a first transmission gate (113b) is driven with the first amplifier device output signal (out), or a signal derived therefrom, and with the second amplifier device output signal (bout), or a a second transmission gate (113a) derived therefrom.

Description

The invention relates to a level conversion device according to the generic term of claim 1.

With semiconductor components, in particular with Memory components such as DRAMs (DRAM = Dynamic Random Access Memory or dynamic read / write memory) can be internal voltage level used in the component from an outside the external voltage level used in the building element.

In particular, the voltage level internally used can be smaller than the external voltage level used - for example, the voltage level internally used 1 , 8V, and the externally used voltage level 2 , 5V.

This may be due to e.g. in this have that external power supply fluctuations relatively large subject, and therefore - with it the component can be operated without errors - by means of a voltage regulator into a (subject to only relatively minor fluctuations, to one certain constant value) internal voltage must become.

Through the use of voltage regulators occurs inevitably a loss of voltage that leads to the internal in the component voltage level used is less than the external voltage level.

A compared to the voltage level used externally reduced internal voltage level has the advantage of doing this the power losses in the semiconductor component are reduced can.

A lower voltage level is generated internally in the component used as external, must the signals generated internally in the component - prior to their output to the outside - are initially by means of So-called level converters are converted into corresponding, higher-level signals become.

Such level converters can e.g. an amplifier circuit have that of cross-coupled p- or n-channel field effect transistors consists.

With the help of the amplifier circuit can Internal, low-level signals generated in the component - with certain delay times afflicted - in corresponding higher level Signals are implemented.

However, this can - with a positive Edge of an internal signal - occurring delay time from - at a negative edge of the internal signal - occurring delay time differ. this leads to to that of the amplifier circuit output, higher level Signals are distorted.

To compensate for this effect, those of the amplifier circuit output signals of one of several, e.g. two inverters connected in series having driver stage supplied become.

The inverters are designed so that compensation for the output from the amplifier circuit Distortion contained signals is achieved.

However, the driver stage leads to one relatively high - additional - signal delay; furthermore can for example due to changes caused by temperature fluctuations the properties of the level converter components the above signal distortion by a level converter of the type described above i.A. only partially compensated become.

In the JP2001024502 A describes a - having an amplifier device - level conversion device with which a signal having a first voltage level is converted into a signal having a second voltage level different from the first voltage level. In order to generate the signal having the second voltage level, in addition to a first output signal from the amplifier device, a second amplifier device output signal which is different therefrom is additionally used.

The invention has for one novel level conversion device provide.

It achieves this and other goals by the subject matter of claim 1.

Advantageous further training Invention are in the subclaims specified.

Is particularly advantageous through triggered an edge of the first amplifier device output signal, that the signal from. having the second voltage level (vddq) changes from a first to a second state, and by an opposite to the Edge of the first amplifier device output signal in time offset edge of the second amplifier device output signal that the signal having the second voltage level (vddq) from the second back changes to the first state.

This is preferably the triggering causing edge of the first amplifier output signal a positive edge, and the triggering edge of the second amplifier device output signal also a positive edge (or the triggering edges) of the first and second amplifier output signals, respectively are negative edges).

With such a level conversion means for example can be achieved that even at relatively high temperature fluctuations in the Verstär distortion contained in the circuitry can be almost completely compensated for.

The invention is explained below of an embodiment and the attached drawing explained in more detail. In the drawing shows:

1 is a schematic representation of a circuit arrangement of a level converter according to the prior art;

2a is a schematic representation of a first section of a circuit arrangement of a level converter according to an embodiment of the present invention

2 B a schematic representation of another portion of the circuit configuration of the level shifter according to the embodiment of the present invention, and

3 is a schematic representation of the time course of the input and output signals of the in 2a and 2 B level converter shown amplifier circuit, and the equalized output signal of the level converter.

In 1 is a schematic representation of a circuit arrangement of a level converter 1 shown according to the prior art. The level converter 1 is built into a DRAM memory component based, for example, on CMOS technology. It serves to convert an internal voltage level (vint) used within the memory component into an external voltage level (vddq) used outside the memory component, the internally used voltage level (vint) being lower than the externally used voltage level (vddq). For example, the internal voltage level (vint) can be 1.8 V and the external voltage level (vddq) can be 2.5 V.

As in 1 is shown, the level converter 1 an amplifier circuit 2 on, and a driver stage 8th with a first and a second inverter 3a . 3b (and alternatively with other inverters not shown here).

The amplifier circuit 2 comprises four cross-coupled transistors, namely a first and a second p-channel field effect transistor 4a . 4b (here: two p-channel MOSFETs 4a . 4b ), and a first and a second n-channel field effect transistor 5a . 5b (here: two n-channel MOSFETs 5a . 5b ).

The source of the first n-channel field effect transistor 5a is connected to ground (gnd). The source of the second n-channel field effect transistor is also corresponding 5b connected to the mass (gnd).

Furthermore, the gate of the first n-channel field effect transistor 5a with a first entrance 6a the amplifier circuit 2 connected, and the gate of the second n-channel field effect transistor 5b with a second amplifier circuit input 6b ,

At a first exit 7a the amplifier circuit 2 the drain of the first n-channel field effect transistor 5a is connected, and the gate of the second p-channel field effect transistor 4b , and the drain of the first p-channel field effect transistor 4a , Correspondingly, there is a second amplifier circuit output 7b connected to the drain of the second n-channel field-effect transistor 5b, as well as to the gate of the first p-channel field-effect transistor 4a, and the drain of the second p-channel field-effect transistor 4b.

The source of the first and second p-channel field effect transistors 4a . 4b is connected to the supply voltage. As already explained above, this has a relatively high voltage level (vddq) compared to the voltage used internally.

At the first entrance 6a the amplifier circuit 2 there is a first internal signal (in) of the DRAM memory component, and at the second input 6b the amplifier circuit 2 a second component-internal signal (bin).

The first and second internal signal (in or bin) are complementary to each other.

The "logically high" states of the first or second internal signal (in or bin) last essentially as long as their "logically low" states Internal signals (in or bin) show - as already explained above - in comparison to the externally used voltage level (vddq) the relatively low, internally used voltage level (on).

With the help of the amplifier circuit 2 it will be at the first entrance 6a the amplifier circuit 2 Internal signal present (in) - corresponding to this signal (in) - at the second output 7b the amplifier circuit 2 tapped - signal (out) implemented, which has the above - relatively high - external voltage level (vddq).

This changes at the first entrance 6a the amplifier circuit 2 The internal signal (in) present from a "logic low" to a "logic high" state (and the complementary internal signal (bin) from a "logic high" state to a "logic low" state) changes the corresponding one at the output 7b the amplifier circuit 2 tapped signal (out) due to internal signal propagation times within the amplifier circuit 2 only after a certain delay d1 'its state from "logic low" to "logic high".

Similarly, when the state of the internal signal (in) changes from "logic high" to "logic low" (and the state of the complementary internal signal (bin) changes from "logic low" to "logic high") this changes corresponding at the exit 7b tapped signal (out) only after a certain delay time d2 'its state from "logically high" to "logically low".

The delay time that occurs on a positive edge of the internal signal (in) d1 ' under differs due to different signal propagation times within the amplifier circuit 2 from the delay time d2 'occurring on a negative edge of the internal signal (in). This causes the exit 7b tapped signal (out) is distorted (in particular its "logically low" state lasts longer than its "logically high" state - and not, as desired, essentially the same length).

To compensate for this effect, the level converter 1 that at the exit 7b the amplifier circuit 2 tapped signal (out) via line 9 to an input of the first inverter 3a the driver stage 8th fed whose output 11 over a line 10 to an input of the second inverter 3b connected.

When the state of the at the output changes 7b signal that can be tapped from the amplifier circuit (out) changes from "logic low" to "logic high" (- or vice versa when the state of the signal (out) changes from "logic high" to "logic low" -) (- each time different delay times -) the signal at the output 11 of the first inverter 3a its state from logic "high" to "logic low" (- or, conversely, from "logic low" to "logic high" -), and consequently the output at a 12 of the second inverter 3b can be tapped output signal (DatoV) from a state "logic low" to a "logic high", or vice versa from a "logic high" to a "logic low" (- again after every mutually different delay times -).

The inverters 3a . 3b - In particular the delay times caused by them, different for positive and negative signal edges - are designed so that the total between a positive signal edge of the input 6a the amplifier circuit 2 applied signal (in), and a corresponding, positive signal edge of the output 12 of the second inverter 3b output signal (DatoV) occurring delay time d1 is substantially the same size, as the total occurring between a negative edge of the signal (in) and a corresponding negative signal edge of the output signal (DatoV) Delay time d2 ,

This will compensate for the im at the output 7b the amplifier circuit 2 applied signal (out) contains distortion (so that, for example, the "logic low" state of the output 12 of the second inverter 3b output signal (DatoV) lasts essentially the same length as its "logically high" state).

However, the driver stage leads 8th to a relatively high - additional - signal delay; Furthermore, due to component inaccuracies or due to changes in the properties of the components used due to temperature fluctuations, the signal distortion can generally only be compensated incompletely by a level converter of the type described above.

In 2a is a schematic representation of a first section 101 a circuit arrangement of a level converter according to an embodiment of the present invention.

The level converter is in a - e.g. on CMOS technology based - DRAM memory device installed, and can be used in particular for an OCD component of the DRAM memory component (OCD = Off Chip Driver), or e.g. for a DLL component (DLL = Delay Locked loop).

With the help of the level converter one within the DRAM memory device used internal voltage level (vint) in an outside of the Memory components used external voltage level (vddq) implemented, where the internally used voltage level (vint) is less than the externally used voltage level (vddq).

The internal voltage level (vint) can e.g. 1.8 V - or alternatively e.g. 1.5 V - and the external voltage level (vddq) for example 2.5 V - or alternatively e.g. 1.8 V.

According to 2a points out the first section 101 of the level converter an amplifier circuit 102 on, and two parallel driver stages, each with an inverter 103a . 103b , as well as a transmission gate or transfer member 113a . 113b exhibit.

The amplifier circuit 102 comprises several, in particular four, cross-coupled transistors, namely a first and a second p-channel field-effect transistor 104a . 104b (here: two p-channel MOSFETs 104a . 104 b), and a first and a second n-channel field effect transistor 105a . 105b (here: two n-channel MO5FETs 105a . 105b ).

The source of the first n-channel field effect transistor 105a is connected to ground (gnd). In a corresponding way is also the source of the second n-channel field effect transistor 105b connected to the mass (gnd).

Furthermore, the gate of the first n-channel field effect transistor 105a with a first entrance 106a the amplifier circuit 102 connected, and the gate of the second n-channel field-effect transistor 105b to a second amplifier circuit input 106b ,

At a first exit 107a the amplifier circuit 102 the drain of the first n-channel field-effect transistor 105a is connected, and the gate of the second p-channel field effect transistor 104b , and the drain of the first p-channel field effect transistor 104a , Correspondingly, there is a second amplifier circuit output 107b connected to the drain of the second n-channel field-effect transistor 105b, and the gate of the first p-channel field effect transistor 104a , and the drain of the second p-channel field effect transistor 104b ,

The source of the first and second p-Ka nal field effect transistor 104a . 104b is connected to the supply voltage. As already explained above, this has a relatively high voltage level (vddq) compared to the voltage used internally.

At the first entrance 106a the amplifier circuit 102 there is a first internal signal (in) of the DRAM memory component, and at the second input 106b the amplifier circuit 102 a second component-internal signal (bin).

The first and second internal signal (in or bin) are complementary to each other.

Furthermore, the “logical high "states of the first or second internal signal (in or bin) essentially as long as their "logical low "states.

As explained above, show the internal signals (in or bin) - compared to the externally used Voltage level (vddq) - den relatively low, internally used voltage level (vint).

With the help of the amplifier circuit 102 this will be at the first amplifier circuit input 106a Internal signal present (in) - corresponding to this signal (in) - at the second output 107b the amplifier circuit 102 tapped - converted signal (out), as well as a signal (bout) complementary to this signal (out), which at the first output 107a the amplifier circuit 102 can be tapped.

The one on the first and second amplifier circuit output 107a . 107b Tapped signals (out or bout) have the relatively high external voltage level (vddq) compared to the voltage level (vint) used for the internal signals (in or bin).

This changes at the first entrance 106a the amplifier circuit 102 Pending internal signal (in) from a "logic low" to a "logic high" state (and the complementary internal signal (bin) from a "logic high" state to a "logic low" state) changes according to 3 that at the second exit 107b the amplifier circuit 102 tapped signal (out) due to internal signal propagation times within the amplifier circuit 102 only after a certain delay d1 'Changes its state from "logic low" to "high logic" (and - after the delay time d1 ' different delay time d2 "- that at the first output 107a tapped signal (bout) from "logic high" to "logic low").

Correspondingly changes according to 3 when the state of the internal signal (in) changes from "logic high" to "logic low" (and the state of the complementary internal signal (bin) changes from "logic low" to "logic high") at the second output 107b tapped signal (out) only after a certain delay time d2 ' its state from "high logic" to "low logic" (and - after a 'different from the delay time d2 delay time d1 '' - at the first exit 107a tapped signal (bout) from "logic low" to "logic high").

The - on a positive edge of the internal signal (in) (or a negative edge of the complementary signal (bin)) - in the signal (out) occurring delay time d1 ' differs due to different internal signal propagation times within the amplifier circuit 102 (Bin or a positive edge of the complementary signal ()) on a negative edge of the internal signal (in) - - from when signal (Out) delay time occurring d2 ' ,

(Bout) in the complementary signal occurring delay time - with a positive edge of the internal signal (in) - In a corresponding manner the different d2 '' of the - at a negative edge of the internal signal (in) - When the complementary signal (bout) delay time occurring d1 '' ,

This leads to the fact that - as in 3 is shown - that at the first and second exit 7a . 7b tapped signals (out or bout) are distorted (in particular their "logically low" state lasts longer than their "logically high" state - and not, as desired, essentially the same length).

To compensate for this effect, the in 2a and 2 B level converter shown exploited the fact that - as well as from 3 it can be seen - the delay time occurring on a positive edge of the internal signal (in) for the signal (out) d1 ' due to the symmetrical structure of the amplifier circuit 102 is the same length as the delay time d1 "occurring on a complementary signal (bout) on a negative edge of the internal signal (in) (or that the delay time d2 'occurring on the signal (out) on a negative edge of the internal signal (in) is the same length as the (bout) with a positive edge of the internal signal (in) when the complementary signal occurring delay time d2 ").

In detail - is referred to again 2a - In the level converter according to the present embodiment, the second output 107b the amplifier circuit 102 tapped signal (out) via a line 109b an input of the second inverter 103b fed, and that at the first output 107a the amplifier circuit 102 tappable, complementary signal (bout) via a line 109a an input of the first inverter 103a ,

Any inverter 103a . 103b consists of an n- and a p-channel field-effect transistor, the source of the respective n-channel field-effect transistor being connected to ground (gnd) and the source of the respective p-channel field-effect transistor connected to the supply voltage (vddq) is. The one in the inverters 103a . 103b The field effect transistors used thus work in source circuit, and amplify the input voltage present at the respective inverter input inverting, with one field-effect transistor of an inverter 103a . 103b represents the load resistance for the other field effect transistor.

As in 2a and 2 B is shown, it will be at the second exit 107b the amplifier circuit 102 tapped signal (out) - except over the line 109b to the second inverter 103b - additionally via a line 111b a first control input of the second transmission gate 113b fed.

It will be the same at the first exit 107a the amplifier circuit 102 tappable, complementary signal (bout) - except over one line 109a an input of the first inverter 103a - additionally via a line 111a to a first control input of the first transmission gate 113a fed.

As further in 2a and 2 B is the output of the first inverter 103a over a line 110a to a second, complementary control input of the first transmission gate 113a connected, and the output of the second inverter 103b over a line 110b to a second, complementary control input of the second transmission gate 113b ,

Every transmission gate 113a . 113b has an n- and a p-channel field effect transistor, the first control input of the respective transmission gate 113a . 113b each to the gate of the first and the second, complementary control input of the respective transmission gate 113a . 113b is connected to the gate of the second field effect transistor.

Furthermore, the first transmission gate 113a the drain or the source of the n- or p-channel field effect transistor (ie the input or output of the first transmission gate 113a ) to ground (gnd), or via a line 114a to an exit 112 of the level converter connected.

In contrast, the second transmission gate 113b the drain or the source of the n- or p-channel field-effect transistor (ie the input or output of the second transmission gate 113b ) to the supply voltage (vddg) or via a line 114b to the level converter output 112 connected.

This has the following effect: As soon as the second output 107b the amplifier circuit 102 tapped, over the line 111b the first control input of the second transmission gate 113b supplied signal (out) changes from "logic low" to "logic high" (and the complementary, via the line 110b supplied signal (outb) from "logic high" to "logic low"), that at the input of the second transmission gate 113b supply voltage (vddq) connected to the transmission gate output, and thus via the line 114b to the level converter output 112 ,

This changes, as in 3 is illustrated, that at the level converter output 112 tapped output signal (DatoV) from a "logically low" to a "logically high" state.

Then change that at the second output 107b the amplifier circuit 102 Tapped signal (out) its state again from "logic high" to "logic low" (and the complementary signal (outb) from "logic low" to "logic high"), that at the input of the second transmission gate 113b applied supply voltage (vddq) again from the output of the second transmission gate 113b However, the output signal (DatoV) remains separate at the level converter output 112 according to 3 initially still in a "logically high" state.

Only when that at the first exit 107a the amplifier circuit 102 tapped, over the line 111 the first control input of the first transmission gate 113a supplied signal (bout) changes from "logic low" to "logic high" (and the complementary signal (boutb) from "logic high" to "logic low") becomes the first transmission gate 113a conductive, and thus the output of the first transmission gate 113a - and thus over the line 114a also the exit 112 of the level converter - pulled to ground (gnd).

This changes, as in 3 is illustrated, that at the level converter output 112 tapped output signal (DatoV) from a "logically high" to a "logically low" state.

Then change that at the first exit 107a the amplifier circuit 102 tapped signal (bout) its state again from "logic high" to "logic low", the input of the first transmission gate 113a again separated from its output: the output signal (DatoV) at the level converter output 112 but remains in accordance 3 initially still in the "logically low" state (since the second transmission gate 113a initially the input and output are separated from one another, ie those at the input of the second transmission gate 113b supply voltage (vddq) is not yet switched through at its output).

That at the level converter output 112 tapped output signal (DatoV) thus shows - unlike that at the outputs 107a respectively. 107 the amplifier circuit 102 applied signals (bout or out) - no (or only insignificantly large) distortions; in particular, the "logically low" state of the output signal (DatoV) lasts essentially the same length as its "logically high" state.

At the in 2a and 2 B level converter shown occurs only a relatively small (additional) signal delay. Furthermore, according to the level converter 2a and 2 B Even with relatively high temperature fluctuations (and thereby caused changes in the properties of the components used), the distortions contained in the amplifier circuit output signals (bout or out) are almost completely compensated.

1

level converter

2

amplifier circuit

3a

inverter

3b

inverter

4a

p-channel field effect transistor

4b

p-channel field effect transistor

5a

n-channel field effect transistor

5b

n-channel field effect transistor

6a

entrance

6b

entrance

7a

output

7b

output

8th

driver stage

9

management

10

management

11

output

12

output

101

Level converter section

101b

Level converter section

102

amplifier circuit

103a

inverter

103b

inverter

104a

p-channel field effect transistor

104b

p-channel field effect transistor

105a

n-channel field effect transistor

105b

n-channel field effect transistor

106a

entrance

106b

entrance

107a

output

107b

output

109a

management

109b

management

110a

management

110b

management

111

management

111b

management

112

output

113a

Transmission gate

113b

Transmission gate

114a

management

114b

management

Claims (12)

Level conversion device ( 101 . 101b ) for converting a signal (in) having a first voltage level (vint) into a signal (DatoV) which has a second voltage level (vddq) different from the first voltage level (vint), the level conversion device ( 101 . 101b ) an amplifier device ( 102 ), and in order to generate the signal (DatoV) having the second voltage level (vddq) in addition to a first output signal (out) of the amplifier device ( 102 ) a second, different amplifier output signal (bout) is additionally used, characterized in that, with the first amplifier device output signal (out), or a signal derived therefrom, a first transmission gate ( 113b ) is driven, and with the second amplifier device output signal (bout), or a signal derived therefrom, a second transmission gate ( 113a ). "Level conversion device ( 101 . 101b ) according to claim 1, wherein the first and the second amplifier output signal (out, bout) are mutually complementary signals. Level conversion device ( 101 . 101b ) according to claim 1 or 2, wherein it is triggered by an edge of the first amplifier device output signal (out) that the signal (DatoV) having the second voltage level (vddq) changes from a first to a second state, and wherein one opposite the Edge of the first amplifier device output signal (out) is triggered in time-displaced edge of the second amplifier device output signal (bout) that the signal (DatoV) having the second voltage level (vddq) changes from the second back to the first state. Level conversion device ( 101 . 101b ) according to claim 3, wherein the triggering edge of the first amplifier device output signal (out) is a positive edge, and the triggering edge of the second amplifier device output signal (bout) is also a positive edge. Level conversion device ( 101 . 101b ) according to claim 3, wherein the triggering edge of the first amplifier output signal (out) is a negative edge and the triggering edge of the second amplifier output signal (bout) is also a negative edge. Level conversion device ( 101 . 101b ) according to one of the preceding claims, in which, with the aid of the first amplifier device output signal (out), or the signal derived therefrom, an input of the first transmission gate ( 113b ), which has a relatively high voltage, to an output ( 114b ) of the first transmission gate ( 113b ) is switched through. Level conversion device ( 101 . 101b ) according to one of the preceding claims, in which, with the aid of the second amplifier device output signal (bout) or the signal derived therefrom, an input of the second transmission gate ( 113b ), at which a relatively low voltage, in particular earth, is present at an output ( 114a ) of the second transmission gate ( 113a ) is switched through. Level conversion device ( 101 . 101b ) according to claim 7, wherein the outputs ( 114a . 114b ) the transmission gates ( 113a . 113b ) are connected. Level conversion device ( 101 . 101b ) according to one of the preceding claims, in which the first voltage level (vint) is lower than the second voltage level (vddq). Level conversion device ( 101 . 101b ) according to claim 9, wherein the first voltage level (vint) is between 1.2 V and 1.9 V, in particular between 1.4 V and 1.6 V, and the second voltage level (vddq) between 1.5 V and 2.2 V, especially between 1.7 V and 1.9 V. Level conversion device ( 101 . 101b ) according to one of the preceding claims, in which the amplifier device ( 102 ) several cross-coupled transistors ( 104a . 104b . 106a . 106b ) having. Level conversion device ( 101 . 101b ) according to claim 11, wherein the transistors ( 104a . 104b . 106a . 106b ) Are field effect transistors.