DE102021203365A1 - Method for testing a measuring system and test system - Google Patents

Abstract

The invention relates to a method and a test system for testing a measurement system, in particular a measurement system for distance measurement, especially in automobiles, in which the measurement system has a measurement cycle and periodically emits a measurement pulse at a time with the measurement cycle, the measurement pulse being recorded by a test system which generates an output pulse and transmits it to the measuring system, the output pulse being delivered with a delay in relation to the measuring pulse, which is composed of a multiple of the system clock plus a simulation delay that correlates to a simulated, predetermined running time of the measuring pulse. The test system preferably has a system clock with a clock signal and a phase shift of the measurement pulse in relation to the clock signal is determined, the phase shift being taken into account when determining the delay time.

Description

The invention relates to a method for testing a high-resolution measuring system with the aid of a test system, the measuring system being in particular a measuring system for distance measurement, especially in automobiles. The invention also relates to a test system for such a method.

To test the functionality and functionality of measuring systems, simulation or test systems are often used which simulate the measured variables to be measured by the measuring system, for example to map different real scenarios in order to check how the measuring system and an associated control system react.

An example of this are measurement systems for distance measurement, especially in the motor vehicle sector, as they are increasingly being used for assistance systems or for autonomous driving, e.g. for Advanced Driving Systems (AD), Automated and Assisted Driving Systems (ADAS) or for Connected and Automated Vehicles (CAVs) .

Distance measuring systems are designed, for example, as radar, ultrasound or laser systems (LIDAR). These are generally based on the fact that a measuring pulse is transmitted and a reflected response signal is recorded and evaluated. Based on the transit time until the response signal arrives, conclusions are drawn about the distance of an object that led to the reflection of the measurement pulse.

It is known to simulate response signals of this type for different distances with the aid of or in test systems. Such a test system typically has a receiver and a transmitter. The measuring pulse emitted by the measuring system is recorded by the receiver and an output pulse is emitted via the transmitter, which simulates the response signal. A defined delay is set between the reception of the measurement pulse and the emission of the output pulse, which is correlated to the transit time of a real response signal that is to be simulated.

Such test arrangements, in which the real measuring system to be tested is integrated into the test environment, are also referred to as hardware in the loop systems (HIL). The system to be tested or the hardware to be tested, that is to say in the present case the measuring system, are generally referred to as DUT (Device Under Test).

Setting the delay between the measuring pulse and the output pulse as precisely as possible is of particular importance. Due to the high speed of signal propagation (e.g. the speed of light in the case of LIDAR), an inaccurate setting of the delay leads to inaccurate results. This is particularly noticeable at close range, i.e. when distances in the range of a few meters or a few tens of meters are to be reliably simulated.

Starting from this, the invention is based on the object of enabling reliable testing of such measuring systems which are based on the evaluation of the transit times of a measurement pulse, specifically with the aid of a test system which simulates the transit time of a measurement pulse by outputting a delayed output pulse.

The object is achieved according to the invention by a method for testing and in particular also for validating the functionalities and the functionality of a high-frequency measuring system, in particular a measuring system for distance measurement, specifically in motor vehicles. The measuring system generally has a measuring cycle and periodically sends out a measuring pulse that is cycled with the measuring cycle. The measuring pulse is recorded by a test system which generates a delayed output pulse as a measure for the measured variable to be measured by the measuring system. This is in particular the transit time of the measurement pulse or, derived from this, a distance and thus a distance to a (fictitious) object. This output pulse therefore simulates a response signal or a reflected signal which would be reflected on a real object at a predetermined distance from the measuring system.

With the help of the test system, the measuring system is therefore tested for its function and, in particular, it is validated whether the measuring system corresponds to a desired requirement profile.

The output pulse is delivered delayed by a delay time in relation to the measurement pulse output by the measurement system, the delay time being composed of an in particular integer multiple, in particular the simplicity of the measurement cycle plus a simulation delay. The simulation delay correlates with a simulated run time of the measuring pulse, that is, a run time that the measuring pulse would need until it would be detected again by the measuring system after a reflection on a (real) object. The simulation delay therefore correlates to a (fictitious) distance.

This refinement is based on the consideration that, especially with short intervals to be simulated and thus with short transit times, the problem arises that internal signal processing times of the test system can lead to a delayed delivery of the output pulse. This would falsify the measurement result. In particular, there is a risk that, in the case of short intervals, the simulation delay time to be set is less than the signal processing time of the test system, which is also referred to as the dead time.

By setting the delay time as the sum of an integer multiple of the measuring cycle plus the simulation delay, the output pulse and thus the simulated response signal is shifted to a subsequent measuring cycle, preferably to the immediately following measuring cycle of the measuring system. A respective measuring cycle is defined by the periodically emitted measuring pulses. A cycle time is defined by the measuring cycle, namely by the time between two successive measuring pulses.

The test system therefore receives a first measurement pulse and sets the delay time in such a way that the output pulse that is emitted in the measurement system only arrives at the measurement system after a further, in particular the following, second measurement pulse. The delay time is set in such a way that the time interval between the further measuring pulse and the arrival of the output pulse at the measuring system corresponds exactly to the transit time that the measuring pulse would need until it returns to the measuring system after a reflection on an object at a defined distance from the measuring system hits. The measuring system then evaluates the transit time between the further (second) measuring pulse and the output pulse. This measure effectively avoids delays caused by signal processing times and enables the delay time to be set with high precision, so that even short distances can be reliably simulated.

Another advantage of the shifting is that a distance from an object can also be simulated, the distance of which lies within the distance range from the measuring system to the test system. Such short distances, for example in the range of less than 10 m, could not previously be simulated / emulated.

If a high-frequency measuring system is mentioned here, this is understood in particular to mean that the measuring rate of the measuring system is in the kilohertz range, specifically in the range between 10 kHz and 100 kHz and preferably, for example, in the range from 30 kHz to 60 kHz, for example 50 kHz . A measuring cycle of 50 kHz corresponds to a cycle time (cycle time, cycle period) of 20 µs. The pulse duration of the measuring pulse is typically well below this cycle time, for example by at least a factor of 100. Typical pulse durations of the measuring pulse are, for example, 200 ns.

With the expression "the simulation delay correlates to a simulated running time of the measuring pulse" it is taken into account that boundary conditions for setting the shift of the output pulse output by the test system (i.e. for setting the time difference between the measuring pulse arriving at the test system and the output pulse) In particular, the physical distance between the measuring system and the test system and, in addition, preferably also the dead time, must be taken into account.

The simulation delay usually corresponds exactly to the total running time of the measuring pulse, which it needs for the distance "measuring system - (fictitious) object in a defined measuring distance - measuring system", however, taking into account a real running time for the (double) distance between measuring system and test system is needed.

The (total) delay time set by the test system contains, in addition to a variable part that can be set by the test system, usually also a fixed part, namely the dead time.

In general, the test system sets a simulation delay in such a way that in the measuring system after a first emitted measuring pulse, the output pulse emitted by the test system does not arrive at the measuring system until a subsequent measuring cycle, namely in such a way that the time interval between the measuring pulse of the subsequent measuring cycle and that of the Measuring system incoming output pulse corresponds to the (simulated) distance between the measuring system and the (simulated) object.

If the (fictitious, virtual) measuring distance is greater than the distance (distance) between the measuring system and the test system, the simulation delay is determined from the total runtime minus the required real runtime of the signal for the distance between the measuring system and test system, i.e. the total runtime is the sum of the real runtime and the positive simulation delay.

If, on the other hand, the desired (fictitious, virtual) measuring distance is smaller than the distance (distance) between the measuring system and the test system, a (mathematically negative) simulation delay is determined from the required real runtime of the signal for the distance between the measuring system and the test system minus the total runtime, ie the total runtime is the sum of the real runtime and the negative simulation delay.

The dead time of the test system, i.e. the time required for signal processing until the output pulse is sent, is also determined by the input and output delays of the test system, including internal configuration settings (multiplexer). In particular, a specified system clock of the test system has a decisive influence on this. Such dead times can be, for example, 20 ns and more. This corresponds to a distance of 3 m and more. This means that without the compensation described above as a result of the shift by one measurement cycle, a possible measurement result for a simulated close range would be greatly falsified.

According to a preferred embodiment, the test system has a system clock with a pulsed clock signal (clock signal) and a phase shift of the measurement pulse received from the test system in relation to the clock signal is determined. This phase shift is then taken into account and compensated for when determining the delay time.

This refinement is based on the consideration that for the detection of the measuring pulse in the event of an unfavorable phase shift between the input of the measuring pulse and the clock signal, almost a complete system clock, i.e. the time between two successive clock signals, can pass and that at least again until the output pulse is emitted a system clock can pass. A total of at least two system clocks can therefore elapse before the output pulse is emitted. This creates the above-mentioned inaccuracy of several meters - for example with a system cycle of 10 ns - and, because of its asynchronous nature, leads to clock jitter and thus also to fluctuations in distance. In order to at least reduce this inaccuracy, the phase relationship, that is to say the time offset between the measuring pulse and the clock signal, is determined. The reference point for the detection of the phase relationship is typically the rising or falling edge of the respective signal pulse of either the measuring pulse or the (pulsed) clock signal.

The determined phase relationship is taken into account when the output pulse is output, preferably in such a way that the phase relationship between the measurement pulse and the system clock corresponds to the phase relationship of the output pulse and the system clock plus the simulation delay time.

To determine the phase shift, the measurement pulse is preferably applied to a measurement block with a large number of individual delay modules. Each of these delay modules has a time delay, i.e. a defined period of time, the delay being the time that elapses until - after the application of an input signal - the state of the delay module changes and it virtually switches. Such delay modules are known in principle. In particular, they are implemented, for example, by inverters or also by multiplexers. To determine the phase shift, the number of delay modules is determined which switched in the period between the measurement pulse, in particular a pulse edge of the measurement pulse, and the clock signal, in particular a pulse edge of the clock signal. The number of switched delay modules multiplied by the duration of the delay results in the phase shift.

This measuring block generally has a serial structure, so that the individual delays add up linearly. For example, the individual delay modules are arranged in series so that the delay results from adding the individual delays of the delay modules.

The delay modules preferably have a time duration for the delay in the range from 1/10 to 1/100 or also to 1/1000 of the system clock. Alternatively, the delays can also be implemented in binary steps, e.g. in the range 1/8 to 1/128 or also up to 1/1024 of the system clock. In comparison to a system without taking the phase shift into account, the accuracy of the acquisition of the incoming measurement pulse is increased by the corresponding factor, for example by a factor of 10.100 or 1000.

The system clock is preferably in the range between 50 MHz and 500 MHz, for example. In particular, it is 100 MHz or 400 MHz. This corresponds to cycle times of 10 ns or 2.5 ns. The time duration for the delay of the delay modules is accordingly, for example, in the range of 100 ps, with a cycle time of 10 ns. In general, the delay of a respective delay module is in the range between 10ps and 500ps, in particular in the range between 50ps and 300ps.

The number of delay modules in the measuring block is preferably dimensioned such that the duration of the delay per module multiplied by the number of modules at least and preferably precisely results in the cycle time. If the delay in the selected example is 100 ps, then 100 modules are used with a cycle time of the system cycle of 10 ns, the total delay of which results in 10 ns.

The system cycle, i.e. the cycle time of the test system, is typically around a factor of 1000 less than the cycle time of the measurement cycle of the Measuring system. In other words, the cycle time of the test system is generally about a factor of 1000 faster than the measurement cycle, that is, than the cycle time of the measurement system.

1. a) Zunächst wird wie zuvor beschrieben die Phasenverschiebung ermittelt.
2. b) Anschließend oder gleichzeitig mit der Ermittlung der Phasenverschiebung wird der Messpuls mit dem Taktsignal synchronisiert. Dies bedeutet, dass der Messpuls so weit zeitlich verschoben (verzögert) wird, dass er keine Phasenverschiebung mehr zum Taktsignal aufweist. Dies bedeutet insbesondere, dass eine Pulsflanke des Messpulses und des Taktsignals zeitgleich vorliegen. Hierzu werden übliche Verfahren zur Synchronisierung zweier Impulse eingesetzt.
3. c) Weiterhin erfolgt ein zeitliches Verschieben des Messpulses um ein ganzzahliges Vielfaches des Systemtaktes. Hierzu weist das Testsystem, speziell eine Steuereinheit des Testsystems, welche beispielsweise durch ein FPGA (Field Programmable Gate Array) gebildet ist, eine erste insbesondere einstellbare Verzögerungsschaltung auf.
4. d) Danach erfolgt ein weiteres Verschieben des Messpulses entsprechend der zuvor ermittelten Phasenverschiebung. Für die Verschiebung des Messpulses entsprechend der Phasenverschiebung ist eine weitere (zweite) Verzögerungsschaltung in der hardwaretechnischen Umsetzung vorgesehen.

In a preferred embodiment, the following steps are carried out:

1. a) First, the phase shift is determined as described above.
2. b) Subsequently or simultaneously with the determination of the phase shift, the measuring pulse is synchronized with the clock signal. This means that the measurement pulse is shifted (delayed) in time to such an extent that it no longer has a phase shift in relation to the clock signal. This means in particular that a pulse edge of the measurement pulse and the clock signal are present at the same time. The usual methods for synchronizing two pulses are used for this purpose.
3. c) Furthermore, the measuring pulse is shifted over time by an integral multiple of the system clock. For this purpose, the test system, specifically a control unit of the test system, which is formed, for example, by an FPGA (Field Programmable Gate Array), has a first, in particular adjustable, delay circuit.
4. d) The measurement pulse is then shifted further in accordance with the previously determined phase shift. A further (second) delay circuit is provided in the hardware implementation for shifting the measurement pulse in accordance with the phase shift.

According to a variant, after this further shifting, the measuring pulse again assumes the same phase position in relation to the system clock as it was before the synchronization. This means that the shifted signal (measuring pulse) again assumes exactly the same phase position with respect to the clock signal. In this way, a time interval between the input of the measuring pulse and the clock signal is maintained, so to speak, during the shift.

Basically, the measuring pulse is shifted by the simulation delay before the output pulse is output. In principle, this can also take place before step d), in which the phase shift is taken into account.

Through these individual steps it is achieved on the one hand that the phase shift is determined first, the subsequent synchronization enables a defined shift by a multiple of the system clock and then the original phase position is restored by the additional shift by the previously determined phase shift, or at least taken into account.

The shift resulting from steps c) and d) is preferably set in such a way that, according to a first embodiment variant, this shift corresponds exactly to the cycle time or an integer multiple of the measurement cycle, i.e. the measurement pulse is shifted by exactly one or more measurement cycles.

In a preferred embodiment, on the other hand, it is provided that this shift is set in such a way that the shift corresponds to the measuring cycle (or an integer multiple of the measuring cycle) minus a distance window. The distance window is set, for example, to 5-20% of the measuring cycle, that is to say, for example, to 0.5 microseconds to 5 microseconds and in particular to 1-2 microseconds. This creates a time interval between the shifted measurement pulse and the subsequent further (second) measurement pulse that is received by the test system.

As already mentioned, the shift by the simulation delay and - if the distance window is set - plus by the distance window is then preferably carried out in a (last) step before the output pulse is emitted. For this further shift by the simulation delay and, if necessary, supplemented by the distance window, a further, third delay circuit is preferably provided in the hardware implementation. The delay circuit is also referred to as a delay line

For the shift by the simulation delay, the dead time of the test system must generally be taken into account. This is known or can be determined. The delay set by the delay circuit therefore takes into account the dead time that is already present.

In the present case, it is of particular importance that the incoming measurement pulse is shifted by an integral multiple of the system clock. The shift is therefore determined in particular exclusively according to the system clock of the test system.

In a preferred embodiment, the test system is designed such that it is used to simulate a distance (of the measuring system) to an object which is smaller than the physical distance between the test system and the measuring system, so that the object to be simulated is between the measuring system and the Test system lies. Ie the simulation delay is selected such that the simulated transit time and evaluated by the measuring system corresponds to a distance which is smaller than the physical distance between the test system and the measuring system. In particular, distances that are less than 10m or less than 3m are simulated. This is not possible with conventional test procedures.

The method described here with the shift by at least and in particular precisely one measuring cycle in a subsequent measuring cycle therefore advantageously enables even the shortest distances to be simulated. The entire distance range (measuring system to the fictitious object) can therefore be simulated by moving. The decisive factor here is that the signal processing time (dead time) and the distance between the test system and the measuring system no longer play a role and are virtually eliminated.

For this purpose, the simulation delay is selected accordingly so that the output pulse is received by the measuring system very close in time after the further (second) measuring pulse.

Since the delay time between the incoming measuring pulse and the output pulse is made up of a multiple of the measuring cycle plus a simulation delay corresponding to the simulated running time, this is purely mathematically negative. In this case, the variant with the distance window described above is used in particular.

Such a test system typically has several (simulation) channels, with different simulation delays being fixed or programmable for the channels. Different simulated distances are set by selecting a respective channel.

To determine the delay time that is set by the test system, a (real) signal transit time between the measuring system and the test system is also regularly taken into account. It is therefore taken into account that the test system has a predetermined measuring distance from the measuring system, which is typically in the range of a few meters, for example from 0.5 m to 4 m.

The test system can preferably be switched between normal operation and compensation operation, the delay time being determined as described above only in compensation operation, so that the measuring pulse is shifted into a subsequent measuring cycle of the measuring system. In the actual setting of the delay time (which is achieved by the delay circuits (delay lines) described, the dead time is preferably also taken into account.

In contrast, in normal operation, only the simulation delay is set (preferably also taking into account the dead time) over which the distance is simulated. These two operating modes can also be viewed as short-range mode and remote mode, with the compensation mode taking place in short-range mode. In normal operation or in remote mode, in which, for example, distances of 100 m or more are simulated, the signal processing time of the test system has little or no influence. However, the dead time can also be taken into account when setting the DelayLine delay.

For the correct setting of the delay time in compensation mode, the exact determination of the phase shift is also essential. Since delay modules are used to determine the phase shift, it depends on the quality of these delay modules. As described above, the delays of these delay modules are in the range of 100 ps. Investigations have shown that due to component tolerances - for example between modules from different production batches of such delay components - the delay can vary greatly, for example by up to a factor of 2. In unfavorable cases, this means that 2 test systems, which are basically identical, but which have delay modules from different batches, can lead to different delays of the output pulse, so that the distances determined by the measuring system fluctuate greatly.

In order to avoid this, a calibration of the test system is provided in an expedient embodiment. A delay time of the delay modules is determined individually for the test system and taken into account when determining the delay time and especially when determining the phase shift. For this purpose, a calibration unit, in particular, is provided as a fixed component of the test system, which is integrated in the control unit, at least in a control device having the control unit.

For this purpose, a ring oscillator with delay components is preferably designed as the calibration unit, specifically the ring oscillator consists of these delay components and the duration of the delay of a respective delay component is calculated based on a natural frequency of the ring oscillator. Using the natural frequency of the ring oscillator, a total delay time of the delay components used for the ring oscillator is first determined and this is then divided by the number of delay components used.

Furthermore, the delay modules used are according to a first one preferred embodiment to structurally identical components, as they are also used for the measuring block, via which the phase shift is determined. This means that the ring oscillator is designed as an additional unit in addition to the measuring block. If one speaks of a structurally identical component, this is understood to mean that the components come from the same production batch.

As an alternative to this, all or at least some of the delay components used for the measuring block are part of the calibration unit, specifically the ring oscillator, and preferably form this. When the natural frequency of the ring oscillator is recorded, the delay times of the delay components used are determined immediately.

The real measuring system is preferably a LIDAR system, which is preferably used in motor vehicles for an assistance system. In such a LIDAR system, laser pulses are therefore emitted as measurement pulses. The measuring pulse and the output pulse of the test system are therefore optical signals.

The object is also achieved according to the invention by a test system having the features of claim 16. The advantages and preferred embodiments set out above with regard to the method can also be applied to the test system in a corresponding manner.

The test system generally has a receiver for receiving a measurement pulse, in particular an optical measurement pulse, which is clocked with a measurement cycle of a real measurement system known to the test system. Furthermore, the test system comprises a transmitter for outputting an output pulse, which is also preferably optical. Finally, the test system has at least one control unit which sets a delay time between the reception of the measurement pulse and the transmission of the output pulse, which is selected such that the output pulse is delivered with a delay in relation to the measurement pulse by a delay time that is composed of a multiple of Measuring cycle plus a simulation delay, which correlates to a simulated, specified runtime of the measuring pulse.

The control unit is, in particular, an integrated electronic circuit (IC) which, in particular, is embodied in a structural unit. An FPGA is preferably used. In addition, the control unit can alternatively also be designed as an ASIC (Application Specific Integrated Circuit), ASSP (Application Specific Standard Product) or SOC (System on Chip).

The programming of this control unit, that is to say the setting up of the hardware in such a way that it executes the method steps specified above, takes place in particular by means of a hardware description language known per se. (Hardware Description Language, HDL). An example of this is VHDL. Other hardware description languages can also be used (e.g. Verilog).

• 1 ein Schaubild eines Messaufbaus mit einem Messsystem und einem Testsystem,
• 2 eine Gegenüberstellung des zeitlichen Verlaufs eines vom Messsystem ausgegebenen Messpulses und eines vom Testsystem ausgegebenen Ausgangspulses,
• 3a,b die Gegenüberstellung der zeitlichen Verläufe der vom Messsystem ausgegebenen Messpulse gegenüber einem um eine Feinverschiebung verschobenen Puls sowie gegenüber dem vom Testsystem insgesamt um eine Verzögerungszeit verzögert ausgegebenen Ausgangspuls zur Erläuterung der Ermittlung der Verzögerungszeit, wobei 3a eine Situation erläutert, bei der der zu simulierende Gegenstand einen Abstand größer dem Abstand zwischen Testsystem und Messsystem aufweist und 3b eine Situation erläutert, bei der bei der der zu simulierende Gegenstand einen Abstand kleiner dem Abstand zwischen Testsystem und Messsystem aufweist,
• 4 eine Gegenüberstellung der zeitlichen Verläufe eines Taktsignals eines Systemtakts des Testsystems gegenüber einem eingehenden Messpulses sowie weiterhin gegenüber einem mit dem Systemtakt synchronisierten Messpuls und schließlich gegenüber dem um die Feinverschiebung verschobenen Puls zur Erläuterung der Bestimmung einer Phasenverschiebung zwischen Messpuls und Systemtakt,
• 5 eine Blockbild-Darstellung einer Schaltungsanordnung mit Delay-Bausteinen, die einen Mess- und Synchronisierungsblock bildet zur Bestimmung der Phasenverschiebung zwischen Messpuls und Systemtakt sowie zur Synchronisierung des Messpulses mit dem Systemtakt,
• 6 ergänzend zu der Blockbild-Darstellung gemäß der 5 die Gegenüberstellung der zeitlichen Verläufe des Systemtaktes, des eingehenden Messpulses und der ausgehenden Signalpegel der Delay-Bausteine,
• 7 eine vereinfachte Blockbild-Darstellung zur Illustration der einzelnen Verzögerungsschritte zwischen dem eingehenden Messpuls und dem ausgehenden Ausgangspuls sowie
• 8 eine Blockbild-Darstellung einer Steuervorrichtung des Testsystems mit einer Steuereinheit, über die die Verzögerung zwischen eingehendem Messpuls und ausgehendem Ausgangspuls erzeugt wird.

An exemplary embodiment of the invention is explained in more detail below with reference to the figures. These show in simplified representations:

• 1 a diagram of a measurement setup with a measurement system and a test system,
• 2 a comparison of the time course of a measuring pulse output by the measuring system and an output pulse output by the test system,
• 3a, b the comparison of the temporal progressions of the measuring pulses output by the measuring system with a pulse shifted by a fine shift and with the output pulse output by the test system delayed by a total delay time to explain the determination of the delay time, wherein 3a explains a situation in which the object to be simulated has a distance greater than the distance between the test system and the measuring system and 3b explains a situation in which the object to be simulated has a distance smaller than the distance between the test system and the measuring system,
• 4th a comparison of the temporal progressions of a clock signal of a system clock of the test system against an incoming measurement pulse and also against a measurement pulse synchronized with the system clock and finally against the pulse shifted by the fine shift to explain the determination of a phase shift between measurement pulse and system clock,
• 5 a block diagram representation of a circuit arrangement with delay modules, which forms a measurement and synchronization block for determining the phase shift between measurement pulse and system clock and for synchronizing the measurement pulse with the system clock,
• 6th in addition to the block diagram representation according to 5 the comparison of the timing of the system clock, the incoming measuring pulse and the outgoing signal level of the delay modules,
• 7th a simplified block diagram to illustrate each Delay steps between the incoming measuring pulse and the outgoing output pulse as well
• 8th a block diagram representation of a control device of the test system with a control unit, via which the delay between the incoming measurement pulse and the outgoing output pulse is generated.

In the figures, parts with the same effect are provided with the same reference symbols.

The Indian 1 The measurement or test setup shown essentially comprises a real measurement system 2 as well as a test system 4th . The real measuring system is, in particular, a system for distance measurement, such as is used in particular in motor vehicles. Specifically, this is a LIDAR system. The measuring system 2 assigns a transmitter 6th for outputting a measuring cycle signal pin code , i.e. a sequence of periodically recurring measurement pulses PIN1 , PIN2 ... PIN on. In the case of a LIDAR system, these are laser pulses. Furthermore, the measuring system 2 a recipient 8th to receive a signal pulse. Furthermore, the measuring system 2 a processing unit 10 on the basis of which a signal transit time between the sending and receiving of the measuring pulse is determined and a distance to an object is derived from this.

In real operation, this distance measurement is used, for example, as an input variable for an assistance system in an autonomous or partially autonomous driving operation of a motor vehicle. About the functionality or the functionality of the measuring system 2 The test system is to be tested on a laboratory scale (Device Under Test, DUT) 4th intended. This is immediately in front of the measuring system 2 and to this by a distance a positioned at a distance. The test system 4th also assigns a recipient 8th to receive the measuring cycle signal pin code as well as a transmitter 6th to deliver an output pulse POUT on. Furthermore, the test system 4th a control unit 16 with the help of which a delay time D. between an incoming measuring pulse PINn and the output pulse POUT is set (see also 3 ). The test system 4th simulates a distance to an object especially (virtual distance), therefore simulates a virtual object 12th at a distance a + va from the measuring system 2 . These are in the test system 4th one or more virtual distances especially deposited and the test system 4th determines corresponding virtual delays, which are subsequently referred to as simulation delays VD are designated.

The time sequence between the measuring pulse pin code and output pulse POUT is simplified in the 2 shown. It can be seen from this that - in relation to the rising pulse edge of the two pulses in each case - the output pulse POUT the simulation delay VD is delayed. This delayed output thus becomes the virtual distance especially simulated. Preferably the test system 4th different virtual distances especially can be specified. This is done, for example, using tables in the control unit 16 be made known.

That to the 1 and 2 The system described works comparatively problem-free at large virtual distances of, for example, 100 m or more. When simulating a close range, i.e. when checking how the measuring system is 2 reacts to objects in the vicinity of, for example, only a few 10 m or less than 10 m, but problems arise due to the extremely short signal transit times due to the required signal processing time within the test system 4th .

For example, in the 3a is shown in the lower area by the dashed arrows and by the dashed output pulse, there is the problem that the simulation delay VD is less than the required signal processing time, including dead time TD called. This means that during normal operation the test system 4th Cannot simulate a close range or can only inadequately simulate it.

When setting the total delay D. or the simulation delay VD is this dead time TD to be taken into account. The virtual delay VD is composed, for example, of the dead time TD and a delay that can be set on the test system subsequently as a delay DL designated. For setting the delay DL a circuit device is implemented, the so-called DelayLine. The dead time can be calibrated or measured, for example by setting DL = 0 and measuring the time difference between the pulses POUT PIN .

The test system is used to simulate such a close range reliably and with high accuracy 4th now designed in such a way that the output signal POUT in total by the delay time D. is output based on the input of the measuring pulse PINn, whereby the delay time D. is dimensioned such that the output pulse POUT in a subsequent measuring cycle of the measuring clock signal pin code , that is, following a further measuring pulse, in particular following a second measuring pulse PIN2 is issued. This situation is in the 3a shown. This representation is still a simplified representation, since there is a required signal transit time between the measuring system 2 and the test system 4th is not yet taken into account. In the simplified representation it is assumed in particular that the Delivery of the measuring pulse pin code on the measuring system 2 and its input to the test system 4th almost at the same time. The simulation delay is shown here with VD ' marked.

The delay time D. is dimensioned in such a way that the output pulse POUT the simulation delay VD ' offset to the further measuring pulse PIN2 he follows. The output pulse POUT generally has a pulse duration PW on. In relation to the reference system of the measuring system 2 receives this after delivery of the further measuring pulse PIN2 a simulated, reflected output pulse POUT , the one to delay the simulation VD ' is received with a delay and determines a distance from this simulated transit time.

Overall, therefore, the output pulse becomes POUT (exactly) by an integer multiple of the cycle time of the measuring cycle, hereinafter referred to as the measuring cycle Tp plus the simulation delay VD ' postponed. For the delay D. therefore results: $$\text{D.}=\text{Tp}+\text{VD}\text{'}$$

An intermediate step takes place within the test system 4th first a fine adjustment PFT of the pulse as specifically related to the 4th is explained in more detail. This fine shift PFT is overall preferably selected in such a way that the pulse shifted here by a time interval window X from the further measuring pulse PIN2 is spaced.

The fine shift therefore results in $$\text{PFT}=\text{Tp}-\text{X}$$

For the delay D. then results: $$\text{D.}=\text{Tp}+\text{VD}\text{'}=\text{PFT}+\text{X}+\text{VD}\text{'}$$

For the delay to be set on the test system using the DelayLine DL for the (further) postponement of the PFT The finely shifted pulse results, taking into account the dead time: $$\text{DL}+\text{TD}=\text{D.}-\text{PFT}=\text{X}+\text{VD}\text{'}$$

The adjustable delay of the DelayLine DL thus results in: $$\text{DL}=\text{X}+\text{VD}\text{'}-\text{TD}$$

In the previous consideration in 3a remained the real distance a between test system 4th and measuring system 2 still out of consideration and initially there was only a computational simulation delay VD considered.

When determining one actually from the test system 4th simulation delay to be set below with VD " , however, it must be taken into account that the pulses pin code as POUT the real distance a , more precisely a route s at the time TS between the recipients 8th and transmitters 6th , have to go through. The following applies at least approximately: s = a = c * TS.

This is in the 3b shown, in which the time sequence of the measuring system 2 output measuring pulses, here referred to as P (DUT), is shown with. It is easy to see that between delivery P (DUT) and reception of the pulse PIN1 on the test system 4th a period of time TS passes.

Furthermore, a case is considered in which the virtual distance to be simulated especially is smaller than the distance a and thus negative as seen from the test system, ie the virtual object lies between the measuring system 2 and test system 4th . In this case, therefore, must be used in determining the delay D. according to 3b the simulation delay VD " arithmetically deducted from Tp and the result is: $$\text{D.}=\text{Tp}-\text{VD}\text{'}\text{'}=\text{PFT}+\text{X}-\text{VD}\text{'}\text{'}$$

For the DelayLine, i.e. for those on the test system in addition to the fine adjustment PFT The delay to be set results including the dead time: $$\text{DL}+\text{TD}=\text{D.}-\text{PFT}=\text{X}-\text{VD}\text{'}\text{'}$$

The adjustable delay of the DelayLine DL thus results in: $$\text{DL}=\text{X}-\text{VD}\text{'}\text{'}-\text{TD}$$

Whereby wg. va <a also applies: VD "<TS.

By shifting to a subsequent measuring cycle of the measuring system 2 there is the particular advantage that the output pulse POUT virtually in any proximity to the second measuring pulse PIN2 can be delivered and thus virtually any distance from the measuring system 2 can be simulated from to an object, in particular also virtual distances especially that are smaller than the distance a are and between the measuring system 2 and test system 4th lie. The simulation delay is chosen so that taking into account the real distance a with the measuring system 2 the output pulse POUT so soon after the second output measuring pulse P (DUT) in the measuring system 2 is received (and thus before the input of the second measuring pulse PIN2 with the test system 4th issued) that the measuring system 2 evaluates a distance which is smaller than the physical distance a to the test system.

In this case, the output pulse must be POUT from the test system 2 be issued before the measuring system 2 the second measuring pulse PIN2 gives away. It is therefore a mathematically negative simulation delay for the equation D = Tp - VD " VD " required as shown above.

• Das Testsystem 4, speziell die Steuereinheit 16, die bevorzugt als ein FPGA ausgebildet ist, weist ein Systemtakt-Signal CLK auf bzw. wird mit einem solchen beaufschlagt. Dieses Systemtakt-Signal CLK weist eine Takt- oder Zykluszeit T auf, die nachfolgend auch kurz als Systemtakt T bezeichnet wird. Der Systemtakt T liegt dabei typischerweise im Bereich von beispielsweise 2,5 ns bis 50 ns und speziell bei 10 ns, was einer Taktung von 100 MHz entspricht. Typischerweise sind bei diesem Systemtakt die Pulsdauern des HI-Pegels und des LO-Pegels identisch.

The fine adjustment PFT takes place in all cases as follows, based on the 4th is explained:

• The test system 4th , specifically the control unit 16 , which is preferably designed as an FPGA, has a system clock signal CLK on or is acted upon by such. This system clock signal CLK has a clock or cycle time T which is also referred to below as the system clock T referred to as. The system clock T is typically in the range of, for example, 2.5 ns to 50 ns and especially 10 ns, which corresponds to a clock rate of 100 MHz. With this system clock, the pulse durations of the HI level and the LO level are typically identical.

In contrast to this system clock T is the measuring cycle Tp , i.e. the cycle time of the measuring cycle signal pin code significantly, for example by a factor of 1000 larger. The clock rate is, for example, in the range between 10 kHz and 100 kHz, for example 50 kHz, which corresponds to a measuring clock Tp of 20 µs. With the measuring cycle signal pin code If the HI level and the LO level are not the same, the HI level is specifically less than 1/5 or 1/10 of the cycle time of the measuring cycle, for example Tp and is, for example, 100 ns.

Coming back to 4th the measurement pulse PINn shows that this is asynchronous to the system clock signal CLK arrives. Between the measuring pulse PINn and the first pulse of the system clock signal CLK , which follows the measuring pulse PINn, there is a phase shift FT . As will be explained below, this phase shift is FT from the test system 4th determined and for the calculation of the delay time D. considered.

In order to enable a defined shifting of the measuring pulse PINn, this is initially in a 1st step with the system clock signal CLK synchronized, ie initially by the phase shift FT shifted so that the measuring pulse PINn is synchronized with the system clock signal CLK is.

Then the pulse is an integer multiple of the system clock T (n * T) shifted, so that the first result is the dotted, shifted pulse signal, which at this point in time is still synchronous with the system clock signal CLK is.

This pulse is then corresponding to the phase shift FT , namely the inverse phase shift T-FT postponed. The pulse signal shifted in this way is that by the fine shift PFT shifted signal. This pulse signal points in relation to the system clock signal CLK the same phase offset as the measuring pulse PINn.

The shift in the 2nd step by an integer multiple of the system clock n * T is such, ie n is selected accordingly, that the fine shift shown is PFT as PFT = Tp -X results. The distance window X is generally selected in this way and, for example, by appropriate programming of the control unit 16 (eg FPGA) is set so that it is, for example, in the range between 1-2 µs, in particular with the aforementioned cycle time of the measuring cycle Tp of about 20 µs. There is thus a sufficient distance between the shifted pulse and the further, 2nd measurement pulse PIN2 given.

That finely shifted pulse PFT will eventually around the gap window X plus the (calculated, without taking into account the real distance A) simulation delay VD postponed ( 3 ).

In an alternative training there is also the possibility that the entire fine adjustment PFT exactly one measuring cycle Tp and only the simulation delay in the last shift stage or delay stage VD must be done.

Overall, the fine adjustment corresponds to PFT a shift by an integral multiple of the system clock T . The total fine shift is the sum of several individual shifts as follows: $$\text{PFT}=\text{FT}+\text{n}*\text{T}+\text{T}-\text{FT}=\left(\text{n}+1\right)*\text{T}.$$

By means of this shift PFT therefore takes place - in connection with a shift around the distance window X - a highly precise shift of the incoming measuring pulse pin code by exactly one or more measuring cycles of the measuring cycle Tp . It should be emphasized that this shift PFT is determined solely by the system clock.

With this measure taking into account the phase shift FT are errors due to an asynchronicity between the measuring pulse pin code and system clock signal CLK avoided or reduced. By shifting the measuring cycle signal to a subsequent measuring cycle pin code it is ensured that even with short signal propagation times and thus short intervals to be simulated, no errors occur as a result of a required signal processing time (dead time).

For the step of determining the phase shift FT and at the same time also for the synchronization of the measuring pulse PINn with the system clock signal CLK instructs the control unit 16 (compare in particular 5 ) has a measurement and synchronization block, hereinafter referred to as the measurement block 18th is designated. This is a circuit arrangement of several modules. This measuring block 18th basically has a large number of individual delay modules D1, D2 ... Dn. Each of these delay modules Dn has a delay d between the application of an input signal and the delivery of an output signal. This means that there is a defined delay between an incoming signal and a switching of the respective delay module Dn (switching of the output level) d elapses. The individual delay modules Dn are, for example, inverters or also a multiplexer arrangement, as they are basically known.

The switching times of these blocks and thus the delay d is, for example, in the region of 100 ps. The measuring pulse PINn is applied to this switching arrangement with the delay modules Dn. According to the 5 the individual delay modules Dn are connected in series. After each module Dn, its switching status is picked up and evaluated. The time sequence is in the 6th shown. The first thing that can be seen is the system clock signal CLK and that of the phase shift FT shifted measuring pulse PINn. As soon as this is applied, it switches after the delay d the first delay module D1 and emits a high-level output signal, which is evaluated as switching. This output signal is delayed by the delay d subsequently to the second module D2 etc. At the next clock of the system clock signal CLK the switching states of the individual modules Dn are read out and the number of switched modules Dn is used if the delay is known d the phase shift with comparatively high accuracy FT determined.

At the same time this measuring block 18th also used to synchronize and thus shift the measuring pulse PINn, as shown in FIG 5 is shown in the lower part of the image. Such a synchronization of a pulse with a predetermined cycle is known in principle. The pulse is synchronized in parallel with the determination of the phase shift FT . The synchronized pulse SYNC we finally from the measuring block 18th submitted.

• Der eingehende Messpuls PIN wird zunächst am Messblock 18 eingespeist. In diesem erfolgt wie eben beschrieben die Bestimmung der Phasenverschiebung FT sowie die Synchronisation mit dem Systemtakt-Signal CLK. Dieses synchronisierte Signal SYNC wird in einem ersten Verarbeitungsblock 20 weiter verarbeitet. Und zwar wird insbesondere das Signal um ein Vielfaches des Systemtaktes T mithilfe einer ersten Verzögerungsschaltung um n*T verschoben. Dieses verschobene Signal wird einem zweiten Verarbeitungsblock 22 zugeführt, in dem eine weitere Verschiebung um die inverse Phasenverschiebung T-FT mit Hilfe einer zweiten Verzögerungsschaltung erfolgt, so dass sich insgesamt der feinverschobene Puls PFT ergibt. Die Phasenverschiebung FT wird mit Hilfe eines Transponders 27 zu T-FT gewandelt und dem zweiten Verarbeitungsblock 22 weitergeleitet. Mit Hilfe des Transponders 27 erfolgt daher eine Art Komplement-Bildung zur Phasenverschiebung FT. Die Erzeugung dieses feinverschobenen Pulses PFT erfolgt insgesamt innerhalb der Steuereinheit 16 in einem Kompensationsblock 24.

The total delay time D. and the individual steps for their determination are explained below using the illustration of 7th explained:

• The incoming measuring pulse pin code is first on the measuring block 18th fed in. The phase shift is determined in this as just described FT as well as the synchronization with the system clock signal CLK . This synchronized signal SYNC is in a first processing block 20th further processed. In particular, the signal is a multiple of the system clock T shifted by n * T using a first delay circuit. This shifted signal is sent to a second processing block 22nd supplied, in which a further shift by the inverse phase shift T-FT takes place with the help of a second delay circuit, so that overall the finely shifted pulse PFT results. The phase shift FT is made with the help of a transponder 27 to T-FT converted and the second processing block 22nd forwarded. With the help of the transponder 27 there is therefore a kind of complement formation for phase shifting FT . The generation of this finely shifted pulse PFT takes place entirely within the control unit 16 in a compensation block 24 .

In a subsequent third processing block 25th with a third delay circuit, the further shifting takes place by the distance window X plus the simulation delay before the output pulse POUT is issued.

A block diagram of the control unit 16 is a simplified representation in the 8th shown. This is preferably designed as an integrated circuit and in particular as an FPGA or has at least one such integrated circuit. The control unit 16 preferably has several signal processing units 17th each forming a channel. For example, there are 4 or more such signal processing units 17th implemented. The control unit 16 and thus at least one (and preferably exactly one) selected signal processing unit 17th is on the input side with the measuring pulse signal pin code is applied and gives the output pulse on the output side POUT the end. The signals pin code and POUT are preferably designed individually for each channel and configured separately. Inside the signal processing unit 17th is the one previously described Compensation block 24 shown, which has the finely shifted pulse PFT issues. Furthermore, there is the third delay block 25th shown, which on the input side - depending on the operating mode - either with the finely shifted signal PFT or with the measuring pulse pin code is applied directly. Finally, the output pulse becomes the output POUT issued.

The control unit 16 furthermore has a communication interface 26th via which the signal processing units17 can be set and configured.

This is an interface known per se, for example a so-called SPI interface (Serial Peripheral Interface, SPI bus). This typically has several connection pins (3 inputs: SCLK, CSN, MOSI, 1 output: MISO), via which input and output take place. In this way, several registers are specifically addressed in order to make settings. These registers 28 , 30th , 32 , 34 , 38 , 40 , 42 are generally referred to below as “connection” and are designed in several ways around the signal processing units 17th to be configured individually.

For example, via a (programming) connection 28 adjustable by how much the signal in the first delay block 20th is to be shifted, so it is in particular the factor n for the integer shift by the clock signal T set.

Basically there is also the possibility of changing the pulse width of the measuring pulse in addition to the shift, ie the pulse width PW (see. 3 ) of the output pulse POUT and to a desired value, for example an integral multiple of the cycle time T of the system clock (m * T).

In particular, safety requirements are specifically taken into account with regard to personal safety. For example, with laser systems, a maximum light intensity (laser safety) must be observed. This can be reduced by setting a short pulse width.

There is also a selection connection 30th provided, which can be used to switch between two operating modes, namely normal operation and compensation operation. In normal operation, the measuring pulse is pin code directly to the third processing block 25th while in compensation mode the measuring pulse PINn is supplied via the compensation block 24 and the finely shifted signal PFT the third processing block 25th is fed.

The processing block 32 monitors the input signal pin code (Watchdog). If there is no pulse edge within a specified time (eg 2 * Tp), this is indicated on a control connection 34 issued.

A calibration unit is also of particular importance 36 that come with a calibration connector 38 connected is.

There is also a configuration connection 40 provided over which the delay of the third processing block 25th is configurable. The virtual distance and thus the simulation delay are specifically set via this configuration connection VD given.

Finally, the communication interface 26th another switching connection 42 on with which the control unit 16 , at least one respective channel, can be activated, so that the output of the respective output pulse POUT can be activated or deactivated.

In addition, there is a debug interface as a register connection 44 provided in order to be able to make settings and measurements independently of the communication interface (SPI).

Via the configuration connection 40 is a fixed simulation delay VD for a respective signal processing unit 17th adjustable. The respective signal processing unit 17th in this respect defines a channel with a specified simulation delay VD . There are preferably several such channels and thus signal processing units 17th inside the control unit 16 provided, for example 4 or more, so that different simulation delays VD can be set, with each channel having a separate connector pin code and POUT may have. The activation of a respective channel (a respective signal processing unit 17th ) then takes place via the switching connection 42 .

With the individual delay circuits of the processing units 20th , 22nd , 25th it concerns circuit arrangements known per se with which the pulses can be delayed by a predetermined, adjustable delay time. These delay circuits are, for example, similar to the measuring block 18th constructed and have several series-connected delay modules Dn. The delay time is set in that a certain number of these delay modules Dn are used to select the total delay time.

Via the calibration unit 36 the delay is determined and checked d the individual delay modules Dn of the respective signal processing unit 17th . For this purpose, there is preferably one (only one) in the control unit 16 built-in ring oscillator, which is the calibration unit 36 educates or trains with. Several delay modules Dn are connected to form a ring for this ring oscillator. The natural frequency of the ring oscillator thus formed is measured. On the basis of this natural frequency (resonance frequency of the ring oscillator formed), the mean delay can be calculated in a simple manner d of the delay modules Dn used. Thus, the natural frequency initially leads to a total delay which, when divided by the number of modules Dn used, ultimately results in an averaged individual delay d of the blocks used Dn results. With the blocks Dn in the measuring block 18th as well as in the calibration unit 36 are structurally identical modules Dn. This is understood in particular to mean that these originate from at least the same production batch. Based on the determined (averaged) delay d will be on the delay d the one in the measuring block 18th used blocks Dn closed. Alternatively, the ones in the measuring block could also be used 18th used building blocks Dn can be used directly as components of the ring oscillator. However, this would be associated with disadvantages in the accuracy of the determination of the frequency of the ring oscillator and thus the determination of the delay of the delay modules Dn. It is specifically provided that the number of components used for the ring oscillator is greater (for example by a factor of at least 10 or at least 100 up to a factor of 1000) than the number for the measuring block 18th used delay modules Dn.

The thus determined value for the delay d is for example via the programming connection 28 the measuring block 18th announced to provide an accurate determination of the phase shift FT to enable.

In the 8th is only a single signal processing unit 17th shown. Several signal processing units are preferred 17th , in the control unit 16 included, each signal processing unit 17th As already mentioned, it has its own channel and different simulation delays for the different channels VD for the respective connections pin code and POUT are set.

The entire control unit is preferred 16 housed on an IC, in particular an FPGA.

The invention is not restricted to the exemplary embodiment described above. Rather, other variants of the invention can also be derived therefrom by the person skilled in the art without departing from the subject matter of the invention. In particular, all of the individual features described in connection with the exemplary embodiment can also be combined with one another in other ways without departing from the subject matter of the invention.

List of reference symbols

2

Measuring system

4th

Test system

6th

Channel

8th

recipient

10

Processing unit

12th

object

16

Control unit

17th

Signal processing unit

18th

Measuring block

20th

first processing block

22nd

second processing block

24

Compensation block

25th

third processing block

26th

Communication interface

27

Transponder

28

(Programming) connection

30th

Selective connection

32

Monitoring unit

34

Control connection

36

Calibration unit

38

Calibration connection

40

Configuration connector

42

Switching connection

44

Register connection

Tp

Cycle time measuring cycle, measuring cycle

T

Cycle time system clock, system clock

TD

Dead time

PW

Pulse width

pin code

Measuring cycle signal

PIN1, 2

Measuring pulse

POUT

Output pulse

D.

Delay Time

DL

Delay

especially

virtual distance

VD

Simulation delay (virtual delay), arithmetical

VD '

simulation delay to be set (taking into account TD )

VD ''

simulation delay to be set (taking into account TS )

a

Distance between measuring system and test system

s

Distance for the pulses between measuring system - test system (s = a)

TS

Pulse transit time for distance s = a

CLK

System clock signal

FT

Phase shift (to the next pulse of the system clock)

PFT

Fine pulse shift

X

Distance window (time delay)

d

Delay Delay module

SYNC

synchronized signal

Claims (16)

A method for testing a measuring system, in particular a measuring system for distance measurement, especially in automobiles, in which the measuring system has a measuring cycle and periodically emits a measuring pulse at a time with the measuring cycle, the measuring pulse being recorded by a test system which generates an output pulse and sends it to the Measuring system transmitted, whereby - The output pulse is delivered with a delay in relation to the measuring pulse, which is composed of a multiple of the measuring cycle plus a simulation delay that correlates to a simulated, predetermined running time of the measuring pulse. Procedure according to Claim 1 , in which the test system has a system clock with a clock signal and a phase shift of the measurement pulse in relation to the clock signal is determined, the phase shift being taken into account when determining the delay time. Method according to the preceding claim, in which, in order to determine the phase shift, the measuring pulse is applied to a measuring block with a plurality of individual delay modules, which each switch after a delay, the number of delay modules being determined between the measuring pulse and the clock signal have switched. Method according to the preceding claim, in which a respective delay module has a delay time in the range from 1/10 to 1/100 or up to 1/1000 of the system clock. Method according to one of Claims 2 to 4, in which the following steps are carried out a) determining the phase shift according to one of the Claims 2 until 4th , b) synchronizing the measuring pulse with the system clock c) shifting the measuring pulse by an integer multiple of the system clock d) further shifting the measuring pulse according to the determined phase shift. Method according to the preceding claim, in which in steps c) and / or d) there is a shift by the measuring cycle minus a distance window. Method according to one of the two preceding claims, in which the shift takes place additionally by the simulation delay - and in the case of a previous setting of a distance window a shift takes place plus by the distance window - the output pulse then being output. Method according to one of the preceding claims, in which the test system has a system clock with a clock signal and the output pulse is shifted by an integral multiple of the system clock in relation to the measurement pulse. Method according to one of the preceding claims, in which a signal propagation time between the measuring system and the test system is additionally taken into account for the calculation of the delay time. Method according to one of the preceding claims, in which the test system is physically spaced a distance from the measuring system and the simulation delay is selected such that the simulated transit time corresponds to a distance which is smaller than the physical distance between the measuring system and the test system. Method according to one of the preceding claims, in which the test system can be switched between normal operation and compensation operation, the delay time according to one of the preceding claims being determined only in compensation operation and only the simulation delay being set in normal operation. Method according to one of the preceding claims and according to Claim 3 , in which a delay time of the delay modules is determined individually for the test system used and for the determination the phase shift and / or the compensation and the setting of the simulation delay is taken into account. Method according to the preceding claim, in which the test system has a ring oscillator with delay modules and the delay of the delay modules is calculated on the basis of a natural frequency of the ring oscillator. Method according to one of the two preceding claims, in which the delay modules are the delay modules which are used to determine the phase shift or additional delay modules of the same construction. Method according to one of the preceding claims, in which the real measuring system is a LIDAR system and both the measuring pulse and the output pulse are optical signals. Test system for a method according to one of the preceding claims, with - a receiver for receiving a measuring pulse with a known measuring cycle of a measuring system, - with a transmitter for outputting an output pulse - With a control unit which determines a delay time between the reception of the measurement pulse and the transmission of the output pulse in such a way that the output pulse is delivered with a delay in relation to the measurement pulse, which is composed of a multiple of the measurement cycle plus a simulation delay that correlated to a simulated, predetermined transit time of the measurement pulse, the control unit also preferably being formed by an IC, in particular by an FPGA.

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