DE102021100529A1 - TSV STRUCTURE AND METHODS OF FORMING THEREOF - Google Patents

Abstract

A method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner over the first lining. The second liner extends into the opening. The method further includes filling a conductive material into the opening to form a via and forming conductive features on opposite sides of the semiconductor substrate. The conductive features are electrically connected to each other through the via.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

This application claims priority to U.S. Provisional Patent Application No. 63/081,502 , filed September 22, 2020, entitled "Novel TSV Structure," which is incorporated by reference into the present application.

BACKGROUND ART

Through-Silicon Vias (TSVs) are used as electrical paths in device dies so that the conductive features on opposite sides of the device dies can be connected together. The process of forming a TSV includes etching a semiconductor substrate to form an opening, filling the opening with a conductive material to form the TSV, performing a backside grinding process to remove a portion of the semiconductor substrate from the backside, and forming an electrical connection on the backside of the Semiconductor substrate for connecting to the TSV.

character list

• Die 1, 2, 3A, 3B, 3C, 3D, 3E, 3F, 3G, 4-13, 14A, 14B, 14C, 14D, 14E, 14F und 14G veranschaulichen die Querschnittsansichten von Zwischenstufen bei dem Bilden von Dies, die Durchkontaktierungen aufweisen, gemäß einigen Ausführungsformen.
• 15 veranschaulicht eine Draufsicht einer Durchkontaktierung gemäß einigen Ausführungsformen.
• 16 veranschaulicht eine dielektrische Auskleidung mit einem stufenweise verkleinerten unteren Abschnitt gemäß einigen Ausführungsformen.
• Die 17 bis 19 veranschaulichen die Querschnittsansichten von Zwischenstufen bei dem Packen eines Dies, der eine Durchkontaktierung aufweist, gemäß einigen Ausführungsformen.
• 20 veranschaulicht einen Prozessfluss zum Bilden eines Dies, der eine Mehrfachauskleidung aufweist, gemäß einigen Ausführungsformen.

Aspects of the present disclosure are best understood by considering the following detailed description when taken in connection with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily exaggerated or minimized for the sake of clarity of explanation.

• the 1 , 2 , 3A , 3B , 3C , 3D , 3E , 3F , 3G , 4-13 , 14A , 14B , 14C , 14D , 14E , 14F and 14G 12 illustrate the cross-sectional views of intermediate stages in the formation of dice having vias, according to some embodiments.
• 15 12 illustrates a top view of a via, according to some embodiments.
• 16 FIG. 12 illustrates a dielectric liner with a progressively reduced bottom portion, according to some embodiments.
• the 17 until 19 12 illustrate cross-sectional views of intermediate stages in packaging a die having a via, according to some embodiments.
• 20 12 illustrates a process flow for forming a die having a multi-liner, according to some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are of course examples only and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in face-to-face contact, and also include embodiments in which additional features are intermediate between the first and second Feature may be formed so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself imply a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially-related terms such as "underlying," "beneath," "lower," "overlying," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to another element(s). ) or feature(s) as illustrated in the figures. The spatial terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially related descriptors used herein may be interpreted equally accordingly.

A die having multilayer liners for vias and the method of forming it are provided according to some embodiments. The die has a plurality of liners, which are formed from different materials and may have different heights. For example, an outer liner can be formed of a dense material to act as a diffusion bar ture and thin to reduce parasitic capacitance. An inner liner may be thicker and have a lower k value than the outer liner. With the multilayer design, the liners of vias may have an improved ability to prevent diffusion while not adversely increasing the parasitic capacitance between the vias and other features such as the semiconductor substrate. The intermediate stages in forming the die are illustrated according to some embodiments. Some variations of some embodiments are discussed. The same reference numbers are used to refer to the same elements throughout the different views and illustrative embodiments.

the 1 , 2 , 3A , 3B , 3C , 3D , 3E , 3F , 3G , 4-13 , 14A , 14B , 14C , 14D , 14E , 14F and 14G 12 illustrate the cross-sectional views of intermediate stages in forming a die having vias, according to some embodiments of the present disclosure. The corresponding processes are also shown schematically in the process flow 200, as in 20 is shown.

1 12 illustrates a cross-sectional view of wafer 20. According to some embodiments of the present disclosure, wafer 20 is or includes a device wafer including active devices and possibly passive devices represented as IC packages 26. FIG. The wafer 20 may have a plurality of chips/dies 22 therein, with one of the chips 22 being illustrated. According to alternative embodiments of the present disclosure, wafer 20 is an interposer wafer that does not have active devices, and may or may not have passive devices.

According to some embodiments of the present disclosure, wafer 20 includes semiconductor substrate 24 and features formed on a top surface of semiconductor substrate 24 . The semiconductor substrate 24 may be or include crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, or a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or the like. Shallow trench isolation (STI) regions (not shown) may be formed in the semiconductor substrate 24 to isolate the active regions in the semiconductor substrate 24 .

According to some embodiments of the present disclosure, wafer 20 includes IC devices 26 formed on the top surface of semiconductor substrate 24 . IC devices 26 may include Complementary Metal-Oxide Semiconductor (CMOS) transistors, resistors, capacitors, diodes, and the like, according to some embodiments. The details of the IC devices 26 are not illustrated herein. According to alternative embodiments, wafer 20 is used to form interposers (which do not include active devices), and substrate 24 may be a semiconductor substrate or a dielectric substrate.

An inter-layer dielectric (ILD) 28 is formed over the semiconductor substrate 24 and fills the space between the gate stacks of the transistors (not shown) in the IC devices 26. According to some embodiments, the ILD 28 is made of phosphosilicate glass (PSG ), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG) or the like. The ILD 28 may be formed using spin coating, flowable chemical vapor deposition (FCVD), or the like. According to some embodiments of the present disclosure, the ILD 28 may also be formed using a deposition process such as plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or the like will.

Contact plugs 30 are formed in the ILD 28 and used to electrically connect the IC devices 26 to overlying metal lines and vias. In accordance with some embodiments of the present disclosure, the contact plugs 30 are formed from or include a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and/or multiple layers thereof. The formation of the contact plugs 30 may include forming contact openings in the ILD 28, filling a conductive material(s) into the contact openings, and performing a planarization process (such as a chemical mechanical polishing (CMP) process) to to bring the top surfaces of the contact plugs 30 to the same level as the top surface of the ILD 28.

Overlying ILD 28 and contact plugs 30 is interconnect structure 32. Interconnect structure 32 includes metal lines 34 and vias 36 embedded in dielectric layers 38 (also known as intermetal dielectric). rika (IMDs, Inter-Metal Dielectrics)) and etch stop layers 37 are formed. The metal lines on a same level are hereinafter collectively referred to as a metal layer. In accordance with some embodiments of the present disclosure, interconnect structure 32 includes a plurality of metal layers including metal lines 34 interconnected by vias 36 . The metal lines 34 and vias 36 may be formed from copper or copper alloys and may be formed from other metals as well. In accordance with some embodiments of the present disclosure, the dielectric layers 38 are formed from low-k dielectric materials. For example, the dielectric constants (k values) of the low-k dielectric materials may be less than about 3.0. The dielectric layers 38 may include a low-k carbonaceous dielectric material, hydrogen silsesquioxane (HSQ, Hydrogen SilsesQuioxane), methylsilsesquioxane (MSQ), or the like. In accordance with some embodiments of the present disclosure, the formation of the dielectric layers 38 includes depositing a porogen-containing dielectric material in the dielectric layers 38 and then performing an annealing process to drive off the porogen, and thus the remaining dielectric layers 38 are porous. The etch stop layers 37 may be formed of or include silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, or the like.

The formation of metal lines 34 and vias 36 in dielectric layers 38 may include single damascene processes and/or dual damascene processes. In a single damascene process to form a metal line or via, a trench or via opening is first formed in one of the dielectric layers 38 followed by filling the trench or via opening with a conductive material. A planarization process, such as a CMP process, is then performed to remove the excess portions of the conductive material that are higher than the top surface of the dielectric layer, leaving a metal line or via in the corresponding trench or via opening will. In a dual damascene process, both a trench and a via opening are formed in a dielectric layer, with the via opening underlying and connected to the trench. The conductive materials are then filled into the trench and the via opening to form a metal line and a via, respectively. The conductive materials may include a diffusion barrier layer and a copper-containing metallic material over the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

Metal lines 34 include upper conductive (metallic) features such as metal lines, metal pads, or vias (referred to as 34A) in a top dielectric layer (referred to as dielectric layer 38A), which is the top layer of dielectric layers 38 . In accordance with some embodiments, dielectric layer 38A is formed of a low-k dielectric material that is similar to the material of lower ones of dielectric layers 38 . The metal lines 34 in the top dielectric layer 38A may also be formed of copper or a copper alloy and may have a dual damascene structure or a single damascene structure.

According to some embodiments, the etch stop layer 40 is deposited on the top dielectric layer 38A and the top metal layer. Etch stop layer 40 may be formed of or includes silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, or the like.

A passivation layer 42 (sometimes referred to as passivation-1 or pass-1) is formed over etch stop layer 40 . In accordance with some embodiments, the passivation layer 42 is formed of a non-low-k dielectric material having a dielectric constant that is equal to or greater than about the dielectric constant of silicon oxide. The passivation layer 42 may be formed from or include an inorganic dielectric material, which may include a material selected from undoped silicate glass (USG), silicon nitride (SiN), silicon oxide (SiO ₂ ), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbide (SiC) or the like, combinations thereof and/or multiple layers thereof is selected and not limited thereto. According to some embodiments, the top surfaces of the top dielectric layer 38A and the metal lines 34 are at the same height. Accordingly, the passivation layer 42 can be a planar layer.

According to some embodiments, dielectric layer 44 is deposited over passivation layer 42 . The respective process is illustrated as process 202 in the process flow 200, as in 20 is shown. The dielectric layer 44 is formed from or includes a material different from that of the passivation layer 42 and may be SiC, SiN, SiON, SiOC or the like may be formed or has them.

With reference to 2 an etch mask 46 is formed and then patterned. According to some embodiments, the etch mask 46 comprises a photoresist and may or may not comprise a hard mask formed of TiN, BN, or the like. An anisotropic etch process is then performed to form an opening penetrating the dielectric layers including dielectric layer 44, passivation layer 42, etch stop layer 40, IMDs 38, etch stop layers 37, ILD 28, and so on. The semiconductor substrate 24 is further etched such that the opening 48 extends to an intermediate plane of the substrate 24, the intermediate plane being between the top surface 24A and the bottom surface of the semiconductor substrate 24. FIG. An opening 48 is thus formed. The respective process is illustrated as process 204 in the process flow 200, as in 20 is shown. The opening 48 is used to form a semiconductor via (TSV, sometimes referred to as a silicon via) and is thus referred to as a TSV opening 48 hereinafter. The anisotropic etching process includes a plurality of etching processes that use different etching gases to etch the dielectric layers formed of different materials and to etch the semiconductor substrate 24 .

According to some embodiments, the TSV opening 48 has a top width W ₁ and a bottom width W ₂ that is less than the top width W ₁ . The TSV opening 48 may have slanted and straight edges 48E, wherein the angle of inclination α of the straight edges 48E is less than 90 degrees, for example in the range of between about 80 degrees and about 90 degrees. The aspect ratio H1/W1 of opening 48 may range from between about 2 and about 10 according to some embodiments. Etch mask 46 is removed after forming TSV opening 48, for example by an ashing process.

With reference to 3A a first liner 50 is deposited. The respective process is illustrated as process 206 in the process flow 200, as shown in FIG 20 is shown. The liner 50 has horizontal sections outside of the TSV opening 48 and vertical sections that extend into the TSV opening 48 . According to some embodiments, the liner 50 is formed from or includes a dielectric material such as silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, or the like, or combinations thereof. According to alternative embodiments, the liner 50 is formed from or includes a conductive material, such as Ti, TiN, Ta, TaN, or the like, or combinations thereof. The thickness T1 of the liner 50 is small so that the liner 50, which may have a high k value, does not cause the disadvantageous amplification of the parasitic capacitance of parasitic capacitors. For example, the thickness T1 of the liner 50 can range from between about 2 Å and about 500 Å, where the thickness T1 can be measured at an intermediate height of the vertical sections. The deposition process may include plasma enhanced chemical vapor deposition (PECVD), final atomic layer deposition (ALD), physical vapor deposition (PVD), or the like. The precursors for forming the liner 50 may include a siliceous precursor such as SiCl ₄ , SiH ₂ Cl ₂ , Si ₂ Cl ₆ , Si ₃ Cl ₈ or the like and a nitrogenous precursor such as NH ₃ , for example when SiN is to be formed. According to some embodiments, the liner 50 has a good ability to prevent diffusion and can prevent unwanted substances from penetrating therethrough.

According to some embodiments, the process conditions of depositing the liner 50 are adjusted such that the liner 50 is a non-conformal layer and the liner 50 covers the sidewalls of an upper portion of the TSV opening 48 while the sidewalls of the lower portion of the TSV opening 48 are not be covered. In accordance with some embodiments, PECVD is used and some process conditions are adjusted to achieve the desired profile for the liner 50 . The adjusted process conditions may include the pressure of the process gas, a Si/N gas flow ratio, etc., where the Si/N gas flow ratio is the ratio of the flow rate of silicon-containing gas to the flow rate of nitrogen-containing gas. For example, increasing the pressure of the process gas may cause the liner 50 to extend less far to the bottom of the TSV orifice 48 (so that the height H2 is reduced), while decreasing the pressure may cause the liner 50 further extends to the bottom of the TSV opening 48. Increasing the Si/N gas flow ratio may cause the liner 50 to extend less far to the bottom of the TSV opening 48, while decreasing the Si/N gas flow ratio may cause the liner 50 to extend further to the bottom of the TSV opening 48 extends. By selecting appropriate process conditions including the appropriate combination of pressure and Si/N gas flow ratio, the bottom of the liner 50 can be at a desired height. As in 3A is shown is to For example, the bottom 20bot is at a level that is at the same level as (or substantially at the same level as) the top surface 24T of the semiconductor substrate 24, for example with a height difference of less than about 100 nm.

3B 12 illustrates the formation of the liner 50 according to alternative embodiments in which the bottom surfaces 50bot of the liner are higher than the top surface 24T of the semiconductor substrate 24. FIG. For example, the sidewalls of the top layers of the dielectric layers 38 may be covered by the liner 50 while the sidewalls of some bottom layers of the dielectric layers 38 are not covered by the liner 50 . These embodiments may be applied when the bottom layers of dielectric layers 38 have higher k values than the top layers of dielectric layers 38, thereby forming the liner 50 such that the sidewalls of the lower k dielectric layers 38 (e.g., k values less than 3.8, or less than about 3.5 or about 3.0), while the sidewalls of dielectric layers 38 having higher k values (e.g., greater than about 3.5 or 3 ,8) are not protected. It is recognized that parasitic capacitors can be formed between the resulting TSV and surrounding conductive or semiconductor materials, and the parasitic capacitance between the TSV and the semiconductor substrate 24 contributes greatly to the parasitic capacitance. Accordingly, when the liner 50 (which has the higher k value than the subsequently formed liner 52 ( 4 ) has) does not extend into the semiconductor substrate 24, as in FIGS 3A and 3B is shown, the parasitic capacitance can be reduced.

3C 12 illustrates the formation of the liner 50 in accordance with still further alternative embodiments in which the bottom surfaces 50bot of the liner 50 are lower than the top surface 24T of the semiconductor substrate 24 and higher than the bottom surface of the TSV opening 48. FIG. The formation of the liner 50 in 3C can be achieved by selecting appropriate process conditions, as discussed previously.

3D 12 illustrates the formation of the liner 50 according to still further alternative embodiments, wherein the liner 50 covers all surfaces exposed to the TSV opening 48, including the bottom surface of the TSV opening 48. According to some embodiments, the liner 50 in 3D can be formed using PECVD and can be achieved by selecting appropriate process conditions as discussed previously. According to alternative embodiments, the liner 50 may be formed using a conformal deposition process such as ALD, CVD, or the like. The resulting liner 50 can thus be conformal, for example with the horizontal sections and the vertical sections having a thickness variation that is less than about 20 percent or about 10 percent.

As in the 3A , 3B , 3C and 3D As shown, the liners 50 may be single layer dielectric liners or composite liners such as dual layer liners. the 3A , 3B , 3C and 3D 12 illustrate exemplary bilayer liners 50 that include dielectric liners (partial liners) 50A and 50B. It is noted that the liners 50 in the 3A , 3B , 3C and 3D can also be single-layer linings. Accordingly, the lines separating liners 50A and 50B are shown in phantom to indicate that these lines may or may not be present. According to some embodiments, the liners 50A and 50B are formed from different materials or the same material having different compositions. For example, the dielectric liner may be formed of both silicon nitride and silicon oxynitride, however, the atomic nitrogen percentage of liner 50A may be greater than or less than the atomic nitrogen percentage in liner 50B. The liners 50A and 50B may be formed in separate processes, which may (or may not) be formed in a same process chamber, and may (or may not) be formed in-situ with no vacuum break therebetween. Although not detailed in the 3A , 3B , 3C and 3D Accordingly, liners 50A and 50B may extend to different depths as shown in FIGS 3E , 3F and 3G according to some example embodiments.

the 3E , 3F and 3G illustrate some details of the bilayer liners 50 as in Figs 3A , 3B , 3C and 3D according to some embodiments. It should be appreciated that the illustrated lower levels of liners 50A and 50B are examples and the bottom of each of liners 50A and 50B may be at any level between the top and bottom of TSV opening 48 in any combination. For example, the bottom of each of the liners 50A and 50B can be at any level, as shown in FIGS 3A , 3B , 3C and 3D shown. 3E illustrates an execution shape in which liner 50B extends deeper into TSV opening 48 than liner 50A. 3F 14 illustrates an embodiment in which liner 50B extends into TSV opening 48 to the same depth as liner 50A. 3G 12 illustrates an embodiment in which liner 50B extends into TSV opening 48 less than liner 50A.

In the embodiments as in the 3A-3G As shown, the process variation may cause different portions of the liners 50 to extend to the same depth or to different depths since the liners 50 (and sub-layers 50A and 50B) are deposited at different depths. For example, in each of the 3A-3G the portion of the liners 50 to the left of the openings 48 extend to the same depth, a greater depth, or a lesser depth than the portion of the liners 50 to the right of the openings 48. Additionally, the lower end portions of the liners 50 may have gradually reduced thicknesses (rather than a uniform thickness). For example illustrated 16 a lower portion of the liner 50 with the gradually reduced thickness. Further illustrated 16 that the different portions of the dielectric liner 50 may extend to different depths of the TSV opening 48 . The depth difference ΔH may be greater than about 100 nm, according to some embodiments.

With reference to 4 a second liner 52 is deposited on the first liner 50 . The respective process is illustrated as process 208 in the process flow 200, as in 20 is shown. According to some embodiments, the dielectric liner 52 is formed of a material different from the material(s) of the liner 50 . For example, the dielectric liner 52 may be formed from or includes a dielectric material such as silicon oxide, silicon oxynitride, or the like. Accordingly, liner 52 is alternatively referred to as dielectric liner 52 . The dielectric liner 52 is deposited as a conformal layer such that the horizontal portions and the vertical portions of the dielectric liner 52 have thicknesses that are close together, for example with a variation that is less than about 20 percent or 10 percent. The deposition process may include Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or the like. The thickness T2 of the dielectric liner 52 may range from between about 500 Å and about 2500 Å. The liners 50 and 52 are also referred to collectively as a multi-layer liner. A ratio T1:T2 may range between about 0.001:1 and about 0.5:1, according to some embodiments.

The liners 50 and 52 may have different densities. According to some embodiments, dielectric liner 50 is denser than liner 52. For example, liner 50 may have a density DS50 ranging from between about 3 g/cm ³ and about 10 g/cm ³ . The dielectric liner 52 may have a density DS52 ranging from between about 2.5 g/cm3 and about 4 g/cm3. The density difference (DS52 - DS50) can be greater than about 0.5 g/cm3 and can range from between about 0.5 g/cm3 and about ⁷ g/cm3.

5 illustrates depositing metal seed layer 54. The respective process is illustrated as process 210 in process flow 200, as shown in FIG 20 is shown. According to some embodiments, the metal seed layer 54 is formed by physical vapor deposition (PVD). The metal seed layer 54 may be a single layer formed of copper, for example, or may have a plurality of layers including, for example, a conductive barrier layer and a copper layer on the conductive barrier layer. The conductive barrier layer may be formed of or include TiN, Ti, TaN, Ta, or the like.

6 12 illustrates the deposition of conductive material 56, which may be a metallic material such as copper or a copper alloy. The respective process is illustrated as process 212 in the process flow 200, as shown in FIG 20 is shown. The deposition process can be performed using electrochemical plating (ECP), electroless plating, or the like. The plating is performed until the top surface of the plated conductive material 56 is higher than the top surface of the liner 50 or 52. FIG.

7 FIG. 12 illustrates a planarization process, which may be a CMP process or a mechanical grinding process, performed to planarize the top surface of conductive material 56. FIG. The respective process is illustrated as process 214 in the process flow 200, as shown in FIG 20 is shown. According to some embodiments, the planarization process is performed using the dielectric layer 42 as a stop layer, as shown in FIG 7 is illustrated. According to alternative Ausführungsfor In this case, the planarization process is performed using other dielectric layers, such as dielectric layer 44 ( 6 ), performed as a CMP stop layer. Accordingly, the top surface of the remaining conductive material 56 will be coplanar with the top surface of the dielectric layer 44 . The remaining portions of metal seed layer 54 and conductive material 56 are collectively referred to as via 61 hereinafter.

the 7 until 13 12 illustrate formation of top features according to some embodiments. It should be noted that these processes are examples and any other connection scheme is contemplated by the present disclosure. Continue with reference to 7 For example, via 58 is formed to further connect to top metal line/pad 34 . The respective process is illustrated as process 216 in the process flow 200, as shown in FIG 20 is shown. According to some embodiments, via 58 is formed by a single damascene process. The formation process may include the etch passivation layer 42 and underlying etch stop layer 37 forming an opening, and depositing a conductive barrier (e.g., formed of titanium, titanium nitride, tantalum, tantalum nitride, or the like) and plating a conductive material, such as copper, tungsten or the like. A CMP process may then be performed to remove excess material, leaving via 58 behind.

With reference to 8th an isolation dielectric layer 60 is deposited according to some embodiments. The respective process is illustrated as process 218 in the process flow 200, as shown in FIG 20 is shown. The material of the insulating layer 60 may be selected from the same group of candidate materials for forming the liner 50 and may be the same as or different from the liner 50 material. For example, if the liner 50 is formed of silicon nitride, the insulating layer 60 may be formed of silicon nitride or silicon carbide.

With reference to 9 the insulating layer 60 is etched and metal pads 62 are formed over the passivation layer 42 . The respective process is illustrated as process 220 in the process flow 200, as shown in FIG 20 is shown. The metal pads 62 can be aluminum pads or aluminum-copper pads, and other metallic materials can be used. The formation process may include depositing a metal layer and then patterning the metal layer to leave the metal pads 62 behind. The metal pads 62 may also have some portions that extend directly over the isolation layer 60 according to some embodiments. Then the passivation layer 64 (sometimes referred to as passivation-2) is formed. The respective process is illustrated as process 222 in the process flow 200, as shown in FIG 20 is shown. The passivation layer 64 can be a single layer or a compound layer and can be formed of a non-porous material such as silicon oxide, silicon nitride, USG, silicon oxynitride, or the like.

Next, the passivation layer 64 is patterned such that some portions of the passivation layer 64 cover the edge portions of the metal pads 62 and some portions of the metal pads 62 are exposed through the openings in the passivation layer 64 . Then the polymer layer 66 is formed, for example by spreading the polymer layer 66 in a flowable form and then curing the polymer layer 66. The polymer layer 66 is patterned to expose the metal pads 62. FIG. The respective process is also illustrated as process 222 in the process flow 200, as in 20 is shown. The polymer layer 66 may be formed from polyimide, polybenzoxazole (PBO), or the like.

Then, under-bump metallizations (UBMs) 68 and conductive regions 70 are formed to electrically connect to the underlying metal pads 62, as shown in FIG 10 is shown. The respective process is illustrated as process 224 in the process flow 200, as shown in FIG 20 is shown. The processes of forming the UBMs 68 and the conductive regions 70 may include depositing a cap metal seed layer that extends into the openings in the passivation layer 64 and the polymer layer 66, forming a patterned plating mask on the metal seed layer, plating the conductive regions 70, removing the plating mask and etching the portions of the cap metal seed layer previously covered by the plating mask. The remaining portions of the cap metal seed layer are referred to as UBMs 68 . The metal seed layer may include a titanium layer and a copper layer over the titanium layer. The conductive regions 70 may include copper, nickel, palladium, aluminum, gold, alloys thereof, and/or multiple layers thereof. Each of the conductive regions 70 may include a copper region, which may or may not be covered with a solder region, which may be formed of SnAg or similar materials. According to some embodiments, the conductive regions 70 protrude higher than the top surface of the top dielectric layer in the wafer 20 and can be used for solder bonding, direct metal-to-metal bonding, or the same can be used. According to alternative embodiments, the dielectric layer 71 is formed to have a top surface that is coplanar with the top surfaces of the conductive regions 70 and can be used for hybrid bonding.

the 11 until 13 12 illustrate the process for forming features on the backside of the semiconductor substrate 24. The respective process is illustrated as process 226 in the process flow 200 as shown in FIG 20 is shown. With reference to 11 a back grinding process is performed to remove a portion of the substrate 24 until the TSV 61 is exposed. Next, the semiconductor substrate 24 is slightly recessed (e.g., by etching) so that the TSV 61 protrudes from the back surface of the semiconductor substrate 24, as shown in FIG 12 is shown.

As in 12 1, the dielectric layer 72 is deposited next, followed by a CMP process or a mechanical grinding process to expose the TSV 61 again. The TSV 61 thus penetrates the dielectric layer 72. According to some embodiments, the dielectric layer 72 is formed of silicon oxide, silicon nitride, or the like. With reference to 13 an RDL 74 having a pad portion touching the TSV 61 is formed. The RDL 74 may be formed from aluminum, copper, nickel, titanium, or the like according to some embodiments.

14A 12 illustrates the formation of dielectric layer 76 and electrical connector 78. According to some embodiments, electrical connector 78 includes a solder region, which may be formed by plating a solder ball on the pad of RDL 74 and reflowing the solder ball. According to alternative embodiments, the electrical connector 78 is formed from non-reflowable (non-solder) metallic materials. For example, the electrical connector 78 may be formed as a copper pad or pillar and may or may not have a nickel cap layer. Electrical connection 78 may protrude from the surrounding dielectric layer and may be used for solder bonding or direct metal-to-metal bonding. Alternatively, the bottom surface of electrical connector 78 can be coplanar with the bottom surface of dielectric layer 76 so that device 22 can be used for hybrid bonding. The dielectric layer 71, which is located on the front side of the wafer 20, is also in 14A shown using dashed lines to indicate that it may or may not be formed. Although not in the 14B , 14C , 14D , 14E , 14F and 14G As shown, the dielectric layer 71 may also be formed in the structures illustrated in those figures. According to some embodiments, the wafer 20 is singulated by a sawing process, for example by cutting through scribe lines 80.

the 14B , 14C , 14D , 14E , 14F and 14G illustrate the structures formed based on the structure shown in FIGS 3B , 3C , 3D , 3E , 3F and 3G is shown. It is noted that the details of the processes and materials used to form the structures used in the 14B , 14C , 14D , 14E , 14F and 14G are shown, respectively on the explanation of 3B , 3C , 3D , 3E , 3F and 3G and the explanation of 4 until 13 relate. In each of the 14A , 14B , 14C and 14D Dashed lines are drawn at the liners 50 indicating that the liners 50 may be single layer liners or may be dual layer liners including partial liners 50A and 50B. Also, the bottoms of the liners 50A may be lower than, level with, or higher than the bottoms of the respective liners 50B. In 14A For example, the liner 50 has a bottom end 50bot that is at the same level as the top surface 24T of the semiconductor substrate 24. FIG. When the dielectric liner 50 has two sub-liners 50A and 50B, one of the sub-liners 50A and 50B has the lower end 50bot at the same level as the top surface 24T, while the other has the lower end 50bot higher than, lower than, or at the same level as the top surface 24T of the semiconductor substrate 24 may lie. 14B 12 illustrates that the lower end 50bot of the liner 50 (or at least one of the partial liners 50A and 50B) is higher than the top surface 24T. 14C 12 illustrates that the lower end of the liner 50 (or at least one of the partial liners 50A and 50B) is lower than the top surface 24T. 14D 12 illustrates that the lower end of liner 50 (and partial liners 50A and 50B) extends to the lower surface of semiconductor substrate 24. FIG. 14E 12 illustrates that partial liner 50A has a bottom surface that is higher than the bottom surface of partial liner 50B. 14F 12 illustrates that partial liner 50A extends at the same level as partial liner 50B. 14G 12 illustrates that partial liner 50A extends lower than partial liner 50B.

In the examples discussed above, the top of the TSV 61 is at the same level as the top surface of the passivation layer 42. According to alternative embodiments, the top end of the TSV 61 at any other level (if possible) that is lower than the top surface of the passivation layer 42. For example, the top surface of TSV 61 may be coplanar with the top surface of the top metal layer in interconnect structure 32, with the top surface of any other dielectric layer in interconnect structure 32, coplanar with the top surface of ILD 28, or coplanar with the top surface of the substrate 24.

15 12 illustrates a top view of TSV 61. According to some embodiments, each of liners 50A and 50B and dielectric liner 52 forms an annulus, which may have a circular shape, a polygon shape (such as a hexagon shape or an octagon shape), or the like. The metal seed layer 54 (if it comprises a material different than that of the conductive material 56) may be distinguishable.

16 12 illustrates the TSV 61 and the liners 50 and 52 according to some embodiments. The lower ends of liner 50 (and sub-layers 50A and 50B) may have gradually reduced thicknesses, with upper portions being thicker than respective lower portions. As previously mentioned, different portions of the liners 50 may extend to different levels. Also, some portions 50' of the liner 50 may or may not be separated from the top portion of the liner 50 to form discrete islands.

the 17 until 19 illustrate the intermediate stages in building the package 81 ( 19 ) which the device 22 has therein. It is understood that the device 22 is illustrated schematically and it is understood that the details (such as the liners of the TSVs) of the device 22 refer to the disclosure above. With reference to 17 device 22 is bonded to device 82. The bonding may be performed by hybrid bonding, where the dielectric layer 71 and the electrical connection (conductive region) 70 are bonded to the surface dielectric layer 84 and the bond pad 86 of the device 82, respectively. Device 82 may be a device die, package substrate, interposer, package, or the like.

18 12 illustrates the structure after the backside grinding process is performed on the semiconductor substrate 24 and after the semiconductor substrate 24 is recessed by etching. Accordingly, the TSV 61 projects higher than the back surface of the semiconductor substrate 24 . As in 19 1, dielectric layer 72 is deposited next, followed by a planarization process to level the top surfaces of dielectric layer 72 and TSV 61. FIG. A gap fill region 90 is then formed, which may be formed from or include a molding compound, silicon nitride, silicon oxide, or the like, or combinations thereof. The interconnect structure 92 having the electrical terminal 78 is then formed over the device 22 and the column fill region 90. FIG. Interconnect structure 92 is electrically connected to device 82 through TSV 61 .

The embodiments of the present disclosure have some advantageous features. By forming more than one dielectric liner for the vias, the electrical performance of the respective device is more stable. The liner(s) can be formed selectively on the sidewall of some parts (such as the parts that are not present in the semiconductor substrate) of the TSVs, so that the parasitic capacitance can be reduced.

According to some embodiments of the present disclosure, a method includes forming a plurality of dielectric layers over a semiconductor substrate; etching the plurality of dielectric layers and the semiconductor substrate to form an opening; depositing a first liner extending into the opening; depositing a second liner over the first liner, the second liner extending into the opening; filling a conductive material into the opening to form a via; and forming conductive features on opposite sides of the semiconductor substrate, the conductive features being electrically connected to one another through the via. In one embodiment, depositing the first liner is performed using a non-conformal deposition process. In one embodiment, depositing the second liner is performed using a conformal deposition process. In one embodiment, the first liner is deposited such that it has a first bottom that is higher than a second bottom of the opening. In one embodiment, the first bottom is at the same level as a top surface of the semiconductor substrate. In an embodiment, the first bottom is higher than a top surface of the semiconductor substrate. In an embodiment, the first bottom is lower than a top surface of the semiconductor substrate. In one embodiment, depositing the first liner includes depositing a conductive liner and depositing the second liner includes depositing a dielectric liner. In one embodiment, depositing the first liner includes depositing silicon nitride and depositing the second liner includes depositing silicon oxide. In one embodiment, depositing the first liner includes depositing silicon carbide and depositing the second liner includes depositing silicon oxide.

According to some embodiments of the present disclosure, a structure includes a semiconductor substrate; a plurality of dielectric layers over the semiconductor substrate; a first conductive feature over the plurality of dielectric layers; a second conductive feature underlying the semiconductor substrate; a via penetrating the semiconductor substrate and the plurality of dielectric layers, the via electrically connecting the first conductive feature and the second conductive feature; a first liner encircling the via; and a second liner encircling the first liner, the second liner having a higher density than the first liner. In one embodiment, the first liner is in physical contact with a top portion of the via and the second liner is in physical contact with a bottom portion of the via. In one embodiment, a lower end of the second liner is at the same level as a top surface of the semiconductor substrate. In an embodiment, a lower end of the second liner is higher than a top surface of the semiconductor substrate. In one embodiment, a bottom end of the second liner is lower than a top surface of the semiconductor substrate. In one embodiment, the first liner comprises silicon oxide and the second liner comprises silicon nitride. In one embodiment, the second liner includes a first sub-layer and a second sub-layer encircling the first sub-layer, the bottoms of the first sub-layer and the second sub-layer being at different elevations.

According to some embodiments of the present disclosure, a structure includes a die. The die includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; a via penetrating the semiconductor substrate and the plurality of low-k dielectric layers; a first liner encircling the via, the first liner extending to both a top end and a bottom end of the via; a second liner encircling the first liner, the second liner being shorter than the via; a first electrical connection over the semiconductor substrate and on a top surface of the die; and a second electrical connection underlying the semiconductor substrate and on a bottom surface of the die, the first electrical connection and the second electrical connection being electrically connected to each other through the via. In one embodiment, the second liner is more dense than the first liner. In one embodiment, the second liner is thinner than the first liner.

The foregoing explains features of various embodiments so that those skilled in the art may better understand aspects of the present disclosure. One skilled in the art should recognize that the present disclosure can readily be used as a basis for designing or modifying other processes and structures to achieve the same purposes and/or obtain the same advantages of the embodiments presented herein. Also, one skilled in the art should realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US63/081502 [0001]

Claims (20)

Method comprising: forming a plurality of dielectric layers over a semiconductor substrate; etching the plurality of dielectric layers and the semiconductor substrate to form an opening; depositing a first liner extending into the opening; depositing a second liner over the first liner, the second liner extending into the opening; filling a conductive material into the opening to form a via; and forming conductive features on opposite sides of the semiconductor substrate, the conductive features being electrically connected to one another through the via. procedure after claim 1 wherein the deposition of the first liner is performed using a non-conformal deposition process. procedure after claim 2 wherein the deposition of the second liner is performed using a conformal deposition process. A method according to any preceding claim, wherein a bottom of the first liner is higher than a bottom of the opening. procedure after claim 4 , wherein the bottom of the first liner is at the same level as a top surface of the semiconductor substrate. procedure after claim 4 , wherein the bottom of the first liner is higher than a top surface of the semiconductor substrate. procedure after claim 4 , wherein the bottom of the first liner is lower than a top surface of the semiconductor substrate. Procedure according to any of the previous ones Claims 1 until 7 , wherein depositing the first liner comprises depositing a conductive liner and depositing the second liner comprises depositing a dielectric liner. Procedure according to any of the previous ones Claims 1 until 7 , wherein depositing the first liner comprises depositing silicon nitride and depositing the second liner comprises depositing silicon oxide. Procedure according to any of the previous ones Claims 1 until 7 , wherein depositing the first liner comprises depositing silicon carbide and depositing the second liner comprises depositing silicon oxide. Structure that has: a semiconductor substrate; a plurality of dielectric layers over the semiconductor substrate; a first conductive feature over the plurality of dielectric layers; a second conductive feature underlying the semiconductor substrate; a via penetrating the semiconductor substrate and the plurality of dielectric layers, the via electrically connecting the first conductive feature and the second conductive feature; a first liner encircling the via; and a second liner encircling the first liner, the second liner having a higher density than the first liner. structure after claim 11 wherein the first liner is in physical contact with a top portion of the via and the second liner is in physical contact with a bottom portion of the via. structure after claim 12 , wherein a lower end of the second liner is at the same level as a top surface of the semiconductor substrate. structure after claim 12 , wherein a lower end of the second liner is higher than a top surface of the semiconductor substrate. structure after claim 12 , wherein a lower end of the second liner is lower than a top surface of the semiconductor substrate. Structure according to any of the previous ones Claims 11 until 15 , wherein the first liner comprises silicon oxide and the second liner comprises silicon nitride. Structure according to any of the previous ones Claims 11 until 16 wherein the second liner comprises a first sub-layer and a second sub-layer encircling the first sub-layer, and wherein the lower ends of the first sub-layer and the second sub-layer are at different elevations. A structure comprising: a die comprising: a semiconductor substrate; a multitude of low-k dielectric layers across the semiconductor substrate; a via penetrating the semiconductor substrate and the plurality of low dielectric layers; a first liner encircling the via, the first liner extending to both a top end and a bottom end of the via; a second liner encircling the first liner, the second liner being shorter than the via; a first electrical connection over the semiconductor substrate and on a top surface of the die; and a second electrical connection underlying the semiconductor substrate and on a bottom surface of the die, wherein the first electrical connection and the second electrical connection are electrically connected to each other through the via. structure after Claim 18 , the second liner being more dense than the first liner. structure after Claim 18 , wherein the second liner is thinner than the first liner.

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