KR102540536B1 - Tsv structure and method forming same - Google Patents

Abstract

The method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and a second liner over the first liner. It includes the step of depositing. A second liner extends into the opening. The method further includes filling a conductive material into the opening to form a through via, and forming conductive features on both sides of the semiconductor substrate. The conductive features are electrically interconnected through through vias.

Description

TSV structure and method of forming the same {TSV STRUCTURE AND METHOD FORMING SAME}

[Priority claim and cross-reference]

This application claims the benefit of US Provisional Application No. 63/081,502, filed on September 22, 2020, entitled "Novel TSV Structure", which is incorporated herein by reference.

Through-Silicon Vias (TSVs) are used as electrical pathways within the device die so that conductive features on both sides of the device die can be interconnected. The process for forming a TSV includes etching the semiconductor substrate to form an opening, filling the opening with a conductive material to form a TSV, performing a backside grinding process to remove a portion of the semiconductor substrate from the backside, and forming electrical connectors on the backside of the semiconductor substrate to connect to the TSVs.

Aspects of the present disclosure are best understood by reading the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. Indeed, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.
1, 2, 3a, 3b, 3c, 3d, 3e, 3f, 3g, 4 to 13, 14a, 14b, 14c, 14d, 14e, 14f , and FIG. 14G shows a cross-sectional view of an intermediate stage in the formation of a die including through vias in accordance with some embodiments.
15 shows a top view of a through via in accordance with some embodiments.
16 shows a dielectric liner with a progressively decreasing lower portion in accordance with some embodiments.
17-19 show cross-sectional views of intermediate stages in packaging a die including through vias in accordance with some embodiments.
20 shows a process flow for forming a die including multiple through-liner vias in accordance with some embodiments.

The following disclosure provides several different embodiments or examples for implementing different features of the present invention. To simplify the present disclosure, specific examples of components and arrangements are described below. These are of course only examples and are not intended to be limiting. For example, formation of a first feature on or on a second feature in the following description may include an embodiment in which the first feature and the second feature are formed in direct contact, and the first feature An embodiment in which an additional feature may be formed between the first feature and the second feature may also be included so that the first feature and the second feature do not directly contact each other. In addition, the present disclosure may repeat reference numbers and/or letters in various examples. This repetition is for the purpose of simplicity and clarity, and such repetition itself does not in itself affect the relationship between the various embodiments and/or configurations discussed.

Also, "underlying", "below", "lower", "overlying", and "above" etc. are used to describe the relationship of one element or feature to another element or feature as shown in the figures. The same spatially relative terminology may be used herein for ease of explanation. Spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientations shown in the figures. The device may be otherwise oriented (rotated 90 degrees or rotated to other orientations) and the spatially relative descriptors used herein may likewise be interpreted appropriately.

According to some embodiments, a die including a multilayer liner for a through via and a method of forming the same are provided. The die includes a plurality of liners formed of different materials and which may have different heights. For example, the outer liner can be formed of a dense material to act as a diffusion barrier, and can be thin to reduce parasitic capacitance. The inner liner may be thicker and may have a lower k value than the outer liner. Using a multilayer design, the liner of a through-via may have an improved ability to prevent diffusion without detrimentally increasing the parasitic capacitance between the through-via and other features, such as a semiconductor substrate. An intermediate step in the formation of a die is illustrated according to some embodiments. Several variations of some embodiments are discussed. Like reference numbers are used throughout the various drawings and illustrative embodiments to indicate like elements.

1, 2, 3a, 3b, 3c, 3d, 3e, 3f, 3g, 4 to 13, 14a, 14b, 14c, 14d, 14e, 14f , and FIG. 14G shows a cross-sectional view of an intermediate stage in the formation of a die including through vias in accordance with some embodiments of the present disclosure. The corresponding process is also schematically reflected in the process flow 200 shown in FIG. 20 .

1 shows a cross-sectional view of a wafer 20 . In accordance with some embodiments of the present disclosure, wafer 20 is or may include a device wafer that includes active devices and possibly passive devices, which is denoted as integrated circuit device 26 . Wafer 20 may include a plurality of chips/dies 22 within the wafer, one of chips 22 being shown. According to an alternative embodiment of the present disclosure, wafer 20 is an interposer wafer without active devices and may or may not include passive devices.

In accordance with some embodiments of the present disclosure, wafer 20 includes a semiconductor substrate 24 and features formed on a top surface of semiconductor substrate 24 . The semiconductor substrate 24 may be formed of or include a group III-V compound semiconductor such as crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or the like. A shallow trench isolation (STI) region (not shown) may be formed in the semiconductor substrate 24 to isolate an active region in the semiconductor substrate 24 .

In accordance with some embodiments of the present disclosure, wafer 20 includes an integrated circuit device 26 formed on a top surface of a semiconductor substrate 24 . Integrated circuit device 26 may include complementary metal-oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, and the like, according to some embodiments. Details of the integrated circuit device 26 are not illustrated herein. According to an alternative embodiment, wafer 20 is used to form an interposer (without active device) and substrate 24 may be a semiconductor substrate or a dielectric substrate.

An interlayer dielectric (ILD) 28 is formed over the semiconductor substrate 24 and fills the space between the gate stacks of transistors (not shown) in the integrated circuit device 26 . According to some embodiments, the ILD 28 is silicon oxide, Phospho Silicate Glass (PSG), Boro Silicate Glass (BSG), Boron-doped Phospho Silicate Glass (BPSG). Glass) or fluorine-doped silicate glass (FSG, Fluorine-doped Silicate Glass). The ILD 28 may be formed using spin coating or flowable chemical vapor deposition (FCVD) or the like. According to some embodiments of the present disclosure, ILD 28 may also be formed using a deposition method such as Plasma Enhanced Chemical Vapor Deposition (PECVD) or Low Pressure Chemical Vapor Deposition (LPCVD). can be formed

A contact plug 30 is formed in the ILD 28 and is used to electrically connect the integrated circuit device 26 to the metal lines and vias overlying it. According to some embodiments of the present disclosure, contact plug 30 is formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum, nitride, alloys thereof, and/or multiple layers thereof. is or contains Formation of the contact plug 30 involves forming a contact opening in the ILD 28, filling the contact opening with a conductive material, and making the top surface of the contact plug 30 flush with the top surface of the ILD 28. It may include performing a planarization process (such as a chemical mechanical polish (CMP) process or a mechanical grinding process) to achieve

Over the ILD 28 and contact plug 30 is an interconnection structure 32 . Interconnect structure 32 includes metal lines 34 and vias 36 formed in dielectric layer 38 (also referred to as Inter-metal Dielectric (IMD)) and etch stop layer 37. do. Metal lines at the same level are hereinafter collectively referred to as metal layers. In accordance with some embodiments of the present disclosure, interconnect structure 32 includes a plurality of metal layers including metal lines 34 interconnected through vias 36 . The metal lines 34 and vias 36 may be formed of copper or a copper alloy, or may be formed of other metals. In accordance with some embodiments of the present disclosure, dielectric layer 38 is formed of a low-k dielectric material. The dielectric constant (k value) of the low-k dielectric material may be lower than about 3.0, for example. Dielectric layer 38 may include a carbon-containing low-k dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), or the like. In accordance with some embodiments of the present disclosure, forming dielectric layer 38 includes depositing a porogen-containing dielectric material in dielectric layer 38 and then performing a curing process to expel the porogen; Thus, the remaining dielectric layer 38 is porous. The etch stop layer 37 may be formed of or include silicon nitride, silicon carbide, silicon oxycarbide, or silicon oxynitride.

The formation of metal lines 34 and vias 36 in dielectric layer 38 may include a single damascene process and/or a dual damascene process. In a single damascene process for forming a metal line or via, a trench or via opening is first formed in one of the dielectric layers 38, followed by filling the trench or via opening with a conductive material. A planarization process, such as a CMP process, is then performed to remove excess portions of the conductive material higher than the top surface of the dielectric layer, leaving metal lines or vias in the corresponding trench or via openings. In a dual damascene process, both trenches and via openings are formed in the dielectric layer, and the via openings lie beneath and connect to the trenches. A conductive material is then filled into the trench and via openings to form metal lines and vias, respectively. The conductive material may include a diffusion barrier layer and a copper-containing metal material over the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

Metal line 34 includes a top conductive (metal) feature, such as a metal line, metal pad, or via 34A in a top dielectric layer that is the top layer of dielectric layer 38 (indicated as dielectric layer 38A). . In accordance with some embodiments, dielectric layer 38A is formed of a low-k dielectric material similar to the material of the underlying layer of dielectric layer 38 . Metal line 34 in top dielectric layer 38A may also be formed of copper or a copper alloy, and may include a dual damascene structure or a single damascene structure.

In accordance with some embodiments, etch stop layer 40 is deposited over top dielectric layer 38A and top metal layer. The etch stop layer 40 may be formed of or include silicon nitride, silicon carbide, silicon oxycarbide, or silicon oxynitride.

A passivation layer 42 (sometimes referred to as passivation-1 or pass-1) is formed over the etch stop layer 40 . According to some embodiments, passivation layer 42 is formed of a non-low-k dielectric material having a dielectric constant approximately equal to or greater than that of silicon oxide. The passivation layer 42 may include undoped silicate glass (USG), silicon nitride (SiN), silicon oxide (SiO ₂ ), silicon oxynitride (SiON), silicon oxide carbide (SiOC), or silicon carbide ( SiC), etc., combinations thereof, and/or multiple layers thereof, and may be formed of or include an inorganic dielectric material. According to some embodiments, top surfaces of top dielectric layer 38A and metal line 34 are flush with each other. Thus, the passivation layer 42 may be a planar layer.

Dielectric layer 44 is deposited over passivation layer 42 in accordance with some embodiments. Each process in process flow 200 shown in FIG. 20 is shown as process 202 . The dielectric layer 44 is formed of or includes a material different from the material of the passivation layer 42 and may be formed of or include a material such as SiC, SiN, SiON, or SiOC.

Referring to FIG. 2 , an etching mask 46 is formed and then patterned. In accordance with some embodiments, etch mask 46 includes photoresist and may or may not include a hard mask formed of TiN or BN or the like. Thereafter, anisotropic etching to form openings through dielectric layers including dielectric layer 44, passivation layer 42, etch stop layer 40, IMD 38, etch stop layer 37, ILD 28, etc. process is carried out. The semiconductor substrate 24 is further etched such that the opening 48 extends to an intermediate level of the substrate 24, which intermediate level is between the top surface 24A and the bottom surface of the semiconductor substrate 24. The opening 48 is thus formed. Each process in process flow 200 shown in FIG. 20 is shown as process 204 . Opening 48 is used to form a Through-Semiconductor Via (TSV) (sometimes also referred to as a Through-Silicon Via) and is therefore referred to hereinafter as TSV opening 48 . The anisotropic etching process includes a plurality of etching processes employing different etching gases for etching the semiconductor substrate 24 and for etching the dielectric layer formed of different materials.

According to some embodiments, the TSV opening 48 has a top width W1 and a bottom width W2 smaller than the top width W1. The TSV opening 48 may have a slanted straight edge 48E, and the slant angle α of the straight edge 48E is less than 90 degrees, such as within a range between about 80 degrees and about 90 degrees. there is. According to some embodiments, the aspect ratio H1/W1 of opening 48 may be in a range between about 2 and about 10. After formation of the TSV openings 48, the etching mask 46 is removed, for example, through an ashing process.

Referring to FIG. 3A, a first liner 50 is deposited. Each process in process flow 200 shown in FIG. 20 is shown as process 206 . The liner 50 includes a horizontal portion outside the TSV opening 48 and a vertical portion extending into the TSV opening 48 . According to some embodiments, liner 50 is formed of or includes a dielectric material such as silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide, or a combination thereof. According to an alternative embodiment, liner 50 is formed of or includes a conductive material such as Ti, TiN, Ta, or TaN, or a combination thereof. The thickness T1 of the liner 50 is small so that the liner 50, which may have a high k value, does not cause an adverse increase in the parasitic capacitance of the parasitic capacitor. For example, the thickness T1 of the liner 50 may be in the range of between about 2 Å and about 500 Å, and the thickness T1 may be measured at the mid-height of the vertical portion. The deposition method may include plasma enhanced chemical vapor deposition (PECVD), final atomic layer deposition (ALD), or physical vapor deposition (PVD). A precursor for forming the liner 50 may include a silicon-containing precursor such as SiCl ₄ , SiH ₂ Cl ₂ , Si ₂ Cl ₆ , or Si ₃ Cl ₈ . For example, when SiN is to be formed, NH ₃ Nitrogen-containing precursors such as According to some embodiments, the liner 50 has good ability to prevent diffusion and can prevent undesirable substances from penetrating the liner 50 .

According to some embodiments, liner 50 is a non-conformal layer, and liner 50 is a layer of TSV opening 48, with sidewalls of bottom portions of TSV opening 48 uncovered. The process conditions of deposition of the liner 50 are adjusted to cover the sidewall of the top portion. According to some embodiments, PECVD is used and some process conditions are adjusted to achieve a desired profile for the liner 50 . The process conditions to be adjusted may include the pressure of the process gas, the Si/N gas flow rate, and the like, and the Si/N gas flow rate is a ratio of the flow rate of the silicon-containing gas to the flow rate of the nitrogen-containing gas. For example, increasing the pressure of the process gas may cause the liner 50 to extend less toward the bottom of the TSV opening 48 (so that the height H2 is reduced), and reducing the pressure may cause the liner 50 to may be further extended toward the lower end of the TSV opening 48. Increasing the Si/N gas flow ratio may cause the liner 50 to extend less toward the bottom of the TSV opening 48, and decreasing the Si/N gas flow ratio may cause the liner 50 to extend less toward the bottom of the TSV opening 48. ) may be further extended toward the bottom of the By choosing the right process conditions, including the right combination of pressure and Si/N gas flow ratio, the bottom of the liner 50 can be positioned at the desired height. For example, as shown in FIG. 3A, the lower end 50bot is at a level (or substantially level) with the upper surface 24T of the semiconductor substrate 24, and the height difference is, for example, about 100 nm. smaller than

3B shows the formation of a liner 50 according to an alternative embodiment, wherein the bottom 50bot of the liner 50 is higher than the top surface 24T of the semiconductor substrate 24 . For example, sidewalls of upper layers of dielectric layer 38 may be covered by liner 50 and sidewalls of some lower layers of dielectric layer 38 are not covered by liner 50 . These embodiments may be applied when the bottom layer of dielectric layer 38 has a higher k value than the top layer of dielectric layer 38, so the liner 50 may have a lower k value (eg, less than 3.8). of a dielectric layer 38 having a higher k value (e.g., greater than about 3.5 or about 3.8) formed to cover sidewalls of the dielectric layer 38 (having a lower or lower k value of about 3.5 or less than about 3.0). The side walls are not protected. It is understood that a parasitic capacitor may form between the resulting TSV and the conductive or semiconductor material surrounding it, with the parasitic capacitance between the TSV and the semiconductor substrate 24 being a major contributor to the parasitic capacitance. Thus, if the liner 50 (which has a higher k value than the subsequently formed liner 52 (FIG. 4)) does not extend into the semiconductor substrate 24 as shown in FIGS. 3A and 3B, the parasitic Capacitance can be reduced.

3C illustrates the formation of a liner 50 according to another alternative embodiment, wherein the bottom 50bot of the liner 50 is lower than the top surface 24T of the semiconductor substrate 24 and the TSV opening 48 ) is higher than the lower end of Formation of the liner 50 in FIG. 3C can be accomplished by selecting the correct process conditions as described above.

3D illustrates the formation of a liner 50 according to another alternative embodiment, wherein the liner 50 covers all surfaces exposed to the TSV aperture 48, including the bottom surface of the TSV aperture 48. do. According to some embodiments, the liner 50 in FIG. 3D can be formed using PECVD, which can be achieved by selecting the right process conditions as described above. According to an alternative embodiment, liner 50 may be formed using a conformal deposition method such as ALD or CVD. The resulting liner 50 may thus be conformal, and may have horizontal and vertical portions with thickness variations of less than about 20 percent or about 10 percent, for example.

The liner 50 as shown in FIGS. 3A, 3B, 3C, and 3D may be a single layer dielectric liner or may be a composite liner such as a dual layer liner. 3A, 3B, 3C, and 3D show an exemplary double-layer liner 50 that includes dielectric (sub) liners 50A and 50B. It is understood that the liner 50 in FIGS. 3A, 3B, 3C, and 3D may also be a single layer liner. Accordingly, the lines separating liners 50A and 50B are shown as broken lines to indicate that these lines may or may not be present. According to some embodiments, liners 50A and 50B are formed of different materials or the same material with different compositions. For example, both dielectric liners may be formed of silicon nitride or silicon oxynitride, but the atomic percentage of nitrogen in liner 50A may be higher or lower than the atomic percentage of nitrogen in liner 50B. Liners 50A and 50B may be formed in separate processes, may be formed within the same process chamber (or may not be), or may be formed in-situ without a vacuum break in between. ) may be formed (or may not be). Accordingly, although not shown in detail in FIGS. 3A, 3B, 3C, and 3D, liners 50A and 50B may have different thicknesses, as shown in FIGS. 3E, 3F, and 3G, in accordance with some embodiments. can be extended to

3E, 3F, and 3G show some details of a double layer liner 50 as shown in FIGS. 3A, 3B, 3C, and 3D according to some embodiments. It is understood that the illustrated bottom level of liners 50A and 50B is exemplary, and the bottom of each of liners 50A and 50B may be at any level between the top and bottom of TSV opening 48 in any combination. . For example, the bottom of each of liners 50A and 50B may be at any level shown in FIGS. 3A, 3B, 3C, and 3D. 3E shows an embodiment in which liner 50B extends deeper into TSV opening 48 than liner 50A. 3F shows an embodiment in which liner 50B extends into TSV opening 48 to the same depth as liner 50A. 3G shows an embodiment in which liner 50B extends less into TSV opening 48 than liner 50A.

In embodiments such as those shown in FIGS. 3A-3G , since the liner 50 (and sublayers 50A and 50B) are deposited to different depths, process variations do not allow different portions of the liner 50 to be of the same depth or depth. It can be extended to different depths. For example, in each of FIGS. 3A-3G , the portion of the liner 50 to the left of the opening 48 is at the same depth as, greater or smaller than, the portion of the liner 50 to the right of the opening 48. depth can be extended. Also, the lower end portion of the liner 50 may have a progressively reduced thickness (rather than a uniform thickness). For example, FIG. 16 shows a bottom portion of a liner 50 having a progressively reduced thickness. 16 also shows that different portions of dielectric liner 50 can extend to different depths of TSV opening 48 . The depth difference ΔH may be greater than about 100 nm according to some embodiments.

Referring to FIG. 4 , a second liner 52 is deposited on the first liner 50 . Each process in process flow 200 shown in FIG. 20 is shown as process 208 . According to some embodiments, dielectric liner 52 is formed of a material different from that of liner 50 . For example, dielectric liner 52 may be formed of or include a dielectric material such as silicon oxide or silicon oxynitride. Accordingly, liner 52 is alternatively referred to as dielectric liner 52 . Dielectric liner 52 is deposited as a conformal layer such that the horizontal and vertical portions of dielectric liner 52 have thicknesses that are close to each other, eg, with variations of less than about 20 percent or about 10 percent. The deposition method may include atomic layer deposition (ALD) or chemical vapor deposition (CVD). The thickness T2 of the dielectric liner 52 may be in a range between about 500 angstroms and about 2,500 angstroms. Liners 50 and 52 are also collectively referred to as multilayer liners. According to some embodiments, the ratio T1:T2 may be in a range between about 0.001:1 and about 0.5:1.

Liners 50 and 52 may have different densities. According to some embodiments, dielectric liner 50 has a higher density than liner 52 . For example, the liner 50 may have a density DS50 within a range between about 3 g/cm ³ and about 10 g/cm ³ . The dielectric liner 52 may have a density DS52 in a range of between about 2.5 g/cm ³ and about 4 g/cm ³ . The density difference (DS52 - DS50) may be greater than about 0.5 g/cm ³ and may be in a range between about 0.5 g/cm ³ and about 7 g/cm ³ .

5 shows the deposition of a metal seed layer 54 . Each process in process flow 200 shown in FIG. 20 is shown as process 210 . In accordance with some embodiments, the metal seed layer 54 is formed via physical vapor deposition (PVD). The metal seed layer 54 may be a single layer, eg formed of copper, or may include a plurality of layers, eg, including a conductive barrier layer and a copper layer on the conductive barrier layer. The conductive barrier layer may be formed of or include TiN, Ti, TaN, or Ta.

6 shows the deposition of a conductive material 56, which may be a metallic material such as copper or a copper alloy. Each process in process flow 200 shown in FIG. 20 is shown as process 212 . The deposition process may be performed using electrochemical plating (ECP) or electroless plating. Plating is performed until the top surface of the conductive material 56 being plated is higher than the top surface of the liner 50 or 52 .

7 shows a planarization process performed to planarize the top surface of conductive material 56, which may be a CMP process or a mechanical grinding process. Each process in process flow 200 shown in FIG. 20 is shown as process 214 . According to some embodiments, as shown in FIG. 7, the planarization process is performed using dielectric layer 42 as a stop layer. According to an alternative embodiment, the planarization process is performed using another dielectric layer, such as dielectric layer 44 (FIG. 6), as the CMP stop layer. Thus, the top surface of the remaining conductive material 56 will be coplanar with the top surface of the dielectric layer 44 . The remaining portions of the metal seed layer 54 and the conductive material 56 are collectively referred to as through vias 61 hereinafter.

7-13 illustrate the formation of top features in accordance with some embodiments. It is understood that these processes are examples, and any other connection scheme is contemplated by this disclosure. Referring further to FIG. 7 , vias 58 for connection to the top metal line/pad 34 are formed. Each process in process flow 200 shown in FIG. 20 is shown as process 216 . According to some embodiments, via 58 is formed through a single damascene process. The formation process etches passivation layer 42 and underlying etch stop layer 37 to form openings, and deposits a conductive barrier (e.g., formed of titanium, titanium nitride, tantalum, tantalum nitride, etc.) and plating a conductive material such as copper or tungsten. A CMP process may then be performed to remove excess material, leaving vias 58 .

Referring to FIG. 8 , a dielectric isolation layer 60 is deposited, in accordance with some embodiments. Each process in process flow 200 shown in FIG. 20 is shown as process 218 . The material of the isolation layer 60 may be selected from the same group of candidate materials for forming the liner 50, and may be the same as or different from the material of the liner 50. For example, when the liner 50 is formed of silicon nitride, the isolation layer 60 may be formed of silicon nitride or silicon carbide.

Referring to FIG. 9 , the isolation layer 60 is etched and a metal pad 62 is formed on the passivation layer 42 . Each process in process flow 200 shown in FIG. 20 is shown as process 220 . The metal pad 62 may be an aluminum pad or an aluminum-copper pad, and other metal materials may be used. The formation process may include depositing the metal layer and then patterning the metal layer to leave the metal pads 62 . Metal pad 62 may also have some portion extending directly above isolation layer 60 according to some embodiments. A passivation layer 64 (sometimes referred to as passivation-2) is then formed. Each process in process flow 200 shown in FIG. 20 is shown as process 222 . The passivation layer 64 may be a single layer or a composite layer, and may be formed of a non-porous material such as silicon oxide, silicon nitride, USG, or silicon oxynitride.

Next, the passivation layer 64 is formed such that some portions of the passivation layer 64 cover the edge portion of the metal pad 62 and some portions of the metal pad 62 are exposed through the opening of the passivation layer 64. patterned. The polymer layer 66 is then formed, for example, by dispensing the polymer layer 66 in a flowable form and then curing the polymer layer 66 . Polymer layer 66 is patterned to expose metal pad 62 . Each process in process flow 200 shown in FIG. 20 is also shown as process 222 . The polymer layer 66 may be formed of polyimide or polybenzoxazole (PBO).

Then, as shown in FIG. 10, Under-Bump-Metallurgies (UBM) 68 and a conductive region 70 are formed to electrically connect to the underlying metal pad 62. Each process in process flow 200 shown in FIG. 20 is shown as process 224 . The formation process of UBM 68 and conductive region 70 deposits a blanket metal seed layer that extends into openings in passivation layer 64 and polymer layer 66, and forms a patterned plating mask on the metal seed layer. and plating the conductive region 70, removing the plating mask, and etching portions of the blanket metal seed layer previously covered by the plating mask. The remaining portion of the blanket metal seed layer is referred to as UBM 68 . The metal seed layer may include a titanium layer and a copper layer over the titanium layer. Conductive region 70 may include copper, nickel, palladium, aluminum, gold, alloys thereof, and/or multiple layers thereof. Each of the conductive regions 70 may include a copper region, which may or may not be capped with a solder region that may be formed of SnAg or a similar material. According to some embodiments, conductive region 70 protrudes higher than the top surface of the top dielectric layer in wafer 20 and may be used for solder bonding or direct metal-to-metal bonding. According to an alternative embodiment, dielectric layer 71 is formed with a top surface that is coplanar with the top surface of conductive region 70 and can be used for hybrid bonding.

11-13 show a process for forming features on the back side of a semiconductor substrate 24 . Each process in process flow 200 shown in FIG. 20 is shown as process 226 . Referring to Figure 11, a backside grinding process is performed to remove portions of substrate 24 until TSVs 61 are exposed. Next, as shown in FIG. 12 , the semiconductor substrate 24 is slightly recessed (eg, via etching) such that the TSVs 61 protrude out of the back surface of the semiconductor substrate 24 .

Next, as shown in FIG. 12, dielectric layer 72 is deposited, followed by a CMP process or mechanical grinding process to expose TSVs 61 again. TSV 61 thus penetrates dielectric layer 72 . According to some embodiments, dielectric layer 72 is formed of silicon oxide or silicon nitride, or the like. Referring to FIG. 13, an RDL 74 including a pad portion contacting the TSV 61 is formed. According to some embodiments, RDL 74 may be formed of aluminum, copper, nickel, titanium, or the like.

14A shows the formation of dielectric layer 76 and electrical connector 78 . According to some embodiments, electrical connector 78 includes a solder region, which may be formed by plating a solder ball onto a pad of RDL 74 and reflowing the solder ball. According to an alternative embodiment, electrical connector 78 is formed from a non-reflowable (non-solder) metallic material. For example, electrical connectors 78 may be formed as copper pads or pillars, and may or may not include a nickel capping layer. Electrical connector 78 may protrude out of the dielectric layer surrounding it and may be used for solder bonding or direct metal to metal bonding. Alternatively, the bottom surface of electrical connector 78 can be coplanar with the bottom surface of dielectric layer 76 so that device 22 can be used for hybrid bonding. Dielectric layer 71 is also shown in FIG. 14A, using broken lines to indicate that dielectric layer 71 on the front side of wafer 20 may or may not be formed. Although not shown in FIGS. 14B, 14C, 14D, 14E, 14F, and 14G, dielectric layer 71 may also be formed within the structure shown in these figures. According to some embodiments, wafer 20 is singulated through a sawing process, eg, by cutting through scribe line 80 .

14B, 14C, 14D, 14E, 14F, and 14G show structures formed based on the structures shown in FIGS. 3B, 3C, 3D, 3E, 3F, and 3G, respectively. do. Details of the processes and materials for forming the structures shown in FIGS. 14b, 14c, 14d, 14e, 14f, and 14g are shown in FIGS. Reference can be made to the discussion of each of FIG. 3G and the discussion of FIGS. 4-13 . In each of FIGS. 14A, 14B, 14C, and 14D, broken lines are drawn within the liner 50, indicating that the liner 50 can be a single layer liner or includes sub-liners 50A and 50B. indicating that it may be a layer liner. Further, the lower end of liner 50A may be lower than, level with, or higher than the lower end of each liner 50B. In FIG. 14A , the liner 50 has a bottom end 50bot flush with the top surface 24T of the semiconductor substrate 24 . When the dielectric liner 50 has two sub-liners 50A and 50B, one of the sub-liners 50A and 50B has a lower end 50bot parallel to the top surface 24T, and the other one has a lower end 50bot. The bottom end 50bot may be higher than, lower than, or flush with the top surface 24T of the semiconductor substrate 24 . 14B shows that the bottom end 50bot of the liner 50 (or at least one of the sub liners 50A and 50B) is higher than the top surface 24T. 14C shows that the bottom end of liner 50 (or at least one of subliners 50A and 50B) is lower than top surface 24T. 14D shows that the bottom end of the liner 50 (and sub liners 50A and 50B) extends to the bottom surface of the semiconductor substrate 24 . 14E shows that the sub liner 50A has a lower end higher than the lower end of the sub liner 50B. 14F shows that the sub liner 50A extends to the same level as the sub liner 50B. 14G shows that the sub liner 50A extends lower than the sub liner 50B.

In the above example, the top end of TSV 61 is flush with the top surface of passivation layer 42 . According to an alternative embodiment, the top end of TSV 61 may be at any other level lower than the top surface of passivation layer 42 (where applicable). For example, the top surface of TSV 61 can be coplanar with the top surface of the top metal layer in interconnect structure 32, and the top surface of any other dielectric layer in interconnect structure 32 can be the top surface of ILD 28. It may be coplanar with the top surface or may be coplanar with the top surface of the substrate 24 .

15 shows a plan view of TSV 61. According to some embodiments, each of liners 50A and 50B and dielectric liner 52 form a ring, which ring may have a circular shape or a polygonal shape (such as a hexagonal shape or an octagonal shape), or the like, according to some embodiments. The metal seed layer 54 may be distinguishable (provided it includes a material different from that of the conductive material 56).

16 shows TSV 61 and liners 50 and 52 according to some embodiments. The bottom end of liner 50 (and sub-layers 50A and 50B) can have a progressively reduced thickness, with the top being thicker than each bottom portion. As noted above, due to process variations, different portions of the liner 50 may extend to different levels. Additionally, there may or may not be some portion 50' of the liner 50 that is separated from the top of the liner 50 to form a separate island.

17-19 show an intermediate step in the formation of a package 81 (FIG. 19) containing the device 22 therein. It is understood that device 22 is shown schematically, and details of device 22 (such as the liner of a TSV) can be found with reference to the foregoing disclosure. Referring to FIG. 17 , device 22 is bonded to device 82 . Bonding can be performed through hybrid bonding, where dielectric layer 71 and electrical connector (conductive region) 70 are bonded to surface dielectric layer 84 and bond pad 86 of device 82, respectively. Device 82 may be a device die, package substrate, interposer, package, or the like.

18 shows the structure after the semiconductor substrate 24 has been subjected to a back surface grinding process and after recessing of the semiconductor substrate 24 through etching. Thus, the TSVs 61 protrude higher than the back surface of the semiconductor substrate 24 . Dielectric layer 72 is then deposited, as shown in FIG. 19, followed by a planarization process to level dielectric layer 72 and the top surface of TSV 61. A gap fill region 90 is then formed, which may be formed of or include a molding compound, silicon nitride, silicon oxide, or the like, or a combination thereof. Interconnect structures 92 including electrical connectors 78 are then formed over devices 22 and gap fill regions 90 . Interconnect structure 92 is electrically connected to device 82 via TSV 61 .

Embodiments of the present disclosure have several advantageous features. By forming more than one dielectric liner for through vias, the electrical performance of each device is more stable. Liners can be selectively formed on the sidewalls of some portions of the TSV (such as portions not within the semiconductor substrate) so that parasitic capacitance can be reduced.

According to some embodiments of the present disclosure, a method includes forming a plurality of dielectric layers over a semiconductor substrate; etching the plurality of dielectric layers and the semiconductor substrate to form an opening; depositing a first liner extending into the opening; depositing a second liner over the first liner, the second liner extending into the opening; filling the opening with a conductive material to form a through via; and forming conductive features on both sides of the semiconductor substrate, the conductive features electrically interconnected through through vias. In an embodiment, depositing the first liner is performed using a non-conformal deposition method. In an embodiment, depositing the second liner is performed using a conformal deposition method. In an embodiment, the first liner is deposited to have a first lower end higher than the second lower end of the opening. In an embodiment, the first bottom is flush with the top surface of the semiconductor substrate. In an embodiment, the first bottom is higher than the top surface of the semiconductor substrate. In an embodiment, the first bottom is lower than the top surface of the semiconductor substrate. In an embodiment, depositing the first liner includes depositing a conductive liner and depositing the second liner includes depositing a dielectric liner. In an embodiment, depositing the first liner includes depositing silicon nitride and depositing the second liner includes depositing silicon oxide. In an embodiment, depositing the first liner includes depositing silicon carbide and depositing the second liner includes depositing silicon oxide.

According to some embodiments of the present disclosure, the structure includes a semiconductor substrate; a plurality of dielectric layers over the semiconductor substrate; a first conductive feature over the plurality of dielectric layers; a second conductive feature underlying the semiconductor substrate; a through via through the semiconductor substrate and the plurality of dielectric layers, the through via electrically interconnecting the first conductive feature and the second conductive feature; a first liner surrounding the through vias; and a second liner surrounding the first liner, the second liner having a higher density than the first liner. In an embodiment, the first liner physically contacts the top portion of the through via and the second liner physically contacts the bottom portion of the through via. In an embodiment, the bottom end of the second liner is flush with the top surface of the semiconductor substrate. In an embodiment, the bottom end of the second liner is higher than the top surface of the semiconductor substrate. In an embodiment, the bottom end of the second liner is lower than the top surface of the semiconductor substrate. In an embodiment, the first liner includes silicon oxide and the second liner includes silicon nitride. In an embodiment, the second liner includes a first sub-layer and a second sub-layer surrounding the first sub-layer, wherein bottom ends of the first sub-layer and the second sub-layer are at different levels.

According to some embodiments of the present disclosure, the structure includes a die. The die includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; through-vias penetrating the semiconductor substrate and the plurality of low-k dielectric layers; a first liner enclosing the through-via, the first liner extending to both the top and bottom ends of the through-via; a second liner enclosing the first liner, the second liner being shorter than the through via; a first electrical connector on the semiconductor substrate and on the top surface of the die; and a second electrical connector under the semiconductor substrate and at a bottom surface of the die, wherein the first electrical connector and the second electrical connector are electrically interconnected through through vias. In an embodiment, the second liner has a higher density than the first liner. In an embodiment, the second liner is thinner than the first liner.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. It should be appreciated that those skilled in the art may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments presented herein. In addition, those skilled in the art should appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure.

<Bookkeeping>

1. In the method,

forming a plurality of dielectric layers on a semiconductor substrate;

etching the plurality of dielectric layers and the semiconductor substrate to form an opening;

depositing a first liner extending into the opening;

depositing a second liner over the first liner, the second liner extending into the opening;

filling the opening with a conductive material to form a through via; and

forming conductive features on both sides of the semiconductor substrate, the conductive features electrically interconnected through the through vias;

Including, method.

2. The method of clause 1, wherein depositing the first liner is performed using a non-conformal deposition method.

3. The method of clause 2, wherein depositing the second liner is performed using a conformal deposition method.

4. The method of point 1 wherein the bottom of the first liner is higher than the bottom of the opening.

5. The method of clause 4 wherein the bottom of the first liner is flush with the top surface of the semiconductor substrate.

6. The method of clause 4 wherein the bottom of the first liner is higher than the top surface of the semiconductor substrate.

7. The method of clause 4 wherein the bottom of the first liner is lower than the top surface of the semiconductor substrate.

8. The method of clause 1, wherein depositing the first liner comprises depositing a conductive liner and depositing the second liner comprises depositing a dielectric liner.

9. The method of clause 1, wherein depositing the first liner comprises depositing silicon nitride and depositing the second liner comprises depositing silicon oxide.

10. The method of clause 1, wherein depositing the first liner comprises depositing silicon carbide and depositing the second liner comprises depositing silicon oxide.

11. In the structure,

semiconductor substrate;

a plurality of dielectric layers over the semiconductor substrate;

a first conductive feature over the plurality of dielectric layers;

a second conductive feature underlying the semiconductor substrate;

a through via through the semiconductor substrate and through the plurality of dielectric layers, the through via electrically interconnecting the first conductive feature and the second conductive feature;

a first liner surrounding the through-via; and

a second liner surrounding the first liner, the second liner having a higher density than the first liner;

Including, the structure.

12. The structure of item 11, wherein the first liner physically contacts the top portion of the through-via and the second liner physically contacts the bottom portion of the through-via.

13. The structure of clause 12, wherein the bottom end of the second liner is flush with the top surface of the semiconductor substrate.

14. The structure of clause 12 wherein the bottom end of the second liner is higher than the top surface of the semiconductor substrate.

15. The structure of clause 12, wherein the bottom end of the second liner is lower than the top surface of the semiconductor substrate.

16. The structure of clause 11 wherein the first liner comprises silicon oxide and the second liner comprises silicon nitride.

17. The method of item 11, wherein the second liner includes a first sub-layer and a second sub-layer surrounding the first sub-layer, wherein lower ends of the first sub-layer and the second sub-layer are different. A structure in a level.

18. In the structure,

die

Including, wherein the die,

semiconductor substrate;

a plurality of low-k dielectric layers over the semiconductor substrate;

a through via passing through the semiconductor substrate and the plurality of low-k dielectric layers;

a first liner surrounding the through-via, the first liner extending to both upper and lower ends of the through-via;

a second liner surrounding the first liner, the second liner being shorter than the through via;

a first electrical connector over the semiconductor substrate and on a top surface of the die; and

a second electrical connector under the semiconductor substrate and at a bottom surface of the die, the first electrical connector and the second electrical connector electrically interconnected through the through via;

Including, the structure.

19. The structure of clause 18, wherein the second liner has a higher density than the first liner.

20. The structure of clause 18, wherein the second liner is thinner than the first liner.

Claims (10)

in the method,
forming a plurality of dielectric layers over a semiconductor substrate;
etching the plurality of dielectric layers and the semiconductor substrate to form an opening;
depositing a first liner extending into the opening, a first bottom end of the first liner being higher than a second bottom end of the opening;
depositing a second liner over the first liner, the second liner extending into the opening;
filling the opening with a conductive material to form a through via; and
forming conductive features on both sides of the semiconductor substrate, the conductive features electrically interconnected through the through vias;
including,
wherein the first liner is shorter than the through via, and wherein the second liner extends to both the top and bottom ends of the through via. in the structure,
semiconductor substrate;
a plurality of dielectric layers over the semiconductor substrate;
a first conductive feature over the plurality of dielectric layers;
a second conductive feature underlying the semiconductor substrate;
a through via through the semiconductor substrate and through the plurality of dielectric layers, the through via electrically interconnecting the first conductive feature and the second conductive feature;
a second liner surrounding the through-via; and
a first liner enclosing the second liner, the first liner having a higher density than the second liner, a first lower end of the first liner being higher than a second lower end of the through via;
including,
wherein the first liner is shorter than the through via, and wherein the second liner extends to both the top and bottom ends of the through via. 3. The structure of claim 2, wherein the second liner physically contacts the top portion of the through via and the first liner physically contacts the bottom portion of the through via. 4. The structure of claim 3, wherein the bottom end of the first liner is flush with the top surface of the semiconductor substrate. 4. The structure of claim 3, wherein the bottom end of the first liner is higher than the top surface of the semiconductor substrate. 4. The structure of claim 3, wherein the bottom end of the first liner is lower than the top surface of the semiconductor substrate. 3. The structure of claim 2 wherein the second liner comprises silicon oxide and the first liner comprises silicon nitride. 3. The method of claim 2, wherein the first liner includes a first sub-layer and a second sub-layer surrounding the first sub-layer, wherein bottom ends of the first sub-layer and the second sub-layer are at different levels. in the structure. in the structure,
die
Including, wherein the die,
semiconductor substrate;
a plurality of low-k dielectric layers over the semiconductor substrate;
a through via passing through the semiconductor substrate and the plurality of low-k dielectric layers;
a second liner surrounding the through-via, the second liner extending to both upper and lower ends of the through-via;
a first liner surrounding the second liner, the first liner being shorter than the through via;
a first electrical connector over the semiconductor substrate and on a top surface of the die; and
a second electrical connector under the semiconductor substrate and at a bottom surface of the die, the first electrical connector and the second electrical connector electrically interconnected through the through via;
Including, the structure. 10. The structure of claim 9, wherein the first liner is thinner than the second liner.

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