DE102020101271A1 - Bottom-up formation of contact plugs - Google Patents

Abstract

One method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer that extends into the trench, performing a nitriding process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.

Description

PRIORITY CLAIM AND CROSS REFERENCE

This application claims priority of the provisional U.S. Patent Application No. 62 / 903,424 , filed September 20, 2019, entitled "Bottom-up Formation of Contact Plugs," which is incorporated herein by reference.

GENERAL STATE OF THE ART

In integrated circuit manufacture, / source / drain contact plugs are used to connect to the source and drain regions and gates of transistors. The source / drain contact plugs are typically connected to source / drain silicide regions, the process of which involves forming contact openings in an interlayer dielectric, depositing a metal layer that extends into the contact openings, and then performing an anneal around the To allow the metal layer to react with the silicon / germanium of the source / drain regions, includes. The source / drain contact plugs are then formed in the remaining contact openings.

Figure list

• 1-6, 7A, 7B, 8-11, 12A, 12B und 13-22 veranschaulichen die perspektivischen Ansichten und Querschnittsansichten von Zwischenstufen bei dem Bilden eines Transistors und der jeweiligen Kontaktstecker gemäß einigen Ausführungsformen.
• 23 veranschaulicht ein Produktionswerkzeug zum Bilden von Kontaktsteckern gemäß einigen Ausführungsformen.
• 24 veranschaulicht einen Prozessfluss zum Bilden eines Transistors und der jeweiligen Kontaktstecker gemäß einigen Ausführungsformen.

Aspects of the present disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Indeed, the dimensions of the various features may be increased or decreased arbitrarily for ease of discussion.

• 1-6 , 7A , 7B , 8-11 , 12A , 12B and 13-22 10 illustrate the perspective and cross-sectional views of intermediate stages in the formation of a transistor and the respective contact plugs in accordance with some embodiments.
• 23 Figure 11 illustrates a production tool for forming contact plugs in accordance with some embodiments.
• 24 illustrates a process flow for forming a transistor and the respective contact plugs in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are of course only examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also include embodiments in which additional features between the first and second Feature may be formed so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

Furthermore, spatially related terms such as "below", "below", "lower", "overlying", "upper" and the like may be used herein for a more convenient description of describing the relationship of one element or feature to another element (s) ) or feature (s) as illustrated in the figures may be used. The spatial terms are intended to encompass various orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or with other orientations) and the spatial descriptors used herein may be interpreted accordingly.

A transistor and the method of forming it are provided in accordance with some embodiments. The intermediate stages in forming the transistor and corresponding contact plugs are illustrated in accordance with some embodiments. The intermediate stages of forming the transistors and vias are illustrated in accordance with some embodiments. Some variations of some embodiments are discussed. Like reference characters are used to refer to like elements throughout the several views and illustrative embodiments. In the illustrated embodiments, the formation of fin field effect transistors (FinFETs) is used as an example to explain the concept of the present disclosure. Other types of transistors, such as nanowire transistors, nanolayer transistors, planar transistors, gate-all-around (GAA) transistors, and the like, may also incorporate the concept of the present disclosure. Furthermore, the method can be used for other interconnection structures, such as vias, metal lines or the like become. While method embodiments can be discussed as being performed in any particular order, other method embodiments can be performed in any logical order.

According to some embodiments of the present disclosure, a source / drain contact plug and a gate contact plug are each formed over and contacting a source / drain region and a gate electrode of a transistor. The processes for forming the contact plugs include depositing a metal layer, nitriding a surface portion of the metal layer to form a metal nitride layer, and performing an annealing process to form source / drain silicide. The metal nitride layer is then oxidized so that the resulting oxide can be removed, and some portions of the metal nitride layer are left on the undersides of the contact openings. The metal nitride layers are used as the basis for selectively depositing a metal, and the deposition is from bottom to top.

1-6 , 7A , 7B , 8-11 , 12A , 12B and 13-22 10 illustrate the perspective and cross-sectional views of intermediate stages in forming a FinFET and corresponding contact plugs in accordance with some embodiments of the present disclosure. The processes shown in these figures are also schematic in the process flow 400 reproduced as in 24 shown.

In 1 is a substrate 20th provided. The substrate 20th may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator substrate (SOI substrate, Semiconductor-On-Insulator Substrate) or the like, which is doped (e.g. with a p- or an n- Dopant) or undoped. The semiconductor substrate 20th can be part of a wafer 10 such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator can be, for example, a buried oxide layer (BOX layer, buried oxide layer), a silicon oxide layer or the like. The insulator layer is provided on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as a multilayer substrate or a gradient substrate, can also be used. In some embodiments, the semiconductor material of the semiconductor substrate can be 20th Silicon; Germanium; a compound semiconductor including silicon carbide, SiPC, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

Continuing with reference to 1 is a tub region 22nd in the substrate 20th educated. The particular process is called a process 402 in the process flow 400 illustrated in 24 is shown. According to some embodiments of the present disclosure, the well region is 22nd a p-well region formed by implanting a p-type impurity, which may be boron, indium, or the like, into the substrate 20th is formed. In accordance with other embodiments of the present disclosure, the well region is 22nd an n-well region formed by implanting an n-type impurity, which may be phosphorus, arsenic, antimony, or the like, into the substrate 20th is formed. The resulting pan region 22nd can extend to the top surface of the substrate 20th extend. The n or p impurity concentration can be 10 ¹⁸ cm -3 or less, such as in the range between about 10 ¹⁷ cm ^-3 and about 10 ¹⁸ cm ^-3 .

With reference to 2 are isolation regions 24 formed so as to extend from a top surface of the substrate 20th into the substrate 20th extend into it. The isolation regions 24 are alternatively referred to below as shallow trench isolation regions (STI regions). The particular process is called a process 404 in the process flow 400 illustrated in 24 is shown. The sections of the substrate 20th between neighboring STI regions 24 are called semiconductor strips 26th designated. To form the STI regions 24 become a pad oxide layer 28 and a hard mask layer 30th on the semiconductor substrate 20th formed and then structured. The pad oxide layer 28 may be a thin film made of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer is 28 formed in a thermal oxidation process, wherein an upper surface layer of the semiconductor substrate 20th is oxidized. The pad oxide layer 28 acts as an adhesion layer between the semiconductor substrate 20th and the hard mask layer 30th . The pad oxide layer 28 can also be used as an etch stop layer for etching the hard mask layer 30th Act. According to some embodiments of the present disclosure, the hard mask layer is 30th formed from silicon nitride, for example using low-pressure chemical vapor deposition (LPCVD). According to other embodiments of the present disclosure, the hard mask layer is 30th formed by thermal nitriding of silicon or plasma-enhanced chemical vapor deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition). A photoresist (not shown) is placed on the hard mask layer 30th formed and then structured. The hard mask layer 30th is then formed using the patterned photoresist as an etch mask of hard masks 30th structured as in 2 is shown.

Next is the textured hard mask layer 30th as an etching mask for etching the pad oxide layer 28 and the substrate 20th is used, followed by filling the resulting trenches in the substrate 20th with (a) dielectric material (ien). A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, is performed to remove excess portions of the dielectric materials, and the remaining portions of the dielectric material (s) are STI regions 24 . The STI regions 24 may have a liner dielectric (not shown), which may be a thermal oxide produced by thermal oxidation of a surface layer of the substrate 20th is formed. The liner dielectric can also be a deposited silicon oxide layer, silicon nitride layer, or the like, which, for example, using atomic layer deposition (ALD), chemical high-density plasma vapor deposition (HDPCVD, high-density plasma chemical vapor deposition) or chemical vapor deposition (CVD, Chemical Vapor Deposition) is formed. The STI regions 24 may also include a dielectric material over the liner oxide, which dielectric material can be formed using flowable chemical vapor deposition (FCVD), spin-on coating, or the like. The dielectric material over the liner dielectric may include silicon oxide in accordance with some embodiments.

The upper surfaces of the hard masks 30th and the top surfaces of the STI regions 24 can be essentially at the same level. The semiconductor strips 26th are located between neighboring STI regions 24 . According to some embodiments of the present disclosure, the semiconductor strips are 26th Parts of the original substrate 20th and is thus the material of the semiconductor strips 26th the same as that of the substrate 20th . In accordance with alternative embodiments of the present disclosure, the semiconductor strips are 26th Replacement strips made by etching the sections of the substrate 20th between the STI regions 24 for forming recesses and performing an epitaxy for growing another semiconductor material again in the recesses. The semiconductor strips are accordingly 26th formed from a semiconductor material different from that of the substrate 20th differs. According to some embodiments, the are semiconductor strips 26th formed from silicon germanium, silicon carbon or a III-V compound semiconductor material.

With reference to 3rd become the STI regions 24 recessed so that the upper sections of the semiconductor strips 26th higher than the upper surfaces 24A of the remaining sections of the STI regions 24 protrude to protruding fins 36 to build. The particular process is called a process 406 in the process flow 400 illustrated in 24 is shown. The etching can be performed using a dry etching process using, for example, HF ₃ and NH ₃ as the etching gases. Plasma can be generated during the etching process. Argon can also be absorbed. In accordance with alternative embodiments of the present disclosure, omitting the STI regions 24 performed using a wet etch process. The etch chemical can include HF, for example.

The protruding fins 36 can be formed from or replaced by other semiconductor materials. For example, for NMOS transistors, the above fins 36 be formed from or comprise Si, SiP, SiC, SiPC or a III-V compound semiconductor (such as, for example, InP, GaAs, AlAs, InAs, InAlAs, InGaAs or the like). For PMOS transistors, the above fins 36 be formed from or comprise Si, SiGe, SiGeB, Ge or a 111-V compound semiconductor (such as InSb, GaSb, InGaSb or the like).

In the previously illustrated embodiments, the fins can be patterned by any suitable method. For example, the fins can be patterned using one or more photolithography processes including double patterning or multiple patterning processes. In general, double structuring or multiple structuring processes combine photolithography and self-aligned processes, which enables the creation of patterns having, for example, spaces that are smaller than what can otherwise be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers or mandrels can then be used to structure the fins.

With reference to 4th are dummy gate stacks 38 formed in such a way that they rest on the upper surfaces and the side walls of the (protruding) fins 36 extend. The particular process is called a process 408 in the process flow 400 illustrated in 24 is shown. The dummy gate stack 38 can use dummy gate dielectrics 40 and dummy gate electrodes 42 over the dummy gate dielectrics 40 exhibit. The dummy gate electrodes 42 for example, can be formed using polysilicon, and other materials can also be used. Each of the dummy gate stacks 38 can also have one (or more) hard mask layer 44 over the dummy gate electrodes 42 exhibit. The hard mask layers 44 may be formed from silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stack 38 can be one or more of the above fins 36 and / or STI regions 24 cross. The dummy gate stack 38 also have longitudinal directions perpendicular to the longitudinal directions of the protruding fins 36 on.

Next are the gate spacers 46 on the sidewalls of the dummy gate stacks 38 educated. The particular process is also called a process 408 in the process flow 400 shown in 24 is shown. According to some embodiments of the present disclosure, the gate spacers 46 formed from a dielectric material (s) such as silicon nitride, silicon carbonitride or the like, and may have a single-layer structure or a multilayer structure including a plurality of dielectric layers.

An etching process is then performed to the portions of the protruding fins 36 to etch those not from the dummy gate stacks 38 and the gate spacers 46 covered what is related to the in 5 structure shown. The particular process is called a process 410 in the process flow 400 illustrated in 24 is shown. The recess can be anisotropic and thus the sections become the fins 36 that are directly below the dummy gate stacks 38 and the gate spacers 46 lying, protected and not etched. The upper surfaces of the recessed semiconductor strips 26th can be lower than the upper surfaces 24A of the STI regions 24 according to some embodiments. The recesses 50 are formed accordingly. The recesses 50 have sections that are on opposite sides of the dummy gate stack 38 and portions between remaining portions of the protruding fins 36 .

Next, epitaxial regions (source / drain regions) 54 by selectively growing (by epitaxy) a semiconductor material in the recesses 50 formed leading to the structure in 6th leads. The particular process is called a process 412 in the process flow 400 illustrated in 24 is shown. Depending on whether the resulting FinFET is a p-FinFET or an n-FinFET, a p- or n-impurity can be doped on site as the epitaxy progresses. For example, if the resulting FinFET is a p-FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), or the like can be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like can be grown. According to alternative embodiments of the present disclosure, the epitaxial regions have 54 111-V compound semiconductors such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof or multiple layers thereof. After the cutouts 50 with the epitaxial regions 54 are filled, causes the further epitaxial growth of the epitaxial regions 54 that the epitaxial regions 54 expand horizontally, and facets can be formed. The further growing of the epitaxial regions 54 can also cause neighboring epitaxial regions 54 merge with each other. There may be gaps (air gaps) 56 be generated. According to some embodiments of the present disclosure, forming the epitaxial regions 54 be terminated when the top surface of the epitaxial regions 54 is still wavy, or if the top surface of the fused epitaxial regions 54 has become planar, which by further growing on the epitaxial regions 54 is achieved, as in 6th is shown.

After the epitaxy step, the epitaxial regions 54 can also be implanted with a p or an n impurity to form source and drain regions, which are also identified using the reference numeral 54 Marked are. According to alternative embodiments of the present disclosure, the implantation step is skipped if the epitaxial regions 54 be doped on site with the p- or n-impurity during the epitaxy.

7A 13 illustrates a perspective view of the structure after the contact etch stop layer (CESL) 58 and the inter-layer dielectric (ILD) are formed. The respective process is a process 414 in the process flow 400 illustrated in 24 is shown. The CESL 58 can be formed from silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, or the like, and can be formed using CVD, ALD, or the like. The ILD 60 may comprise a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or some other deposition process. The ILD 60 can be formed by an oxygen-containing dielectric material, which can be a silicon oxide-based material such as silicon oxide, Phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), silicon oxycarbide, a high-k dielectric material such as zirconium oxide, hafnium oxide, or a low-k dielectric material. A planarization process, such as a CMP process or a mechanical grinding process, can be performed on the top surfaces of the ILD 60 , the dummy gate stack 38 and the gate spacer 46 to align with each other.

7B illustrates the reference cross-section 7B-7B in 7A at which the dummy gate stack 38 are illustrated. It can be seen that the structures are on the right-hand side of the source / drain region 54 (such as in the regions 63 ) are not shown, while in some embodiments a structure including a same gate structure as the gate structure 38 and the corresponding gate spacers in the region 63 and the region to the right of the region 63 can be formed.

Next are the dummy gate stacks 38 including the hard mask layers 44 , the dummy gate electrodes 42 and the dummy gate dielectrics 40 etched, trenches 62 between the gate spacers 46 be formed as in 8th is shown. The particular process is called a process 416 in the process flow 400 illustrated in 24 is shown. The top surfaces and the side walls of the protruding fins 36 become the trenches 62 exposed. As in 9 Next, shown are replacement gate stacks 68 in the trenches 62 educated ( 8th ). The particular process is called a process 418 in the process flow 400 illustrated in 24 is shown. The replacement gate stacks 68 have gate dielectrics 64 and the corresponding gate electrodes 66 on.

According to some embodiments of the present disclosure, the gate dielectric comprises 64 an Interfacial Layer (IL) 64 as its lower part. The IL is on the exposed surfaces of the protruding fins 36 educated. The IL may have an oxide layer, such as a silicon oxide layer, which is formed by the thermal oxidation of the protruding fins 36 , a chemical oxidation process or a deposition process is formed. The gate dielectric 64 may also include a high-k dielectric layer formed over the IL. The high-k dielectric layer comprises a high-k dielectric material such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide or the like. The dielectric constant (k value) of the high K dielectric material is greater than 3.9 and can be greater than about 7.0 and sometimes has a height of 21.0 or more. The high-k dielectric layer lies over the IL and can touch it. In accordance with some embodiments of the present disclosure, the high-k dielectric layer is formed using ALD, CVD, PECVD, molecular beam deposition (MBD), or the like.

The gate electrode 66 is on the gate dielectric 64 educated. The gate electrode 66 may have multiple stacked layers, which may be formed as conformal layers, and a filler metal region covering the rest of the trenches 62 fills that are not filled by the multiple stacked layers. The stacked layers may include a barrier layer, a work function layer over the barrier layer, and one or more metal cover layers over the work function layer. The fill metal region can be formed from tungsten, cobalt, or the like. According to alternative embodiments, the barrier layer may not be formed and the cover layers can completely fill the trenches and the fill metal region is not formed.

10 illustrates the formation of self-aligned hard masks 70 according to some embodiments. The particular process is called a process 420 in the process flow 400 illustrated in 24 is shown. According to other embodiments, the self-aligned hard masks are 70 not educated. The formation of the hard masks 70 may include performing an etch process to cut gate stacks 68 so that there are gaps between gate spacers 46 , filling the recesses with a dielectric material, and then performing a planarization process, such as a CMP process or a mechanical grinding process, to remove excess portions of the dielectric material. The hard masks 70 may be formed from or comprise silicon nitride, silicon oxynitride, silicon oxycarbonitride or the like. Thus, the FinFET 100 is formed.

With reference to 11 becomes the etch stop layer 72 educated. According to some embodiments of the present disclosure, the etch stop layer is 72 formed from a dielectric material which may include silicon nitride, silicon oxycarbide, silicon oxynitride, aluminum oxide, or the like, or multiple layers thereof. The ILD 74 becomes over the etch stop layer 72 deposited. The processes for forming the etch stop layer 72 and the ILD 74 are as a process 424 in the process flow 400 illustrated in 24 is shown. According to some embodiments, the ILD 74 formed from a material selected from the same group of candidate materials for forming the ILD 58 is selected.

12A and 12B illustrate the formation of the source / drain contact opening 76 and the gate contact opening 78 . The particular process is called a process 424 in the process flow 400 illustrated in 24 is shown. The formation process of the source / drain contact hole 76 may include forming a patterned photoresist (not shown) and etching the ILD 74 , the etch stop layer 72 , of the ILD 60 and the CESL 58 to expose the source / drain region 54 include. The gate contact opening formation process 78 may include forming another patterned photoresist (not shown) and etching the ILD 74 , the etch stop layer 72 and the hard mask 70 to expose the gate electrode 66 include. The source / drain contact opening 76 and the gate contact opening 78 can be formed by different etching processes or can be formed using common etching processes. In accordance with some embodiments, is the source / drain contact opening 76 elongated and has a longitudinal direction (X direction) perpendicular to the source / drain region direction (Y direction). According to some embodiments, the ILDs 74 and 58 using the mixed gases of NF ₃ and NH ₃ , the mixed gases of HF and NH _3, or the like. The etch stop layer 72 and the CESL 58 can be etched using the mixed gases of CF ₄ , O ₂ and N2, the mixed gases of NF ₃ and O ₂ , the mixed gases of SF ₆ and O _2, or the like. After the contact openings 76 and 78 are formed, a cleaning process can be performed to remove the polymer generated in the etching process. The cleaning process can be carried out using oxygen ( 02 ) or the mixture of H ₂ and N ₂ , generating plasma, followed by a wet cleaning process using deionized water.

12B illustrates the reference cross-section 12B-12B in 12A . According to some embodiments, the widths are W1 of the openings 76 and 78 in the range of between about 12 nm and about 20 nm. The aspect ratios (which are the ratios of the depths to the respective widths) of the openings 76 and 78 can be in the range of between about 6 and 8.

Next, referring to FIG 13th dielectric spacers 80 educated. The formation process may include depositing a dielectric cover layer and etching the dielectric cover layer by an anisotropic etching process. The dielectric cover layer can be a conformal or substantially conformal layer, for example the thickness of horizontal sections and vertical sections having a difference that is less than about 10 percent of the horizontal thickness. The deposition can be achieved by ALD, CVD, or the like. The dielectric spacers 80 can be formed from a dielectric material selected from SiN, SiON, SiCN, SiC, SiOCN, AlON, AlN, HfOx, combinations thereof, and / or multiple layers thereof. The dielectric spacers 80 can help prevent leakage between the subsequently formed source / drain contact plug and the gate contact plug. The thickness of the dielectric spacers 80 can range between about 1 nm and about 3 nm.

With reference to 14th becomes the metal layer 82 deposited, which are in both the source / drain contact opening 76 as well as the gate contact opening 78 extends into it. The particular process is called a process 426 in the process flow 400 illustrated in 24 is shown. The metal layer 82 may be formed from or comprise pure or substantially pure (e.g., above 95 percent) Ti, Ta, Ni, or the like, or alloys thereof. The metal layer 82 is a non-conformal layer, the thickness being T1 of the horizontal sections greater than the thickness T2 of vertical sections is. The fat T2 can be at the middle depths of the openings 76 and 78 be measured. According to some embodiments of the present disclosure, the ratio is T1 / T2 greater than 5: 1 and can range between about 5: 1 and about 15: 1. For example, the thickness can T1 are in the range of between about 100 Å and about 150 Å. The fat T2 can range from between about 6 Å and about 20 Å. In accordance with some embodiments of the present disclosure, the deposition is performed by physical vapor deposition (PVD). To the desirable relationship T1 / T2 To achieve this, the deposition can be performed with a bias current (and a bias voltage) applied. For example, the bias voltage can be greater than about 150 volts and can range between about 150 volts and about 300 volts.

15th illustrates a nitriding process 83 for forming the metal nitride layer 84 . The particular process is called a process 428 in the process flow 400 illustrated in 24 is shown. According to some embodiments, the nitriding process is carried out by treating the metal layer 82 in a nitrogen-containing process gas such as ammonia (NH3). The metal nitride layer 84 may be formed from or include TiN, TaN, NiN, or the like, or combinations thereof. The nitriding process can be carried out by a thermal nitriding process and / or a plasma nitriding process. A surface layer of the metal layer 82 is in the metal nitride layer 84 transformed. The Sidewall portions of the metal layer 82 can be completely converted. Alternatively, a surface layer becomes each of the side wall portions of the metal layer 82 converted while an inner portion of the side wall portions of the metal layer 82 Metal layer remains. The horizontal sections of the metal nitride layer 84 are partially converted, the metal nitride layer 84 the remaining portions of the metal layer 82 overlaps. According to alternative embodiments, instead of depositing and then nitriding a metal layer, the metal nitride layer is used 84 over the metal layer 82 deposited. According to some embodiments, on the undersides of the source / drain contact opening 76 and the gate contact opening 78 the fat T3 the metal nitride layer 84 are in the range of between about 4 nm and about 6 nm.

16 illustrates the silicidation process by annealing, leaving the metal layer 82 with the source / drain region 54 reacts to the silicide region 86 to form which titanium silicide, tantalum silicide, nickel silicide or the like, depending on the metal in the metal layer 82 , includes. The particular process is called a process 430 in the process flow 400 illustrated in 24 is shown. The fat T4 the silicide region 86 can range between about 4 nm and about 6 nm. The silicidation process can be accomplished by annealing the wafer 10 at a temperature in the range of between about 500 ° C and about 600 ° C, for example for a time in the range of between about 10 seconds and about 20 seconds. As a result of the silicidation process, the sections of the metal layer 82 on the underside of the source / drain contact opening 76 completely silicided and thus touches the metal nitride layer 84 the silicide region 86 . On the gate electrode 66 can the metal layer 82 still have a portion that is under the respective part of the metal nitride layer 84 remains.

With reference to 17th becomes an oxidation process 87 performed to the metal oxide layer 88 to form, which can be formed from or comprise TiOX, TaOX, NiOx or combinations thereof. The particular process is called a process 432 in the process flow 400 illustrated in 24 is shown. The metal oxide layer 88 may include nitrogen therein and thus may be a metal oxynitride layer, with metal oxynitride being considered a type of metal oxide. For example, the portion of the metal oxide layer 88 in the gate contact opening 78 a metal oxide layer consisting of the metal layer 82 and a metal oxynitride layer composed of the metal nitride layer 84 is formed, include, wherein the metal oxynitride layer overlies and contacts the metal oxide layer. On the other hand, the sections of the metal nitride layer 84 in the source / drain contact opening 76 on the side walls of the contact openings 76 and 78 and over the ILD layer 74 all completely converted to metal oxynitride. On the bottom of each of the source / drain contact openings 76 and the gate contact opening 78 a metal nitride layer remains 84 unoxidized. This is achieved by controlling the oxidation time and temperature.

The oxidation can be carried out using an oxygen-containing gas such as oxygen ( 02 ), Ozone (O ₃ ) or the like. The oxidation can be carried out by a thermal process using the aforementioned process gases, with plasma being generated or not. The oxidation can be carried out by using the plasma that is generated using the aforementioned process gases, with the temperature of the wafer 10 is room temperature or higher during the oxidation. The temperature of the wafer 10 during the thermal and / or plasma oxidation process can also be in the range between room temperature and approximately 250 ° C, in the range between approximately 160 ° C and approximately 250 ° C. The flow rate of the oxygen-containing gas can range between about 2,000 sccm and about 6,000 sccm. The oxidation time can range between about 15 seconds and about 60 seconds. The oxidation is carried out without applying a bias voltage or a bias current.

In a subsequent process, the metal oxide layer is created 88 removed by etching. The particular process is called a process 434 in the process flow 400 illustrated in 24 is shown. According to some embodiments, the etching is performed using a chlorine-based etching gas such as TaCl ₅ , WCl ₅ , WCl ₆ , MoCl ₅ , NbCl _5, or the like, or combinations thereof. The etching can be performed by a thermal dry etching process, taking the temperature of the wafer 10 is in the range of between about 300 ° C and about 500 ° C. Etching can be done with or without plasma. Likewise, no hydrogen is produced during the etching ( H2 ) introduced and no NH ₃ introduced. Otherwise, the process gases can be a precursor for depositing a metal layer instead of for etching the metal oxide layer 88 become. As a result of the etching, the metal oxide layer becomes 88 completely removed. The etch is self-limiting, with the remaining metal nitride layer 84 acts as an etch stop layer. A thin layer of the metal nitride layer 84 thus becomes on the underside of each of the source / drain contact openings 76 and the gate contact opening 78 left behind. The remaining metal nitride layer 84 can be a thickness T5 in the range of between about 1 nm and about 3 nm. The metal nitride layers 84 can also be as thin as possible provided that they all have complete coverage of the undersides of the source / drain contact opening 76 and the gate contact opening 78 on.

18th illustrates a treatment process that occurs on the metal nitride layer 84 is carried out. The particular process is called a process 436 in the process flow 400 illustrated in 24 is shown. The treatment can be carried out using a process gas, with the wafer 10 in which process gas is soaked. The process gas can comprise TaCl ₅ , NiCl ₄ , WCl ₅ , MoCl ₅ or the like or combinations thereof. During the treatment, the wafer becomes 10 heated, for example to a temperature in the range of between about 200 ° C and about 500 ° C. No plasma is generated. The duration of treatment can be greater than about 5 seconds and can range between about 5 seconds and 50 seconds. When TiCl _{4 is used} as the treatment process _{gas, the TiCl 4} soaking causes the resulting molecules (such as TiCl ₃ molecules) to bond with the dangling bonds of the underlying metal nitride layers 84 get connected. The linked molecules are shown as 89, as in FIG 18th shown. On the other hand, there are no molecules of the treatment gas with the surfaces of the exposed dielectric materials, such as the dielectric spacers 80 and the dielectric layer 74 , connected.

19th also illustrates the selective deposition of the silicon layer 90 using a silicon-containing gas as a precursor, which can be SiH ₄ , Si2H ₆ , Si ₃ H _8, or the like, or combinations thereof. The particular process is called a process 438 in the process flow 400 illustrated in 24 is shown. The deposition can be carried out using chemical vapor deposition (CVD) or other applicable methods. During the deposition of the silicon layer 90 can the wafer 10 for example, to a temperature in the range of between about 400 ° C and about 550 ° C. The pressure of the precursor can range between about 15 torr and about 40 torr. The deposition time can range between about 30 seconds and about 600 seconds. The silicon layer 90 may have a thickness in the range of between about 1 Å and about 10 Å, and the thickness may be in the range of between about 1 Å and about 10 Å or in the range of between about 1 Å and about 5 Å. The silicon layer 90 can be an amorphous layer.

When the silicon layer 90 is formed, and when hydrogen (e.g. from SiH ₄ ) is provided, Si-H bonds are formed on the top surface of the silicon layers 90 educated. This provides a good foundation for the subsequent filling of metal, and the silicon layer 90 acts as a seed layer for the selective deposition of metal in the source / drain contact opening 76 and the gate contact opening 78 . According to alternative embodiments, the chlorine-based gas treatment and / or the deposition of the silicon layer are used 90 not done. According to some embodiments, even if these processes are not performed with a suitable process gas selected, some bottom-up effect can still be achieved by using the metal nitride layers 84 can be achieved as a basis for selective deposition. However, the selectivity of the deposition is higher when the silicon layer 90 where the selectivity is the ratio of the rate of deposition of metal on silicon to the rate of deposition of metal on dielectric materials.

20th illustrates the selective bottom-up deposition of a metal into the source / drain contact opening 76 and the gate contact opening 78 so that the metal regions 92 are formed. The particular process is called a process 440 in the process flow 400 illustrated in 24 is shown. According to some embodiments, the regions are metal 92 formed from or comprise aluminum, molybdenum, ruthenium, iridium, tungsten, cobalt, or the like, or combinations thereof. The entire metal regions 92 can be homogeneous. According to some embodiments in which aluminum is deposited, the reaction process gases include dimethyl aluminum hydride (DMAH) and hydrogen ( H2 ). The DMAH tends to deposit aluminum selectively, particularly on the silicon layer. The deposition process can include CVD or similar processes. The deposition temperature can range between about 175 ° C and about 275 ° C. The pressure of the reaction gases can range between about 1 torr and about 3 torr. The resulting metal regions 92 can completely cover the source / drain contact opening 76 and the gate contact opening 78 or filled so that they have upper surfaces that are slightly lower than the upper surface of the ILD 74 are. For example, the height of the metal regions 92 are in the range of between about 500 Å and about 1,500 Å, depending on the depths of the source / drain contact opening 76 and the gate contact opening 78 .

The silicon layer 90 acts as a seed layer to deposit the metal region 92 . On the other hand, metal does not become on exposed dielectric materials, such as on the surfaces of the dielectric spacers 80 and the ILD 74 , deposited. The deposition of the metal region is corresponding 92 a selective one Deposition process and a bottom-up deposition process. The resulting metal regions 92 are germ-free. Since aluminum has good adhesion with respect to the metal nitride layer 84 , the dielectric spacer 80 and the ILD 74 has, the metal regions 92 can be formed without having to form adhesive layers (barriers) (which are typically made of Ti, TiN, Ta, TaN, or the like). The resulting contact plugs are therefore barrier-free.

23 illustrates a production tool 200 to perform the processes as in 18th , 19th and 20th shown. The production tool 200 has a charging module 110 for loading and unloading wafers and several process chambers. The process chambers include chambers 112 for etching the metal oxide (oxynitride) layer 88 (in 17th shown), chambers 114 for treating the metal nitride layers and depositing the silicon layers 90 ( 19th ) and chambers 116 to deposit the metal region 92 ( 20th ). The etching of metal oxide layers, the treatment of the metal nitride layer 84 and the deposition of the silicon layer 90 and the deposition of the metal region 92 are on site in the production tool 200 carried out so that no vacuum interruption occurs between these processes. Otherwise, the exposed areas of the metal nitride layers 84 and the silicon layers 90 are oxidized and the subsequent deposition processes may not be selective.

In a subsequent process, the structure goes through, as in 20th shown a thermal process to the metal regions 92 to melt. During the melting process, hydrogen ( H2 ) can be used as a process gas, leaving some undesirable impurities, such as carbon, in the metal regions 92 removed. During the melting process, the temperature of the wafer 10 in the thermal process are in the range of between about 400 ° C and about 450 ° C. Aluminum, when used, can be in the metal regions 92 be partially melted. As a result of the melting, the metal regions show 92 a polycrystalline structure and the grain size can advantageously be enlarged compared to before the melting. For example, prior to the melting process, over 75 percent (grain number percentage) of the grains in the metal regions have a grain size in the range of between approximately 2 nm and approximately 8 nm. After the melting process, over 75 percent of the grains have grain sizes that fall in the range of between approximately 9 nm and approximately 15 nm. Furthermore, with the melting, joints or gaps are created in the metal region 92 removed, if present.

Depending on whether the melting process is carried out or not, and depending on the temperature of the subsequent process, the silicon layers 90 with the overlying metal regions 92 react (or not) to metal silicide regions 91 which may be aluminum silicide (AlSi _Y ) regions in accordance with some embodiments. Accordingly, the corresponding region is marked and is called silicon-containing regions 90 / 91 referred to to indicate that distinguishable silicon layers 90 may be present or metal silicide regions 91 may be present. In some embodiments, the thickness of the metal silicide regions is 91 in the range of between about 2 Å and about 30 Å.

With reference to 21 a planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, is performed to remove excess portions of the metal regions 92 remove, leaving the top surfaces of the metal regions 92 coplanar with the upper surface of the ILD 74 are. The particular process is called a process 442 in the process flow 400 illustrated in 24 is shown. The source / drain contact plug 94A and the gate contact plug 94B are thus formed.

According to some embodiments, the source / drain contact plug 94A the metal region 94 who have favourited silicon layer 90 or the silicide region 91 and the metal nitride layer 84 on. The metal nitride layer 84 lies above the silicide region 86 and touches them. The elements (such as Ti and Cl) that are introduced by the treatment (using TiCl ₄ ) can be at the interface between the silicon layer 90 and the metal nitride layer 84 are located. The silicon layer can also 90 or the silicide region 91 may or may not be a distinguishable layer because it is too thin and also due to the fact that the subsequent thermal process can cause its diffusion. The silicon atom percentage in the silicon-containing regions 90 / 91 may be the highest, and the atomic percentages decrease in the direction further away from the silicon-containing regions 90 / 91 . Similarly, some elements, such as chlorine, can be found in the silicon-containing regions 90 / 91 (due to the TiCl ₄ treatment), the concentrations of these elements may decrease further away from the interfacial regions. For example, the arrows illustrate 96A and 96B in 21 the directions in which the chlorine percentages can gradually decrease. The arrow 96A also illustrates the direction in which the silicon atom percentage decreases. It should be noted, however, that the silicon atom percentage is in the silicide region 86 can reach a peak. Accordingly, the silicon atom percentage can have two concentration peaks, the first peak in the silicide region 86 lies and the second tip where the silicon layer 90 is, lies. The second peak can be lower than the first peak. The silicon atom percentage in the metal nitride layer 84 can be less than both peaks.

According to some embodiments, the gate contact plug comprises 94B the metal region 94 , the silicon-containing region 90 / 91 and the metal nitride layer 84 on. A titanium layer 82 may or may not be present. Accordingly, either touches the lower surface of the metal nitride layer 84 or the lower surface of the titanium layer 82 the gate electrode 66 . The elements (such as Ti and Cl) introduced by the treatment (using TiCl ₄ ) can be at the interface between the silicon-containing region 90 / 91 and the metal nitride layer '4 are located. The silicon-containing region 90 / 91 may or may not be a distinguishable layer because it is too thin and also due to the fact that the subsequent thermal process can cause its diffusion. The silicon atom percentage in the silicon-containing region 90 / 91 may be the highest and the atomic percentages decrease in the direction further away from the silicon-containing region 90 / 91 . Similarly, some elements, such as chlorine, can be observed in the interfacial regions and the concentrations of these elements may decrease further away from the interfacial regions. For example, the arrows illustrate 97 in 21 the directions in which the silicon atom percentages and chlorine percentages can gradually decrease.

22nd illustrates the formation of the etch stop layer 122 and the dielectric layer 124 . According to some embodiments, the etch stop layer is 122 formed from silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide or the like, or multiple layers thereof, wherein the dielectric layer 124 may be a low-k dielectric layer. The vias 130 and 132 are formed in such a way that they extend into the dielectric layer 124 and the etch stop layer 122 extend in and each of the source / drain contact plug 94A and the gate contact plug 94B touch. Each of the vias 130 and 132 can the adhesion / barrier layer 126 and the fill metal region 128 exhibit. The adhesion / barrier layer 126 may be formed from Ti, TiN, Ta, TaN, or the like. The filler metal region 128 may include Ru, Ir, Mo, W, Cu, or the like, or alloys thereof.

The embodiments of the present disclosure have several advantageous features. By oxidizing the metal nitride layers, the metal nitride layers can be removed from sidewalls and top surfaces of the dielectric layers, while the metal nitride layers can be selectively left on the undersides of the contact openings. This enables the selective deposition of silicon layers and thus the selective deposition from bottom to top of metal regions. Accordingly, the contact plugs are sterile.

According to some embodiments of the present disclosure, a method includes etching a dielectric layer to form a trench in the dielectric layer; depositing a metal layer extending into the trench; performing a nitriding process on the metal layer to convert a top portion of the metal layer into a metal nitride layer; performing an oxidation process on the metal nitride layer to form a metal oxynitride layer; removing the metal oxynitride layer; and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug. In one embodiment, a source / drain region is exposed under the dielectric layer after the trench is formed. In one embodiment, the method further comprises performing an annealing process after the nitriding process and before the oxidation process to react a lower portion of the metal layer with the source / drain region to form a silicide region. In one embodiment, after the metal oxynitride layer is removed, a lower portion of the metal nitride layer remains on an underside of the trench. In one embodiment, the method further comprises selectively depositing a silicon layer on the lower portion of the metal nitride layer, wherein the metallic material is selectively grown from the silicon layer. In one embodiment, the method further comprises, prior to the selective deposition of the silicon layer, treating the lower portion of the metal nitride layer using titanium chloride (TiCl ₄ ). In one embodiment, the oxidation process that is carried out on the metal nitride layer results in the entire metal nitride layer over the dielectric layer and the entire metal nitride layer being nitrided on sidewalls of the dielectric layer, with a lower section of the metal nitride layer remaining on an underside of the trench after the oxidation process. In one embodiment, the removal of the metal oxynitride layer and the filling of the metallic material on site are performed in the same vacuum environment.

According to some embodiments of the present disclosure, a device includes a contact etch stop layer; a first interlayer dielectric over the contact etch stop layer; and a contact plug that extends into the contact etch stop layer and the first interlayer dielectric extends into, the contact plug comprising: a metal nitride layer; a silicon-containing layer over the metal nitride layer; and a homogeneous metallic material over the silicon-containing layer. In one embodiment, the metal nitride layer has a first metal and the homogeneous metallic material has a second metal that differs from the first metal. In one embodiment, the silicon-containing layer comprises aluminum silicide. In one embodiment, the device further comprises chlorine at an interface between the silicon-containing layer and the metal nitride layer. In one embodiment, the device further includes a silicide region underlying the metal nitride layer, wherein first chlorine atom concentrations in the silicon-containing layer and the metal nitride layer are higher than second chlorine atom concentrations in the homogeneous metallic material and the silicide region. In one embodiment, the metal nitride layer does not extend on sidewalls of the homogeneous metallic material. In one embodiment, sidewalls of the homogeneous metallic material touch sidewalls of the first interlayer dielectric. In one embodiment, the device further comprises an etch stop layer over the first interlayer dielectric; and a second interlayer dielectric over the etch stop layer, wherein the contact plug further extends into the etch stop layer and the second interlayer dielectric. In one embodiment, the device further comprises a metal layer under the metal nitride layer; and a gate electrode underlying and contacting the metal layer.

According to some embodiments of the present disclosure, a device has a source / drain region; a first metal silicide region over and in contact with the source / drain region; a contact plug over and in contact with the first metal silicide region, the contact plug comprising: a metal nitride layer; a second metal silicide region over the metal nitride layer; and an aluminum region over the second metal silicide region. In one embodiment, the contact plug is barrier-free. In one embodiment, the device further comprises a contact etch stop layer; an interlayer dielectric over the contact etch stop layer; and a dielectric spacer encircling and contacting the contact plug, the dielectric spacer extending into both the contact etch stop layer and the interlayer dielectric.

The foregoing illustrates features of various embodiments so that one skilled in the art may better understand aspects of the present disclosure. One skilled in the art should recognize that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments presented herein. One skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure and can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

QUOTES INCLUDED IN THE DESCRIPTION

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Patent literature cited

• US 62903424 [0001]

Claims (20)

Procedure comprising: Etching a dielectric layer to form a trench in the dielectric layer; Depositing a metal layer extending into the trench; Performing a nitriding process on the metal layer to convert an upper portion of the metal layer into a metal nitride layer; Performing an oxidation process on the metal nitride layer to form a metal oxynitride layer; Removing the metal oxynitride layer; and Filling a metallic material into the trench using a bottom-up deposition process to form a contact plug. Procedure according to Claim 1 , exposing a source / drain region beneath the dielectric layer after the trench is formed. Procedure according to Claim 2 , further comprising, after the nitriding process and before the oxidation process, performing an annealing process to react a lower portion of the metal layer with the source / drain region to form a silicide region. A method according to any preceding claim, wherein after the metal oxynitride layer is removed, a lower portion of the metal nitride layer remains on an underside of the trench. Procedure according to Claim 4 further comprising selectively depositing a silicon layer on the lower portion of the metal nitride layer, wherein the metallic material is selectively grown from the silicon layer. Procedure according to Claim 5 , further comprising, prior to the selective deposition of the silicon layer, treating the lower portion of the metal nitride layer using titanium chloride (TiCl ₄ ). Method according to one of the preceding claims, wherein the oxidation process which is carried out on the metal nitride layer results in the entire metal nitride layer over the dielectric layer and the entire metal nitride layer being nitrided on sidewalls of the dielectric layer, a lower section of the metal nitride layer being nitrided on an underside of the trench remains after the oxidation process. Method according to one of the preceding claims, wherein the removal of the metal oxynitride layer and the filling of the metallic material on site are carried out in the same vacuum environment. Apparatus comprising: a contact etch stop layer; a first interlayer dielectric over the contact etch stop layer; and a contact plug extending into the contact etch stop layer and the first interlayer dielectric, the contact plug comprising: a metal nitride layer; a silicon-containing layer over the metal nitride layer; and a homogeneous metallic material over the silicon-containing layer. Device according to Claim 9 wherein the metal nitride layer comprises a first metal and the homogeneous metallic material comprises a second metal that is different from the first metal. Device according to Claim 10 wherein the silicon-containing layer comprises aluminum silicide. Device according to one of the Claims 9 to 11 which further comprises chlorine at an interface between the silicon-containing layer and the metal nitride layer. Device according to Claim 12 further comprising a silicide region underlying the metal nitride layer, wherein first chlorine atom concentrations in the silicon-containing layer and the metal nitride layer are higher than second chlorine atom concentrations in the homogeneous metallic material and the silicide region. Device according to one of the previous ones Claims 9 to 13th wherein the metal nitride layer does not extend on sidewalls of the homogeneous metallic material. Device according to one of the previous ones Claims 9 to 14th wherein sidewalls of the homogeneous metallic material contact sidewalls of the first interlayer dielectric. Device according to one of the previous ones Claims 9 to 15th further comprising: an etch stop layer over the first interlayer dielectric; and a second interlayer dielectric over the etch stop layer, the contact plug further extending into the etch stop layer and the second interlayer dielectric. Device according to one of the previous ones Claims 9 to 16 further comprising: a metal layer under the metal nitride layer; and a gate electrode underlying and contacting the metal layer. A device comprising: a source / drain region; a first metal silicide region over and in contact with the source / drain region; and a contact plug over and in contact with the first metal silicide region, the contact plug comprising: a metal nitride layer; a second metal silicide region over the metal nitride layer; and an aluminum region over the second metal silicide region. Device according to Claim 18 , whereby the contact plug is barrier-free. Device according to Claim 18 or 19th Further comprising: a contact etch stop layer; an interlayer dielectric over the contact etch stop layer; and a dielectric spacer encircling and contacting the contact plug, the dielectric spacer extending into both the contact etch stop layer and the interlayer dielectric.

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