DE102019205183A1 - Method of making an ion trap - Google Patents

Abstract

A method for producing a three-dimensional ion trap (10) with the following steps: providing a first substrate (20) and a second substrate (22), forming an isolation region (34, 36) on a first surface of at least one of the substrates (20, 22) , Applying and structuring a metallization (38) on both substrates (20, 22), forming bonding areas on mutually facing sides of the substrates (20, 22), forming a continuous recess in the at least one substrate (20, 22) on which the isolation area (34, 36) is formed, removal of the isolation area (34, 36) in the area of the recess of the at least one substrate (20, 22) on which the isolation area (34, 36) is formed, connection of the two substrates (20 , 22) through a bonding process.

Description

The invention relates to a method for producing an ion trap and to such an ion trap, in particular a three-dimensional ion trap.

State of the art

In an ion trap, ions are held as electrically charged atoms or molecules by means of electric and magnetic fields. Depending on the type and strength of the acting fields, ions of a certain mass can be specifically trapped. Alternatively, all ions can be kept in the trap and ions of a certain mass can be removed by changing the fields and thus the ion supply can be scanned or scanned in a targeted manner, separated by mass.

Micromechanical processes such as those used in MEMS (Microelectromechanical Systems) are used to produce such an ion trap. It should be noted that micromechanical processes are a key technology in order to represent scalable platforms, in particular qubit platforms, on the basis of ion traps. A qubit, also known as a quantum bit, is a two-state quantum system that can be manipulated at will and thus a system that can be correctly described by quantum mechanics and can only have two distinguishable states. In quantum computing, qubits play the same role as the classic bit in conventional computers.

The parallel alignment of the electrodes using lithography and wafer bonding processes is possible with very low tolerances. Conventional two-dimensional ion traps that are easy to manufacture have the disadvantage that the achievable containment energies are in the range of thermal energy at room temperature and are significantly lower than with three-dimensional ion traps. In particular, three-dimensional ion traps are the best option for realizing quantum computers that work at room temperature.

To confine the ions, ion traps based on the Paul trap principle are preferably used, in which an electrostatic field in combination with an HF alternating field ensures that the ions are contained in potential.

For the production of the three-dimensional ion traps with micromechanical processes, on the one hand, simple structuring of the substrate is advantageous, which is why semiconductor substrates, for example made of silicon, are preferably used. On the other hand, the RF wave must not be absorbed in the substrate, which is why insulating ceramic substrates are used. Ceramic substrates, however, are very difficult to structure and can become superficially charged, especially since high-energy light is usually radiated in to manipulate the quantum states of the ions. However, stray charges can lead to undesirable interactions with the ions stored in the trap. For this reason, a higher conductivity of the trap walls is sought.

Disclosure of the invention

Against this background, a method according to claim 1 and an arrangement according to claim 9 are presented. Embodiments emerge from the dependent claims and from the description.

The method described serves to produce an ion trap, in particular a three-dimensional ion trap, and provides that the ion trap is built up in a multi-stage process based on at least two substrates, in embodiments on two substrates.

• - Bereitstellen zweier Substrate,
• - Bilden eines Isolationsbereichs zumindest auf einer ersten Oberfläche des ersten und/oder zweiten Substrats,
• - Aufbringen und Strukturieren einer Metallisierung auf beiden Substraten,
• - Ausbilden von Bondflächen auf den später einander zugewandten Seiten der Substrate,
• - Ausbilden einer durchgängigen Ausnehmung in dem mindestens einen Substrat, auf dem bzw. auf denen der Isolationsbereich gebildet ist, und gegebenenfalls einer weiteren Ausnehmung,
• - Entfernen des Isolationsbereichs im Bereich der Ausnehmung des mindestens einen Substrats, auf dem bzw. auf denen der Isolationsbereich gebildet ist,
• - Verbinden der beiden Substrate durch einen Bondprozess,
• - Freilegen der verdeckten Bondpads auf dem zweiten Substrat.

The presented method can include the following steps:

• - providing two substrates,
• - Forming an isolation region at least on a first surface of the first and / or second substrate,
• - Application and structuring of a metallization on both substrates,
• - Formation of bonding surfaces on the later facing sides of the substrates,
• - Forming a continuous recess in the at least one substrate on which or on which the insulation area is formed, and optionally a further recess,
• Removal of the insulation area in the area of the recess of the at least one substrate on which the insulation area is formed,
• - connecting the two substrates by a bonding process,
• - Exposing the covered bond pads on the second substrate.

It should be noted that the metallization can be applied in several layers.

The insulation area below the conductor tracks is formed by dielectric side walls of a cover layer and cavities.

The three-dimensional ion trap presented, which is produced in particular by a method of the type presented here, enables high-quality three-dimensional ion traps to be displayed. The ion trap architecture enables a low HF absorption with higher conductivity of the trap walls and easier structuring of the substrate.

• - mindestens zwei übereinander angeordnete Substrate, von denen mindestens eines im Wesentlichen leitfähig ist,
• - auf beiden Substraten Elektroden,
• - eine im ersten leitfähigen Substrat ausgebildete durchgängige Substratausnehmung mit leitfähigen Seitenwänden, wobei die Elektroden die Substratausnehmung überragen und wobei zwischen Elektroden-Metallisierung und leitfähigem Substrat abschnittsweise ein Isolationsbereich wenigstens im Bereich der Leiterbahnen angeordnet ist.

The presented three-dimensional ion trap component comprises in configuration:

• - at least two substrates arranged one above the other, at least one of which is essentially conductive,
• - electrodes on both substrates,
• - A continuous substrate recess formed in the first conductive substrate with conductive side walls, the electrodes projecting beyond the substrate recess and an insulation area being arranged in sections between the electrode metallization and the conductive substrate, at least in the area of the conductor tracks.

The insulation area can have a thickness of 5 to 100 μm, in an embodiment 20 to 100 μm. The insulation area can also be formed by a bridge structure made up of pillars or supporting walls and a cover layer over a cavity. This isolation area is alternatively formed by a porous structure. The material of the isolation region can be an oxide, e.g. B. a SiO ₂ , be.

Both substrates can have a substrate recess, the recesses at least partially overlapping in a projection along an axis perpendicular to a main direction of extent of the substrates.

The first substrate can have a further recess area directly adjoining the recess area on the surface facing the second substrate.

In a peripheral region of the surfaces facing one another, the substrates have bonding connection areas which consist, for example, of Au / Si, Au / Ge, Au / In or Au / Au.

The first substrate can be made of silicon, e.g. B. made of highly doped and thus conductive silicon. The second substrate can be conductive, for example made of highly doped silicon, or insulating, e.g. B. made of glass.

The electrode metallization can be formed from Au or Pt and can have an adhesion promoter layer made from Ti, TiW, Cr at least in the area of the supply lines on the insulation area. Furthermore, the electrode metallization can consist of several layers of Au or Pt and thin intermediate layers of a further conductive material, such as, for example, Ti / Au / Ti / Au / Ti / Au in the insulation area and Au / Ti / Au / Ti / Au in the recess area.

In addition, the three-dimensional ion trap or the three-dimensional ion trap component can comprise a third substrate with a third layer of electrodes on a third substrate. In one embodiment, the second substrate projects beyond the first substrate in at least one main direction of extent, it being possible for contact regions for the electrodes to be provided on the second substrate.

The third substrate can be formed corresponding to the second substrate or with essentially the same method steps as the second substrate.

The electrodes can protrude from the substrate recess by at least 10 µm, for example by about the distance between the ions and the DC and HF electrodes. The side walls of the substrate recess can be at least partially coated with a further conductive material, for example a noble metal.

Further advantages and configurations of the invention emerge from the description and the accompanying drawings.

It goes without saying that the features mentioned above and those yet to be explained below can be used not only in the respectively specified combination, but also in other combinations or on their own, without departing from the scope of the present invention.

Figure list

• 1 shows a schematic representation of a section through an embodiment of the three-dimensional ion trap presented.
• 2 shows the three-dimensional ion trap 1 in a top view.
• 3 shows a further embodiment of the ion trap presented.
• 4th Figure 3 shows yet another embodiment of the ion trap.
• 5 shows the provision of two substrates.
• 6th shows the application and structuring of a metallization.
• 7th shows the formation of bond pads.
• 8th shows the formation of a continuous recess at least in a first substrate.
• 9 removing the insulation region at least in the region of the recess in the first substrate.
• 10 shows the connection of the two substrates by a bonding process.
• 11 illustrates the uncovering of the covered bond pads on the second substrate.
• 12 shows the isolation area in a detailed representation.

Embodiments of the invention

The invention is shown schematically on the basis of embodiments in the drawings and is described in detail below with reference to the drawings.

1 shows in a schematic cross section an embodiment of the presented three-dimensional ion trap, denoted as a whole with the reference number 10 is designated. This ion trap 10 includes a top chip 12 and a lower chip 14th . The illustration shows a first substrate 20th and a second substrate 22nd , a bond area 24 , a first recess 26th , a second recess 28 , another recess 30th , a bond pad 32 , a first isolation area 34 , a second isolation area 36 , a metallization 38 , an adhesion promoting layer and a diffusion barrier 40 , a first RF electrode 42 , a first DC electrode 44 , a second HF electrode 46 and a second DC electrode 48 . In the first recess 26th an ion trap area 50 is provided.

The ion trap shown 10 thus comprises two substrates 20th , 22nd with a crossover arrangement of the DC electrodes 44 , 48 and RF electrodes 42 , 46 after Paul.

2 shows the three-dimensional ion trap in a schematic plan view 10 out 1 . The illustration shows the top chip 12 and the lower chip 14th , the bond area 24 , a bond pad area 60 , the first HF electrode 42 , the first DC electrode 44 , the first recess 26th and the ion trap regions 50.

3 shows, in a schematic cross section, a further embodiment of the 3 D ion trap presented, denoted as a whole by the reference number 100 is designated. This ion trap 100 includes a top chip 112 and a lower chip 114 . The illustration shows a first substrate 120 and a second substrate 122 , which is formed as an insulating lower substrate, a bonding area 124 , a recess 126 , another recess 130 , a bond pad 132 , an isolation area 134 , a metallization 138 , an adhesion promoting layer and a diffusion barrier 140 , a first RF electrode 142 , a first DC electrode 144 , a second HF electrode 146 and a second DC electrode 148 . In the recess 126 an ion trap area 150 is provided.

The ion trap shown 100 thus comprises two substrates 120 , 122 with a crossover arrangement of the DC electrodes 144 , 148 and RF electrodes 142 , 146 after Paul. Contrasted with running out 1 is at the ion trap 100 out 3 the insulating lower substrate 122 intended.

4th shows, in a schematic cross section, a schematic representation of a further embodiment of the three-dimensional ion trap, denoted as a whole by reference number 200 is designated. The ion trap 200 includes a top chip 212 , a medium chip 214 and a lower chip 216 . The illustration shows a first substrate 220 , a second substrate 222 , a third substrate 224 , a first bond area 226 , a second bond area 228 , a first recess 230 , a second recess 232 , a third recess 234 , a first further recess 240 , a second further recess 242 , a first bond pad 244 , a second bond pad 246 , a first isolation area 250 , a second isolation area 252 , a third isolation area 254 , a metallization 260 , an adhesion promoting layer and a diffusion barrier 262 , first DC electrodes 270 , first HF electrodes 272 and second DC electrodes 274 . In an area roughly between the first recess 230 and the second recess 232 an ion trap area 280 is provided.

There are thus three substrates in this embodiment 220 , 222 , 224 with an arrangement of the DC electrodes 270 , 274 above and below as well as the HF electrodes 272 in the middle provided for Paul.

The following figures illustrate in a process flow, each in a schematic cross section, the production of embodiments of the three-dimensional ion trap presented.

5 shows the division into an upper chip 300 and a lower chip 302 and providing a first substrate 304 and a second substrate 306 , being on the first substrate 304 a first isolation area 310 and on the second substrate 302 a second isolation area 312 the substrates on at least one surface in each case 304 , 306 provided. Details can be found in 12 .

6th shows the application and structuring of a metallization on both substrates 304 , 306 . After these steps are an adhesion promoting layer and a diffusion barrier 322 , a metallization 320 as well as a bond pad 324 intended.

7th illustrates the formation of bond areas on the later facing sides of the substrates 304 , 306 . The illustration shows a bond area for this purpose 330 .

8th shows the formation of a continuous recess at least in a first substrate and possibly a further recess. The illustration shows a first recess for this purpose 340 , a second recess 342 and another recess 344 . In the first recess 340 an ion trap area 350 is provided.

9 shows the removal of the isolation area 310 or. 312 at least in the region of the recess of the first substrate.

10 shows the joining of the two substrates 304 , 306 through a bonding process.

11 illustrates the uncovering of the covered bond pads on the second substrate.

• - Trenchätzen der Pfeiler bzw. Stützwände (Bezugsziffer 400),
• - Verfüllen mit einem Verfüllmaterial, z. B. Oxid, (Bezugsziffer 402)
• - Öffnen eines Opferschichtätzzugangs + Opferschichtätzen von Substratmaterial, z. B. mit XeF2, (Bezugsziffer 404),
• - optional Verschließen mit einer Deckschicht, z. B. Oxid. (Bezugsziffer 406).

12 shows the isolation area in a detailed representation. This isolation area below the conductor tracks is made of dielectric side walls, e.g. B. formed from oxide or nitride, a cover layer and cavities. Manufacturing can include the following steps:

• - Trench etching of the pillars or retaining walls (reference number 400 ),
• - Backfilling with a backfill material, e.g. B. Oxide, (ref 402 )
• - Opening a sacrificial layer etching access + sacrificial layer etching of substrate material, e.g. B. with XeF2, (reference number 404 ),
• - optionally closing with a top layer, e.g. B. Oxide. (Reference number 406 ).

It must be taken into account that the Paulian ion traps in a first embodiment require a crossed quadrupole arrangement of DC and HF electrodes. In the method described, this arrangement is achieved by arranging two substrates with a recess. The recess forms, on the one hand, an enclosure volume for the ions and, on the other hand, provides access both for the ions and for the light necessary for manipulating the qubits.

It can be of advantage if the substrate forming the side walls of the ion trap is made conductive. In this way, unwanted charges on the side walls can be avoided. The continuous recess is necessary in order to enable the trap to be loaded with ions, to provide an enclosure volume and to create an optical access for the light for manipulation. The electrodes advantageously protrude beyond the substrate recess so that the electrical or electromagnetic fields are defined as well as possible and are not shielded by the substrate. As the electrodes protrude beyond the substrate recess, the influence of possible stray charges on the walls of the substrate recess is also reduced. The insulation area below the supply lines is intended to prevent the absorption or attenuation of the RF wave by the substrate and to prevent electrical breakdown to the substrate.

The insulation area typically has a thickness of 5 to 100 μm, in an embodiment 20 to 100 μm. The isolation area must on the one hand meet electrical requirements as described above and on the other hand remain mechanically stable. It has been shown that a thickness of 5 to 100 µm is a suitable compromise.

There are several possibilities for realizing the insulation area: It can be formed by a bridge structure made up of pillars or supporting walls and a cover layer over a cavity or also by a porous structure. An oxide, for example an SiO2, and / or a nitride, for example a Si-rich nitride, is preferably considered as the material.

Both substrates can have a substrate recess, the recesses overlapping in a projection along an axis perpendicular to a main direction of extent of the substrates. In this way there are two entrances for excitation light and ions. The first substrate can have a further recess area on the surface facing the second substrate. This further recess area serves to isolate the upper substrate from the conductor tracks of the lower substrate.

In a peripheral region on the surfaces facing one another, the substrates have bonding connection areas, for example made of Au / Si, Au / Ge, Au / In or Au / Au. This enables the alignment and connection of the two substrates at wafer level, so that small tolerances with regard to rotation and offset result for the electrode arrangement.

As an alternative embodiment, the second substrate can be insulating, for example made of glass, sapphire or similar materials, with which the insulation requirements are automatically met.

The electrode metallization can be formed from Au or Pt. No oxidation can occur with these metals, so that no localized surface charges can form.

The electrode metallization can furthermore have an adhesion promoter layer made of Ti, TiW, Cr at least in the area of the supply lines on the insulation area. This improves the adhesion of the electrode metallization. In order to prevent oxidation of the adhesion promoter layer in the transfer area of the recess, the adhesion promoter layer is removed there in one embodiment before the electrode metallization is applied.

The electrode metallization can consist of several layers of Au or Pt and thin intermediate layers of another conductive material, e.g. Ti / Au / Ti / Au / Ti / Au in the isolation area and Au / Ti / Au / Ti / Au in the recess area. By designing the electrode metallization as a multilayer stack, a layer stress gradient can be counteracted.

The three-dimensional ion trap device can include a third substrate with a third layer of electrodes on a third substrate. This represents a further implementation possibility with a Paul trap, whereby in this configuration two DC cap electrodes and one ring-shaped HF electrode are required.

The second substrate protrudes beyond the first substrate in at least one main direction of extent, with contact areas being provided for the electrodes. In this way, both chips can advantageously be contacted from one side, for example with wire bonds.

To further prevent stray charges from occurring on the side walls of the substrate recess, the side walls can be coated with a further conductive layer, for example Au or Pt.

The ion trap presented can be used for quantum computers or quantum sensors.

Claims (10)

Method for producing a three-dimensional ion trap (10, 100, 200) with the following steps: - providing a first substrate (20, 120, 220, 304) and a second substrate (22, 122, 222, 306), - Forming an isolation region (34, 36, 134, 250, 252, 254, 310, 312) on a first surface of at least one of the substrates (20, 22, 120, 122, 220, 222, 304, 306), - Applying and structuring a metallization (38, 138, 260, 320) on both substrates (20, 22, 120, 122, 220, 222, 304, 306), - Forming bonding areas on mutually facing sides of the substrates (20, 22, 120, 122, 220, 222, 304, 306), - Forming a continuous recess (26, 28, 126, 230, 232) in the at least one substrate (20, 22, 120, 122, 220, 222, 304, 306) on which the insulation area (34, 36, 134, 250, 252, 254, 310, 312) is formed, - Removal of the isolation area (34, 36, 134, 250, 252, 310, 312) in the area of the recess of the at least one substrate (20, 22, 120, 122, 220, 222, 304, 306) on which the isolation area ( 34, 36, 134, 250, 252, 310, 312) is formed, - Connecting the two substrates (20, 22, 120, 122, 220, 222, 304, 306) by a bonding process. Procedure according to Claim 1 wherein the second substrate (22, 122, 222, 306) is formed as an insulating lower substrate. Procedure according to Claim 1 wherein a third substrate (224) is formed and then bonded to the second substrate (22, 122, 222, 306). Method according to one of the Claims 1 to 3 , in which the insulation area (34, 36, 134, 250, 252, 254, 310, 312) is formed by the following steps: Trench etching of pillars, filling with an insulating filling material, opening of a sacrificial layer etching access and sacrificial layer etching of substrate material. Procedure according to Claim 4 , in which the insulation area (34, 36, 134, 250, 252, 254, 310, 312) is closed with a cover layer. Method according to one of the Claims 1 to 5 , in which, in a final step, covered bond pads on the second substrate (22, 122, 222, 306) and possibly the third substrate (224) are exposed. Method according to one of the Claims 1 to 6th , in which a further recess (30, 130, 240, 242) is formed adjacent to the recess. Ion trap with - at least two substrates (20, 22, 120, 122, 220, 222, 304, 306) arranged one above the other, at least one of which is conductive, - electrodes which are placed on the at least two substrates (20, 22, 120, 122 , 220, 222, 304, 306) are provided, - a continuous substrate recess formed in the first conductive substrate (20, 120, 220, 304) with conductive side walls, the electrodes protruding beyond the substrate recess and an insulation area being arranged in sections between the electrode metallization and the conductive substrate, at least in the area of the conductor tracks. Ion trap after Claim 8 , in which the insulation area has a thickness of 5 to 100 µm. Ion trap after Claim 8 or 9 , in which the insulation area (34, 36, 134, 250, 252, 254, 310, 312) is formed by a bridge structure of pillars and a cover layer over a cavity.

Images