DE102009027321A1 - Method for producing electrical interlayer connection in substrate of micro-component or sensor, involves opening mask layer over substrate area provided for electrical interlayer connection, where mask layer is applied on substrate - Google Patents

Abstract

The method involves opening a mask layer over a substrate area provided for the electrical interlayer connection. The mask layer is applied on the substrate (10). A through-hole is generated in the substrate area and an electrical interlayer connection is inserted in the through-hole. The mask layer partially remains in the area of the through-hole during opening of the mask layer, generation of the through-hole and insertion of the electrical interlayer connection. An independent claim is also included for a substrate with an opening recess.

Description

The The invention relates to a method for producing an electrical Via in a substrate and a substrate with a electrical via. Furthermore, the invention relates to a microcomponent or a sensor with such a substrate.

State of the art

electrical Through-holes through a substrate or through a partial area A substrate is available in different embodiments. aim is it about, one as possible small via with a low electrical resistance to realize. To achieve this, often becomes a narrow through hole created with a nearly vertical wall in the respective substrate (Trenchen, Laser, etc.), the wall electrically insulated and then the through hole wholly or partly with a metal or a metal alloy filled, to the desired to achieve low electrical resistance.

Method, with which metals deposited in a deep through hole can be consuming. One for this usable electroplating is expensive and is used by manufacturers of micromechanical Components for contamination reasons bought reluctantly.

It In particular, it is difficult to fully complete such a narrow through hole to fill a metal or a metal alloy. For this reason will be often only the side walls or the side wall of the through hole with the metal or the Metal alloy occupied. Through a remaining opening on a surface of the Substrate in the area of the through hole arise difficulties in a subsequent structuring of the metal or the metal alloy. Classic paint processes with positive or negative coatings are not possible. As well are spray paint processes due to a sharp edge in the through hole area and due to a preferred high aspect ratio of deep through-hole to achieve a high packing density, not applicable. This also applies to further processing steps, if z. B. on a rewiring or passivation level the substrate should be applied.

task

It It is an object of the invention to provide an improved method of manufacturing specify an electrical feedthrough in a substrate. This should be possible in particular be, a through hole for the electrical feedthrough on the one hand only on the side wall or side walls with an electrically conductive Layer on the other hand ensure that the through hole after or during the manufacture of the electrical feedthrough can be closed or is. A closure of the through hole should be approximate be a plan. Furthermore, a simple to set up, reliable and inexpensive to produce electrical via be provided.

Disclosure of the invention

The The object of the invention is achieved by a method for producing a electrical via in a substrate according to claim 1 and a substrate with an electrical feedthrough according to claim 7 solved. Advantageous developments of the invention will become apparent from the dependent Claims.

According to the invention is a produced electrical via in a substrate in which a mask layer deposited on the substrate over one for the electrical via provided area of the substrate opened, one Through hole in the for generates the electrical via provided region of the substrate and the electrical feedthrough introduced into the through hole becomes. When opening the Mask layer, creating the through hole and introducing the electrical Through-hole, the mask layer remains partially in Area of the through hole. This structured mask layer becomes then from the electrical via or a passivation layer locked.

According to the invention the mask layer does not become in the entire diameter range as in the prior art of the through hole to be inserted above the substrate, but it remains in the production of the through hole z. B. a fine structure or a grid over the substrate. At a Deposition of metallic layers in the production of electrical Through-hole is not just a metallic layer on one Sidewall applied in the through hole, but it becomes simultaneously also the structure or the grid covered with metal. According to the invention either so much metal deposited that the structure or the Grid completely is closed, or it follows after the metal deposition one further deposition, z. B. a TEOS deposition, which then to a complete closure the passage yoke leads.

Care must be taken here that the mask layer remaining in the through hole with the metallic layer deposited thereon and the optional TEOS layer does not tend to weaken to move considerably out of a clamping plane. This can happen when the deposited layer system is under a high compressive stress, which adversely affects subsequent process steps and membrane stability. When depositing the layers, care must therefore be taken to set a favorable overall stress of the layer system. It ideally moves in the light pressure (> approx. -150 to -100 MPa) into the light to medium tensile stress range (<approx. 400 to 500 MPa).

chronologically after introducing the through-hole into the substrate and over time prior to making the electrical via in the via, is still an electrical on / in the side wall of the through hole Insulation layer providable; However, this is only necessary if the substrate consists of an electrically conductive material. in this connection is also the structure or the grid with the additional Insulation layer provided.

According to the invention is the mask layer present in the region of the through hole on the substrate configured to make material contact with the mask layer outside has the through hole. Here, the electrical insulation layer in the diameter region of the through-hole through-holes and webs, a hole or slot grid, a screening, such. B. a meandering Rasterung, exhibit.

It is according to the invention a method for producing an electrical feedthrough in a substrate or a substrate with an electrical via presented, which is a wall coating of a through hole the substrate with a conductive Material allowed while allowing the through hole to be provided with a substantially planar or planar closure. This inventive type of electrical through-hole has advantages of an open electrical via - namely a simple, fast and cheap Manufacturability at an increased reliability when introducing the electrical feedthrough, wherein the wall coating z. B. with a metal, for. B. made with common CVD method can be. Different thermal expansion coefficients between metal and silicon as a preferred material for the substrate, can due to low layer thicknesses and thus better expansion possibilities the wall coating can be easily compensated. On the other hand advantages of a completely filled electric Through connection - z. B. at least one simple sequential process that take place on a flat surface can.

Brief description of the figures

The Invention will be described below with reference to exemplary embodiments with reference on the attached Drawing closer explained. In the drawing show:

1 & 2 each in a two-dimensional side sectional view of an embodiment of an electrical feedthrough in a wafer, according to the prior art;

3 - 9 in each case in a two-dimensional lateral sectional view proceeding process steps for introducing an inventive electrical feedthrough into a wafer; and

10 - 13 in each case a two-dimensional plan view of a diameter range of the electrical through-connection according to the invention to be introduced into the wafer, immediately after opening an electrical insulation layer arranged on a substrate of the wafer.

Embodiments of the invention

in the The term wafer is not meant to be just the term substrate but also the production / production thereof electronic / electromechanical components, electrical conductors u. Ä. Here For example, the wafer may be a substrate only for a single microcomponent such as z. B. a sensor, in particular a motor vehicle sensor, such as z. As an acceleration sensor, make available. When used of the invention to a wafer for Sensors, the wafer z. B. be a sensor wafer. Furthermore, can the wafer is a cap wafer or a wafer stack of a plurality of wafers. A material for the substrate of the wafer may be silicon, gallium, indium or glass, silicon-based wafers are preferred.

1 and 2 show conventional embodiments of an electrical feedthrough in a wafer, wherein 1 a via with completely filled through hole and 2 a via in which only the sidewalls of the via are occupied. Hereinafter, embodiments of the method according to the invention and the electrical feedthrough according to the invention will be described with reference to FIGS 3 to 13 compared to the conventional vias, as in 1 and 2 are shown, explained in more detail.

In 3 is a wafer 1 shown on one side 12 a substrate 10 - below as a base 12 denotes - one on an electrical insulation layer 20 located, electrically conductive layer 30 having. The one on the bottom 12 of the wafer 1 existing electrical insulation layer 20 has z. As SiO _x , Si _x N _y or Si _x O _y N _z , and preferably as a conductor track 30 formed electrically conductive layer 30 preferably has a metal, a metal alloy, conductively doped silicon or a polysilicon layer. The electrical insulation layer 20 can z. B. deposited as a TEOS layer. In one area of one in the wafer 1 to be introduced electrical feedthrough 71 (please refer 7 - 9 ) is the electrical insulation layer 20 on the bottom 12 of the wafer 1 except in this area the electrically conductive layer 30 preferably directly on the substrate 10 is arranged.

On one of the bottom 12 opposite side 11 of the substrate 10 - in the following as the top 11 designated - is on the substrate 10 first a hard mask 50 from a dielectric, so an electrical insulation layer, applied, which together with the provision or forming the electrical insulation layer 20 on the bottom 12 and preferably also has SiO _x , Si _x N _y or Si _x O _y N _z . For this purpose, z. B. in turn a TEOS layer are deposited. Advantageously, the electrical insulation layer 50 a layer with tensile stress, as such an electrical insulation layer 50 in the following process steps has no tendency to sag. But also by a suitable choice of a thickness of the electrical insulation layer 50 a deflection can be avoided. Likewise, you can work with a layer stack. So z. B. a Si _x N _y layer are surrounded with a tensile stress on both sides with a TEOS layer, wherein at least one upper TEOS layer can be under a compressive stress in order to make an adjustment of a total layer stress can. Due to a low etch rate of a TEOS layer in a later following trench step, an etching attack on the Si _x N _y layer can be further avoided.

In a range of a later electrical feedthrough 71 of the wafer 1 becomes the applied electrical insulation layer 50 open. Here are in an openable diameter range 54 one in the wafer 1 to be introduced through hole 13 (please refer 4 - 9 ) for the electrical feedthrough 71 , consciously z. B. narrow webs 52 in the electrical insulation layer 50 ditched. Ie. it arises in the diameter range 54 of the through hole 13 alternating bridges 52 the electrical insulation layer 50 and passageways 51 in the electrical insulation layer 50 (please refer 10 ).

It can, for. As well as a grid, such as. B. a hole (see 11 ) or slot grid, or other suitable pattern. The bridges 52 whose diameter or dimensions z. B. may be constant or variable, characterized in that they always connect to an edge of the partially opened diameter range 54 to have. Become the webs 52 Undercut in a subsequent process step, they continue to remain with the electrical insulation layer 50 the non-plated through areas of the wafer 1 connected. Comes with an electrical insulation layer 50 worked, the pressure stress, it may prove favorable, the webs 52 to arrange such that the pressure stress by a bending of the webs 52 in a plane of the electrical insulation layer 50 is compensated. With a meandering pattern (see 12 ) one can so z. B. arching of the webs 52 effectively prevent.

The opened electrical insulation layer 50 in the diameter range 54 of the through hole to be produced 13 is hereafter referred to as a mask 51 . 52 used for an anisotropic trench process, what in the 4 is shown. In this case, process parameters for etching and passivation steps are selected such that it is directly under the mask 51 . 52 or only at a certain distance below the mask 51 . 52 to a partial or complete undercut of the bars 52 the mask 51 . 52 comes. The undercut of the bars 52 can also take place in a process step following the trench process. Initially, the passivation layer formed during trenching is removed. Subsequently, with a possible isotropic etching process, for. Using SF ₆ , ClF ₃ , XeF ₂ or other suitable gases extending below the lands 52 the mask 51 . 52 located walls, in particular the silicon walls removed.

This process is driven as far as to the electrically to be contacted trace 30 or electrical contact surface 30 is reached. For some applications, it may prove beneficial on the bottom 12 of the substrate 10 to provide one or more dielectric layers as an etch stop. In a further step, such a layer must be opened by a suitable etching step. This then creates the through hole 13 which extends through the electrical insulation layer 50 and the substrate 10 up to the electrically conductive layer 30 extends, wherein in a longitudinal end portion 53 of the through hole 13 the electrical insulation layer 50 still partially available.

The following will be, see 5 through the mask 51 . 52 the electrical insulation layer 50 through, a side wall 14 or the side walls 14 of the through hole 13 , z. B. by a TEOS deposition, electrically isolated. Ent stands next to a sidewall passivation 60 of the through hole 13 an additional electrical insulation layer 60 on the electrical insulation layer 50 , which are also all around the bars 52 the mask 51 . 52 and on a floor 15 of the through hole 13 located. The electrical insulation layer 60 may in turn have SiO _x , Si _x N _y or Si _x O _y N _z . Shooting, see 6 , with an anisotropic etching process through-holes 61 in the electrical insulation layer 60 on the ground 15 of the through hole 13 to the conductor to be contacted 30 or electrical contact surface 30 created something in 6 is shown. Optionally, a diffusion barrier and / or an adhesive layer is then deposited.

In a next, in 7 illustrated process step, is preferably a metal 70 in the through hole 13 and at least partially on the electrical insulation layer 60 deposited (electrically conductive layer 70 ). Preferred for this purpose are CVD methods, since with such methods metals 70 can be deposited compliantly. It may additionally prove to be beneficial, the electrically conductive layer 70 deposit in several steps and make back sputtering steps in between. The mask 51 . 52 is due to the deposition of the metal 70 gradually overgrown. The sputtering steps may cause the mask to grow 51 . 52 be partially withdrawn. The released metal 70 is mostly in the through hole 13 separated again. By these back sputtering steps may also be aware of a thickness of the electrically conductive layer 70 be reduced at the surface. Instead of a metal 70 can also be a metal alloy 70 or conductive doped silicon 70 or a polysilicon layer 70 as an electrically conductive layer 70 be applied.

A closure of the mask 51 . 52 can either directly through the deposition of the metal 70 , please refer 8th , or by the deposition of a passivation layer. The use of one or more passivation layers for masking the mask 51 . 52 can also be used advantageously to a layer stress of the self-supporting structure of the remaining electrical insulation layer 50 in the diameter range 54 for the through hole 13 to optimize or minimize, so as to achieve a high reliability. A structuring, see 9 , the electrically conductive layer 70 on the surface of the wafer 1 , the manufacture and structuring of another wiring or Passivierungsebene or a contact surface for further processing of the wafer 1 , can according to the invention on the now almost planar surface of the wafer 1 done with conventional methods of semiconductor technology.

An alternative processing (not shown in the drawing) takes place for. B. as follows. First, the through hole 10 trimmed and the side walls 14 passivated. Thereafter, an optional diffusion barrier and the metallization will become 70 deposited and subsequently the mask 51 . 52 Missed. There are then contact holes from the bottom 12 in the area of the through hole 13 with a stop on the metallization 70 in the through hole 13 created. Only now is the conductive layer 30 on bottom 12 deposited and structured, wherein an electrical contact of the metal 30 with the metal 70 in the through hole 13 is made within the contact holes. In contrast to the embodiment already described, the metallization takes place here 30 only after the closure of the through hole 13 , The advantage of such an embodiment is not on the ground 15 of the through hole 13 a contact between metal 70 and metal 30 to have to produce, but this easier by means of contact holes from the bottom 12 to do.

Alternatively to the deposition of the metal 70 may also preferably doped silicon 70 as an electrically conductive layer 70 be used. For some applications, this may be advantageous, especially if first the electrical feedthrough 71 should be created and only after that time CMOS structures or MEMS structures in / on the wafer 1 should be generated. polysilicon layers 70 guarantee a low risk of contamination, allow processes at high temperatures and are easy to integrate into existing manufacturing. There are various variants for the production of the polysilicon layer 70 and the closure of the through-hole 13 conceivable. So z. B.

secrete and closure with one or more doped or, e.g. B. over a Occupancy, separately doped polysilicon layers. Or separating one or more, doped or, e.g. B over an occupancy, separately doped polysilicon layers and closure with an oxide layer. Respectively. Depositing an undoped / endowed / subsequently endowed Polysilicon starting layer, thickening and closure over a epitaxially deposited polysilicon layer. Or z. B. deposition an undoped / doped / post-doped polysilicon seed layer, Thickening over Epitaxially deposited polysilicon and closure with a Oxide layer.

The last two of the four mentioned embodiments are preferred embodiments, in particular if epitaxial layers are necessary for subsequent steps or processes. These can simultaneously with an epilayer in the electrical feedthrough 71 to be raised. Is about an anisotropic etching step prior to deposition removes a polysilicon seed layer on the surface, may be on the surface of the wafer 1 monocrystalline silicon grown. The polysilicon starter layer can be highly doped via an occupancy. Since this layer is selectively removable on the surface via an anisotropic etching step, it can be achieved that on the surface of the wafer 1 grows a lightly doped epilayer, as required for typical CMOS processes. At the same time, the high doping of the starting layer in the electrical feedthrough achieves this 71 the high, desired electrical conductivity of the silicon layers in this area.

The thicknesses of the electrical insulation layers 50 . 60 are preferably 0.5-10 .mu.m, in particular 5-10 .mu.m, more preferably 2-4 .mu.m and particularly particularly preferably 1-2 microns. In such a range are preferably the widths of the webs 52 and or the through-holes 51 the mask 51 . 52 from the electrical insulation layer 50 or the electrical insulation layers 50 . 60 , Furthermore, these widths can also be two, three or four times the widths mentioned. Further shows 13 another embodiment of a mask 51 . 52 These are a circular and the diameter range 54 for the through hole 13 concentric bridge 52 which has four bars 52 with the electrical insulation layer 50 outside the diameter range 54 is materially formed in one piece, that is in material contact. In principle, the shape or the pattern of the mask 51 . 52 as desired and may vary depending on an application, so have a correspondingly advantageous shape.

Claims (11)

Method for producing an electrical feedthrough ( 71 ) in a substrate ( 10 ), wherein a mask layer applied to the substrate ( 50 ) over an area provided for the electrical feedthrough ( 54 ) of the substrate ( 10 ), a through hole ( 13 ) in the area provided for the electrical feedthrough ( 54 ) of the substrate ( 10 ), and the electrical feedthrough ( 71 ) in the through hole ( 13 ) is introduced, characterized in that when opening the mask layer ( 50 ), Creating the through-hole ( 13 ) and introducing the electrical feedthrough ( 71 ) the mask layer ( 50 ) in that area ( 54 ) of the through hole ( 13 ) partially remains. A method according to claim 1, characterized in that after the creation of the through-hole ( 13 ) and before the electrical feedthrough ( 71 ) in the through hole ( 13 ) on the side wall ( 14 ) of the through hole ( 13 ) an electrical insulation layer ( 60 ) is applied. Method according to claim 1 or 2, characterized in that in the region ( 54 ) of the through hole ( 13 ) remaining mask layer ( 50 ) Through holes ( 51 ) and bridges ( 52 ), a hole or slot grid ( 51 . 52 ) and / or a screening ( 51 . 52 ) having. Method according to one of claims 1 to 3, characterized in that in the area ( 54 ) of the through hole ( 13 ) remaining mask layer ( 50 ) from the electrical feedthrough ( 71 ) is closed. Method according to one of claims 1 to 3, characterized in that in the area ( 54 ) of the through hole ( 13 ) remaining mask layer ( 50 ) is closed by an additionally applied passivation layer. Method according to one of claims 1 to 5, characterized in that the mask layer applied to the substrate ( 50 ) is subjected in a compressive or tensile stress. Substrate ( 10 ) with an electrical feedthrough ( 71 ), whereby in one through the substrate ( 10 ) through hole (FIG. 13 ) the electrical feedthrough ( 71 ), which two sides ( 11 . 12 ) of the substrate ( 10 ) electrically conductively connected, characterized in that in the area ( 54 ) of the through hole ( 13 ) with the electrical feedthrough ( 71 ) a structured mask layer ( 60 ) of the electrical feedthrough ( 71 ) or a passivation layer is closed. Substrate according to Claim 7, characterized in that the structured mask layer ( 60 ) Through holes ( 51 ) and bridges ( 52 ), a hole or slot grid ( 51 . 52 ) and / or a screening ( 51 . 52 ) having. Substrate according to claim 7 or 8, characterized in that the electrical feedthrough ( 71 ) on a side wall ( 14 ) of the through hole ( 13 ) is provided. Substrate according to claim 9, characterized in that between the electrical feedthrough ( 71 ) and the side wall ( 14 ) of the through hole ( 13 ) an electrical insulation layer ( 60 ) is provided. Microcomponent or sensor with a substrate ( 10 ) according to one of claims 7 to 10.

Images