DE102010039180B4 - Method for producing semiconductor chips and corresponding semiconductor chip - Google Patents

Abstract

Method for producing semiconductor chips with the following steps:
Providing an assembly of a wafer substrate (10), a first layer (12) of an insulating material on the wafer substrate (10), and a layer (14) of single crystal silicon on the first insulating layer (12);
Patterning the layer (14) of monocrystalline silicon and the underlying first layer (12) of the insulating material such that both layers (12, 14) remain in a defined lateral area (16), thereby forming a block (17);
Forming a buried layer (20) of conductive material in lateral regions of the assembly outside the defined lateral region (16);
Depositing a start layer (26) of polycrystalline silicon on lateral areas of the arrangement outside the defined lateral area (16);
epitaxially depositing silicon on the monocrystalline silicon layer (14) and on the polycrystalline silicon start layer (26), thereby forming an epitaxially deposited silicon layer (31) having laterally adjacent single crystalline and polycrystalline regions;
wherein the epitaxially deposited layer (31) is patterned of silicon to form functional regions;
wherein in structuring the epitaxially deposited layer (31) in a region (28) made of monocrystalline silicon, a spring (36) of a micromechanical structure consisting entirely of monocrystalline silicon connected to a movable element (38) is formed single crystal and polycrystalline silicon; and
Exposing the spring (36) and the movable member (38) by means of a gas phase etching process such that the movable member (38) is on one side of the spring (36) is suspended, wherein the spring (36) is coupled on the other side with the wafer substrate (10).

Description

The present invention relates to a method for producing semiconductor chips and a corresponding semiconductor chip.

The DE 10 2008 040 851 A1 discloses a method of making semiconductor chips wherein a silicon layer is epitaxially grown simultaneously on a layer of single crystal silicon and on a polycrystalline silicon start layer.

State of the art

Various methods are known with which layers of monocrystalline silicon can be provided on a layer of insulating material (Silicon On Insulator SOI). These are used to make electronic components or electromechanical microstructures (MEMS). However, when using SOI substrates, pads, traces, and electrodes must be placed above the circuits or micromechanical structures.

Furthermore, the production of polycrystalline micromechanical structures is known. In this case, a polycrystalline silicon starting layer is deposited on an oxide layer, which is thickened by an epitaxial deposition. By means of suitable process control, contact surfaces, interconnects and electrodes can be integrated under the micromechanical structures. This is for example in the DE 195 37 814 A1 described.

1. [1] „A micromachining technique for a thin silicon membrane using merged epitaxial lateral overgrowth of silicon and SiO2 for an etch-stop‟, James J. Pak, Abul E. Kabir, Gerold W. Nedeck, James H. Logsdon, David R. DeRoo and Steven E. Staller, TRANSDUCERS '91, 1991 International Conference on Solid-State Sensors and Actuators, Digest of Technical Papers (Cat. No.91CH2817-5), San Francisco, CA, USA, 24-27 June 1991 / 1991 / 4160016.
2. [2] „Automatic etch stop on buried oxide using epitaxial lateral overgrowth‟, Gennisen P.T.J., Bartek M., French P.J., Sarro P.M., Wolffenbuttel R.F., Proceedings of the International Solid-State Sensors and Actuators Conference - TRANSDUCERS '95; Stockholm, Sweden, 25-29 June 1995 / 1995 / 5248250 CA Conference Paper (C)
3. [3] „A new epitaxial lateral overgrowth silicon bipolar transistor‟, Gerold W. Neudeck, IEEE Electron Device Letters, Vol. EDL-8, No. 10, October 1987

In addition, it is known that oxide layers can be monocrystalline overgrown by means of an epitaxial deposition of laterally adjacent monocrystalline regions. This is described, for example, in the following publications [1], [2] and [3]:

1. [1] "A micromachining technique for a thin silicon membrane using a merged epitaxial lateral overgrowth of silicon and SiO 2 for an etch-stop", James J. Pak, Abul E. Kabir, Gerold W. Nedeck, James H. Logsdon, David R. DeRoo and Steven E. Staller, TRANSDUCERS '91, 1991 International Conference on Solid-State Sensors and Actuators, Digest of Technical Papers (Cat. No. 91CH2817-5), San Francisco, CA, USA, 24-27 June 1991/1991/4160016 ,
2. [2] "Automatic etch stop on buried oxide using epitaxial lateral overgrowth", Gennisen PTJ, Bartek M., French PJ, Sarro PM, Wolffenbuttel RF, Proceedings of the International Solid-State Sensors and Actuators Conference - TRANSDUCERS '95; Stockholm, Sweden, 25-29 June 1995/1995/5248250 CA Conference Paper (C)
3. [3] "A new epitaxial lateral overgrowth silicon bipolar transistor", Gerold W. Neudeck, IEEE Electron Device Letters, Vol. EDL-8, no. 10, October 1987

Disclosure of the invention

The method according to the invention for producing semiconductor chips according to claim 1 and the semiconductor chip obtainable by such a method according to claim 6 provide silicon layers with mixed monocrystalline and polycrystalline regions, wherein contact surfaces, interconnects and electrodes can be arranged under the polycrystalline regions.

The present invention is based on a SOI wafer with a thin, monocrystalline layer. The monocrystalline layer is partially removed and allowed to stand only in a defined range. In the areas in which the monocrystalline layer has been removed, a buried conductive layer is applied, over which a polysilicon starter layer is applied. Subsequently, silicon is grown in an epitaxial deposition. In this case, monocrystalline silicon is accordingly grown in the monocrystalline regions, while in the polycrystalline regions corresponding to the substrate polycrystalline silicon is grown. With this method, there are no restrictions in the size or in the lateral lead to adjacent functional structures when creating the monocrystalline regions. Thus, several monocrystalline structures can be arranged close to each other. The monocrystalline regions can be arranged arbitrarily within functional structures, so that known layouts can be adopted with almost no change. In addition, in this method, an epitaxial process can be used, which is very robust and fast and therefore inexpensive.

In the dependent claims are advantageous developments and improvements of the respective subject of the invention.

According to a preferred embodiment of the invention, the surface of the layer of monocrystalline silicon is arranged higher than the surface of the starting layer of polycrystalline silicon before the epitaxial deposition and / or the monocrystalline silicon has a surface orientation in the 100 direction. With such an arrangement, monocrystalline growth dominates over polycrystalline growth because the 100-direction is the fast growth direction in the standard epitaxy process. By simultaneously selecting the layer structure such that the monocrystalline silicon layer is arranged higher than before the epitaxy process the polycrystalline starting layer, the monocrystalline growth process in the 100 direction will always have a height advantage in front of the polycrystalline growth front. In general, under these conditions, below 54 °, an interface between the monocrystalline and the polycrystalline region, ie along the slow growth direction, will form. With these measures, it is possible to produce particularly large monocrystalline regions.

According to a preferred embodiment of the invention, the application of a buried layer of conductive material comprises the following substeps: removal of the first layer of insulating material in the regions of the arrangement outside the defined range; Forming a second layer of insulating material over the entire surface of the assembly; Depositing and doping a layer of polycrystalline silicon on the entire surface of the second layer of insulating material; Patterning the layer of polycrystalline silicon so that it is removed at least from the defined area; Forming a third layer of insulating material over the entire surface of the assembly; and removing the second and third layers of insulating material in the defined area.

The second and third layers of insulating material are preferably each an oxide layer, which is produced either by thermal oxidation of the exposed silicon layers or, for example, by chemical vapor deposition of tetraethyl orthosilicate (TEOS-LPCVD) at low pressure. The removal of the layers of insulating material in the defined area is preferably carried out after the starting layer of polycrystalline silicon has been applied to the entire surface of the arrangement and then removed again in the defined area.

Preferably, the third layer of insulating material is patterned prior to deposition of the polycrystalline silicon seed layer to provide contact areas.

According to the invention, the epitaxially deposited layer is also patterned to form functional regions, which is preferably done by means of an anisotropic etching process, also called trench process. The functional areas may be either circuits of electronic components or electromechanical microstructures as used in sensors. Previously, the epitaxially deposited layer can be planarized by chemical mechanical polishing.

According to the invention, when structuring the epitaxial layer in a region consisting of monocrystalline silicon, a spring of a micromechanical structure is formed. For such springs, it is desirable that they lie only in monocrystalline regions. As a result, the offset scattering which occurs in the case of polycrystalline material due to the stochastic distribution of the monocrystalline regions and their transition regions occurring stresses and makes more and more noticeable with ever smaller components, can be drastically reduced.

To expose the spring, the layers of insulating material are preferably partially removed by means of a gas phase etching process. To this end, in patterning the epitaxial layer, additional holes are formed in the epitaxial layer at a distance smaller than the undercutting degree to allow access to the layers to be etched.

Preferred embodiments and advantages of the method according to the invention also apply correspondingly to the semiconductor chip according to the invention.

list of figures

Embodiments of the invention are illustrated in the drawings and explained in more detail in the following description.

• 1 ein erstes Stadium der Herstellung einer Ausführungsform eines erfindungsgemäßen Halbleiterchips in Querschnittsansicht;
• 2 ein zweites Stadium der Herstellung der Ausführungsform eines erfindungsgemäßen Halbleiterchips in Querschnittsansicht;
• 3 ein drittes Stadium der Herstellung der Ausführungsform eines erfindungsgemäßen Halbleiterchips in Querschnittsansicht;
• 4 ein viertes Stadium der Herstellung der Ausführungsform eines erfindungsgemäßen Halbleiterchips in Querschnittsansicht;
• 5 ein fünftes Stadium der Herstellung der Ausführungsform eines erfindungsgemäßen Halbleiterchips in Querschnittsansicht;
• 6 ein sechstes Stadium der Herstellung der Ausführungsform eines erfindungsgemäßen Halbleiterchips in Querschnittsansicht;
• 7 ein siebtes Stadium der Herstellung der Ausführungsform eines erfindungsgemäßen Halbleiterchips in Querschnittsansicht;
• 8 ein achtes Stadium der Herstellung der Ausführungsform eines erfindungsgemäßen Halbleiterchips in Querschnittsansicht;
• 9 ein neuntes Stadium der Herstellung der Ausführungsform eines erfindungsgemäßen Halbleiterchips in Querschnittsansicht;
• 10 ein zehntes Stadium der Herstellung der Ausführungsform eines erfindungsgemäßen Halbleiterchips in Querschnittsansicht;
• 11 ein elftes Stadium der Herstellung der Ausführungsform eines erfindungsgemäßen Halbleiterchips in Querschnittsansicht;
• 12a, b ein zwölftes Stadium der Herstellung der Ausführungsform eines erfindungsgemäßen Halbleiterchips in Draufsicht und in Querschnittsansicht; und
• 13a, b ein dreizehntes Stadium der Herstellung der Ausführungsform eines erfindungsgemäßen Halbleiterchips in Draufsicht und in Querschnittsansicht.

Show it:

• 1 a first stage of manufacturing an embodiment of a semiconductor chip according to the invention in cross-sectional view;
• 2 a second stage of the production of the embodiment of a semiconductor chip according to the invention in cross-sectional view;
• 3 a third stage of the production of the embodiment of a semiconductor chip according to the invention in cross-sectional view;
• 4 a fourth stage of manufacturing the embodiment of a semiconductor chip according to the invention in cross-sectional view;
• 5 a fifth stage of the production of the embodiment of a semiconductor chip according to the invention in cross-sectional view;
• 6 a sixth stage of manufacturing the embodiment of a semiconductor chip according to the invention in cross-sectional view;
• 7 a seventh stage of manufacturing the embodiment of a semiconductor chip according to the invention in cross-sectional view;
• 8th an eighth stage of manufacturing the embodiment of a semiconductor chip according to the invention in cross-sectional view;
• 9 a ninth stage of manufacturing the embodiment of a semiconductor chip according to the invention in cross-sectional view;
• 10 a tenth stage of manufacturing the embodiment of a semiconductor chip according to the invention in cross-sectional view;
• 11 an eleventh stage of manufacturing the embodiment of a semiconductor chip according to the invention in cross-sectional view;
• 12a, b a twelfth stage of manufacturing the embodiment of a semiconductor chip according to the invention in plan view and in cross-sectional view; and
• 13a, b a thirteenth stage of the production of the embodiment of a semiconductor chip according to the invention in plan view and in cross-sectional view.

Embodiments of the invention

1 FIG. 12 is a cross-sectional view of an SOI substrate constituting the initial stage of the manufacturing process according to a preferred embodiment of the present invention. FIG.

The SOI substrate comprises a silicon wafer 10 with an oxide layer 12 on the wafer surface and a thin layer 14 of monocrystalline silicon on the surface of the oxide layer 12 ,

2 is a cross-sectional view of a second process stage of the manufacturing method according to the preferred embodiment of the invention.

According to the preferred embodiment, both the thin monocrystalline silicon layer 14 as well as the underlying oxide layer 12 removed in subregions, leaving both layers only in a defined lateral area 16 stop, creating a block 17 is formed.

3 FIG. 12 is a cross-sectional view of a third process stage of the manufacturing process according to the preferred embodiment of the invention. FIG.

After structuring the two layers 12 and 14 becomes an oxide layer 18 deposited on the entire surface of the device. This is done either by thermal oxidation of the two exposed silicon layers or, for example, by chemical vapor deposition of tetraethyl orthosilicate at low pressure (TEOS-LPCVD).

4 FIG. 12 is a cross-sectional view of a fourth process stage of the manufacturing process according to the preferred embodiment of the invention. FIG.

On the surface of the oxide layer 18 For example, a layer is created to apply a buried trace or electrode 20 deposited from polycrystalline silicon. This polysilicon layer 20 is doped to be conductive.

5 FIG. 12 is a cross-sectional view of a fifth process stage of the manufacturing method according to the preferred embodiment of the invention. FIG.

In the defined lateral area 16 and optionally from the side walls of the block 17 the polycrystalline silicon is removed again. In this step, at the same time, the polysilicon layer 20 to form the buried trace and an electrode.

6 FIG. 12 is a cross-sectional view of a sixth process stage of the manufacturing method according to the preferred embodiment of the invention. FIG.

After removal of the polysilicon, an oxide layer is formed again 22 deposited on the surface of the device so that the polysilicon layer 20 and the block 17 are covered. This oxide layer 22 essentially serves as a sacrificial layer in the further process. Its thickness defines the distance between the buried interconnect or electrode and a functional layer added in the further process.

7 FIG. 10 is a cross-sectional view of a seventh process stage of the manufacturing process according to the preferred embodiment of the invention. FIG.

In the oxide layer 22 become contact areas 24 etched, which serve to establish an electrically conductive connection between the buried conductor track and the functional layer.

8th FIG. 12 is a cross-sectional view of an eighth process stage of the manufacturing process according to the preferred embodiment of the invention. FIG.

After creating the contact areas 24 the deposition of another layer takes place 26 polycrystalline silicon over the entire surface of the device, that is, the polysilicon layer 26 covers the oxide layer 22 as well as the contact areas 24 ,

The polysilicon layer 26 serves as a starting layer for an epitaxial growth of silicon.

9 FIG. 12 is a cross-sectional view of a ninth process stage of the manufacturing method according to the preferred embodiment of the invention. FIG.

After deposition, the polysilicon layer becomes 26 structured, wherein the polysilicon from the defined lateral area 16 and from the side walls of the block 17 Will get removed.

10 FIG. 10 is a cross-sectional view of a tenth process stage of the manufacturing method according to the preferred embodiment of the invention. FIG.

After removal of the polysilicon, the oxide also becomes in the defined lateral region 16 so far removed that the layer 14 is exposed from single crystal silicon, that is, the surface and sidewalls of the block 17 are removed until the layer 14 comes to light. In 10 it can be seen that the surface of the layer 14 of monocrystalline silicon in the arrangement is higher than the remaining parts of the layer 26 made of polycrystalline silicon. As a result, the monocrystalline growth process following in the next step has a height advantage in front of the polycrystalline growth front. In addition, according to the preferred embodiment of the invention for the layer 14 single crystalline silicon with a surface orientation in 100 Direction, since this is the fast growth direction in the standard epitaxy process. At the next step, in the silicon epitaxially on the starting layer 26 made of polycrystalline silicon and on the layer 14 is deposited from single-crystal silicon, therefore dominates the monocrystalline growth over the polycrystalline growth, so that forms an interface between the resulting regions of monocrystalline silicon and polycrystalline silicon of the epitaxially grown layer below 54 ° to the horizontal.

11 FIG. 12 is a cross-sectional view of an eleventh process stage of the manufacturing process according to the preferred embodiment of the invention, which is the monocrystalline region. FIG 28 and the polycrystalline region 30 the epitaxially grown layer 31 shows.

The epitaxially grown layer 31 forms the functional layer of the semiconductor chip to be produced. In 11 it can be seen that the area 28 made of monocrystalline silicon becomes wider towards the top. After deposition, the layer becomes 31 planarized from epitaxially grown silicon by chemical-mechanical polishing.

12a and b are views of a twelfth process stage of the manufacturing process according to the preferred embodiment of the invention.

12a FIG. 12 is a plan view of the arrangement after patterning the epitaxially grown silicon layer. FIG 31 , The structuring takes place by means of an anisotropic etching process, also called the trench process. In this case, on the one hand in the monocrystalline region 28 a feather 36 educated. On the other hand, a ditch 32 and holes 34 designed for a later gas phase etching process. The ditch 32 also serves to separate a movable element 38 which has both monocrystalline silicon and polycrystalline silicon. The distance of the holes 34 is chosen to be less than a set undercutting degree. If, for example, an undercutting degree of 10 μm is set, then the distance of the holes from each other and from the trench must be 32 be smaller than 10 microns, so that in the following Gasphasenätzprozesse the entire sacrificial layer under the holes 34 Will get removed.

12b is a cross section through the arrangement along the dashed line of 12a ,

13a and FIG. 8b are views of a thirteenth process stage of the manufacturing process according to the preferred embodiment of the invention.

13a is a plan view of the resulting according to the preferred embodiment of the invention arrangement. It shows a microstructure with a spring 36 and one with the spring 36 connected movable element 38 which holes 34 having. The feather 36 consists entirely of monocrystalline silicon, while the movable element 38 comprises both monocrystalline and polycrystalline silicon.

13b is a cross section along the dashed line in FIG 13a , It shows the result of the gas phase etching process, in which the oxide layer 22 and a part of the oxide layer 18 and the rest of the oxide layer 12 were removed, causing the spring 36 and the movable element 38 were exposed, so that the movable element 38 at the spring 36 hung on the other side with the substrate 10 is coupled. The part of the conductive layer 20 that is under the moving element 38 is, serves as an electrode and is, as well as the movable element 38 , contacted via the buried interconnect and through the oxide layer 18 from the wafer substrate 10 electrically isolated.

The present invention has been explained using the example of a free-standing MEMS structure with a spring and a movable element. Such a MEMS structure can be used for all acceleration and rotation rate sensors. The invention is not limited to such MEMS structures, but also applicable to other electronic components, for the functional structures of monocrystalline silicon regions are advantageous.

Claims (7)

Method for producing semiconductor chips with the following steps: Providing an assembly of a wafer substrate (10), a first layer (12) of an insulating material on the wafer substrate (10), and a layer (14) of single crystal silicon on the first insulating layer (12); Patterning the layer (14) of monocrystalline silicon and the underlying first layer (12) of the insulating material such that both layers (12, 14) remain in a defined lateral area (16), thereby forming a block (17); Forming a buried layer (20) of conductive material in lateral regions of the assembly outside the defined lateral region (16); Depositing a start layer (26) of polycrystalline silicon on lateral areas of the arrangement outside the defined lateral area (16); epitaxially depositing silicon on the monocrystalline silicon layer (14) and on the polycrystalline silicon start layer (26), thereby forming an epitaxially deposited silicon layer (31) having laterally adjacent single crystalline and polycrystalline regions; wherein the epitaxially deposited layer (31) is patterned of silicon to form functional regions; wherein in structuring the epitaxially deposited layer (31) in a region (28) made of monocrystalline silicon, a spring (36) of a micromechanical structure consisting entirely of monocrystalline silicon connected to a movable element (38) is formed single crystal and polycrystalline silicon; and Exposing the spring (36) and the movable member (38) by means of a gas phase etching process such that the movable member (38) is suspended on one side of the spring (36), the spring (36) on the other side being in contact with the wafer substrate (38). 10) is coupled. Method according to Claim 1 wherein the surface of the monocrystalline silicon layer (14) prior to epitaxial deposition is higher than the surface of the polycrystalline silicon start layer (26) and / or the monocrystalline silicon has a 100 direction surface orientation. Method according to Claim 1 or 2 wherein applying the buried layer (20) of conductive material comprises the substeps of: removing the first layer (12) of insulating material in the regions of the assembly outside the defined region (16); Forming a second layer (18) of insulating material over the entire surface of the assembly; Depositing and doping the layer (20) of polycrystalline silicon on the entire surface of the second layer (18) of insulating material; Patterning the polycrystalline silicon layer (20) so as to be removed at least from the defined region (16); Forming a third layer (22) of insulating material over the entire surface of the assembly; and removing the second and third layers (18, 22) of insulating material in the defined lateral region (16). Method according to Claim 3 wherein before applying the polycrystalline silicon starting layer (26), the third layer (22) of insulating material is patterned to provide contact regions (24). Method according to Claim 3 or 4 wherein the layers (12, 18, 22) of insulating material are at least partially removed by the gas phase etching process. Semiconductor chip with a wafer substrate (10); a silicon layer (31); and a patterned layer (20) of conductive material having at least one recess between the wafer substrate (10) and the silicon layer (31); in which the silicon layer (31) in a region (28) made of monocrystalline silicon comprises a spring (36) made entirely of monocrystalline silicon connected to a movable element (38) comprising monocrystalline and polycrystalline silicon; and the spring (36) and the movable member (38) are exposed such that the movable member (38) is suspended on one side of the spring (36) and the spring (36) on the other side is coupled to the wafer substrate (10) is. Semiconductor chip after Claim 6 , characterized in that the lateral single-crystal region (28) widens with increasing distance from the wafer substrate (10).

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