DE102019110021A1 - Electronic circuit for a differential amplifier with at least four inputs - Google Patents

Abstract

An electrical circuit (100) for an analog, complementary differential amplifier with two or more inverting and non-inverting inputs each, comprising: two differential input stages (110) with six terminals (111, 112, 113, 114, 115, 116), comprising: a first and a second n-transistor connection (140) each with three connections (141, 142, 143), a first and second p-transistor connection (150) with three connections (151, 152, 153); four resistor circuits (180) each with two connections (181, 182); a negative and a positive voltage supply (-Ub, + Ub); a first and a second constant current source (160, 170) each having two connections (161, 162, 171, 172); four inputs (E1, E2, E3, E4); four outputs (A1, A2, A3, A4); a three terminal p-current mirror (120) (121, 122, 123); and an n-current mirror (130) with three terminals (131, 132, 133).

Description

The invention relates to an electronic circuit of an analog, complementary differential amplifier. Such a circuit according to the invention forms an analog, complementary differential amplifier, each with two or more inverting and non-inverting inputs. It is used in the input stage of a complementary amplifier circuit and makes it possible to replace the classic complementary differential amplifier with a single inverting and non-inverting input. The possible uses of such an amplifier circuit are thus expanded to include many areas of application for which a plurality of separate amplifiers was previously required.

Such a circuit according to the invention makes it possible to use a single amplifier circuit to simultaneously sample a plurality of analog voltage signals with high impedance, to add up the input voltages at the non-inverting inputs and to subtract the sum of the input voltages at the inverting inputs therefrom. The resulting difference signal can be tapped non-inverted and inverted by the circuit and amplified. With such a circuit according to the invention, it is possible to implement or provide one or more differential amplifiers whose performance data, such as signal propagation time, bandwidth and maximum steepness of the output signal, are hardly influenced negatively regardless of the number of inputs.

The following formula (1) applies to the transfer equation of a common amplifier (e.g. operational amplifier) with an ordinary differential amplifier as input stage, with one inverting and one non-inverting input and the no-load gain V ₀ : $${\text{U}}_{\text{Out}}=\left({\text{U}}_{+\text{One}}-{\text{U}}_{-\text{One}}\right)\cdot {\text{V}}_0$$

When using a differential amplifier according to the invention, which functions as an input stage of an amplifier, with two inverting and two non-inverting inputs, the transfer equation changes to formula (2): $${\text{U}}_{\text{Out}}=\left({\text{U}}_{+\text{One}1}+{\text{U}}_{+\text{One}2}-{\text{U}}_{-\text{One}1}-{\text{U}}_{-\text{One}2}\right)\cdot {\text{V}}_0$$

Correspondingly, when using a differential amplifier according to the invention, which acts as an input stage of an amplifier, with N (here N ∈ ℕ, ie N = 1, 2, 3, ...) inverting and N non-inverting inputs, the following formula (3) follows as the transfer equation for the amplifier circuit: $${\text{U}}_{\text{Out}}=\left({\text{U}}_{+\text{One}1}+{\text{U}}_{+\text{One}2}+...+{\text{U}}_{+\text{AN}}-{\text{U}}_{-\text{One}1}-{\text{u}}_{-\text{One}2}-...-{\text{U}}_{-\text{AN}}\right)\cdot {\text{V}}_0$$

State of the art

1. 1) Der Differenzverstärker stellt den invertierenden- und den nichtinvertierenden Eingang zur Verfügung. Er verstärkt die Differenzspannung zwischen den beiden Eingängen. Der Ausgang des Differenzverstärkers ist mit dem Spannungsverstärker verbunden.
2. 2) Der Spannungsverstärker ist für die hohe Leerlaufverstärkung V₀ des Verstärkers verantwortlich. Sein Ausgang ist mit der Endstufe verbunden.
3. 3) Die Endstufe weist eine hohe Stromverstärkung auf. Der Ausgang der Endstufe bildet den Ausgang der Verstärkerschaltung.

The invention is based on a common analog amplifier circuit. Such an amplifier has a non-inverting and an inverting input and an output. Internally, such an amplifier can be divided into three stages:

1. 1) The differential amplifier provides the inverting and the non-inverting input. It amplifies the differential voltage between the two inputs. The output of the differential amplifier is connected to the voltage amplifier.
2. 2) The voltage amplifier is responsible for the high open circuit gain V _{0 of} the amplifier. Its output is connected to the output stage.
3. 3) The output stage has a high current gain. The output of the output stage forms the output of the amplifier circuit.

• Um ein analoges Spannungssignal um einen bestimmten Faktor zu verstärken, kann ein Verstärker entweder nichtinvertierend oder invertierend beschaltet werden, siehe [1], S. 510.

The invention was initially developed to solve the following basic circuit problem:

• In order to amplify an analog voltage signal by a certain factor, an amplifier can be wired either non-inverting or inverting, see [1], p. 510.

At the non-inverting amplifier, the input of the amplifier circuit has a high input impedance, which is in the range of about 500 kilo ohms and about 10 mega ohms. In the case of an inverting amplifier, however, the input of the amplifier circuit has a low input impedance in a range from approximately 500 ohms to approximately 100 kiloohms, since both the input signal and the inverted signal of the negative feedback must be connected to the same inverting input of the amplifier. Due to the potential difference, a compensating current flows between the input and the output of the inverting amplifier circuit when it is modulated. This puts stress on the signal source, which can lead to distortion.

• • Den Strom der Gegenkopplung senken, was aber zu Nichtlinearität und Instabilität der Schaltung führen kann.
• • Einen Impedanzwandler vor den Eingang der invertierenden Verstärkerschaltung vorschalten. Dies hat einen negativen Einfluss auf die Bandbreite, die Flankensteilheit, das Rauschverhalten und die Signallaufzeit der Gesamtschaltung.
• • Eine Instrumentenverstärkerschaltung anstatt einer gewöhnlichen Verstärkerschaltung verwenden. Bei dieser Schaltung ist die Gegenkopplung von den beiden Eingängen getrennt, wodurch die Schaltung auch bei invertierendem Betrieb einen hochohmigen Eingang aufweist. Ein Instrumentenverstärker ist intern aus zwei oder drei einzelnen Verstärkern aufgebaut, wodurch sie eine niedrigere Bandbreite und Flankensteilheit sowie eine höhere Signallaufzeit aufweisen.

Conventional approaches are, for example:

• • Reduce the negative feedback current, but this can lead to non-linearity and instability of the circuit.
• • Connect an impedance converter upstream of the input of the inverting amplifier circuit. This has a negative influence on the bandwidth, the edge steepness, the noise behavior and the signal delay of the overall circuit.
• • Use an instrumentation amplifier circuit instead of an ordinary amplifier circuit. In this circuit, the negative feedback is separated from the two inputs, which means that the circuit has a high-resistance input even in inverting operation. An instrumentation amplifier is built up internally from two or three individual amplifiers, which means that they have a lower bandwidth and slope as well as a longer signal delay.

All of these approaches to solving this circuit-related problem thus lead to a number of disadvantages, such as a reduced bandwidth, a reduced edge steepness, or an increased signal propagation time and an increased component cost of the circuit. It is therefore not possible with the current state of the art to produce an inverting amplifier with the same performance data as a non-inverting amplifier.

The font DE 32 32 442 A1 describes an amplifier circuit which is monolithically integrated on a semiconductor chip and is composed of two separate amplifiers. This circuit has two non-inverting inputs, but no inverting input. The purpose of this circuit is to automatically offset the output voltage. To do this, one of the two inputs is connected to the desired reference potential. This document differs significantly from the circuit described here, since it is made up of two separate amplifiers and does not provide any inverting inputs.

The font U.S. 4,780,630 describes the structure of a differential amplifier with four independent inputs. The circuit disclosed has two distinct goals. On the one hand, it should allow the formation of the sum and difference of four signals via the four inputs. In the second application, an input pair consisting of an inverting and a non-inverting input is used as the differential amplifier input of the circuit. The second input pair is used solely to compensate for the offset voltage. This document differs significantly from the circuit described herein. On the one hand by its structure: The font reveals a constant current source and four paths. The circuit according to the invention developed uses a complementary structure, each with two constant current sources and two paths. An inverting circuit is not possible with the circuit from this document, for example, and would only deliver a strongly distorted output signal. This means that the four inputs of this circuit cannot be wired as universally as the invention mentioned. The document also gives no indication of how an expansion of the differential amplifier to six or more inputs is to be formed.

This invention is based on the objective technical problem of providing a differential amplifier which enables an inverting amplifier circuit which has the same performance data in terms of high input impedance, bandwidth, edge steepness and signal propagation time as a non-inverting amplifier circuit.

This objectively technical problem mentioned above is achieved with the method disclosed herein according to the subject matter of the first independent claim 1. Related secondary claims or subclaims reproduce advantageous configurations or embodiments. Advantageous developments, which can be implemented individually or in any combination, are presented in the dependent claims.

In the following, the terms “have”, “comprise” or “include” or any grammatical deviations therefrom are used in a non-exclusive manner. Accordingly, these terms can refer to situations in which, besides the features introduced by these terms, no further features are present, or to situations in which one or more other features are present. For example, the expression "A has B", "A comprises B" or "A includes B" can refer to the situation in which, apart from B, there is no other element in A (i.e. a situation in which A consists exclusively of B), as well as the situation in which, in addition to B, one or more further elements are present in A, for example element C, elements C and D or even further elements.

Furthermore, it should be noted that the terms “at least one” and “one or more” as well as grammatical modifications of these terms, if these are used in connection with one or more elements or features and are intended to express that the element or feature is provided once or several times can be used, as a rule, only once, for example when the feature or element is introduced for the first time. If the feature or element is subsequently mentioned again, the corresponding term “at least one” or “one or more” is generally no longer used, without restricting the possibility that the feature or element can be provided once or several times.

Furthermore, the terms “preferably”, “in particular”, “for example (for example)” or similar terms are used below in connection with optional features, without this limiting alternative embodiments. Features introduced by these terms are optional features, and it is not intended to use these features to restrict the scope of protection of the claims and in particular of the independent claims. Thus, as the person skilled in the art will recognize, the invention can also be carried out using other configurations. In a similar way, features which are introduced by “in one embodiment” or by “in a further embodiment” are understood as optional features, without this being intended to restrict alternative configurations or the scope of protection of the independent claims. Furthermore, by means of these introductory expressions, all possibilities of combining features introduced in this way with other features, be it optional or non-optional features, remain untouched.

general description

In order to achieve the above-mentioned problem, a new type of differential amplifier for use in complementary analog amplifier circuits has been developed. This developed circuit concept has two to N inverting and non-inverting inputs, where N represents an element of the natural numbers. Here, all inverting and all non-inverting inputs have equal rights and can be freely wired, like the only inverting and only non-inverting input in a common differential amplifier. All inputs are high-impedance, the term high-impedance here being understood to mean an impedance that is in a range from approximately 500 kiloohms to 10 megohms, and thus approximately independent of one another. Such an amplifier with four inputs, ie two inverting and two non-inverting inputs, makes it possible to implement an inverting amplifier circuit with a high input impedance and the same performance data as a non-inverting amplifier from a single amplifier. For this purpose, the negative feedback signal is connected to one of the two inverting inputs and the input signal to the other inverting input, instead of both being connected to the same inverting input. The summation of the input and negative feedback signals is carried out separately from the input signals in the differential amplifier. The high input impedance of the amplifier results in approximately the same high input impedance as a non-inverting amplifier. Since the invention describes an expansion of a complementary differential amplifier connected in parallel, it does not lead to any effective deterioration in the bandwidth, the edge steepness or the signal propagation time, with only a slightly increased component cost. The implementation of such an amplifier with four inputs and the properties mentioned requires a complementary amplifier structure, as listed in [2], for example. Such a circuit is used especially for amplifiers with a high edge steepness. The differential amplifier of such a complementary amplifier is expanded by two additional inputs in that a further path with input transistors and emitter resistors is connected in parallel to the existing input transistors with emitter resistors. The collector currents of the input transistors add up via the common current mirror and thus effectively also the input signals. For this summation, currents must be applied in the differential amplifier which are decoupled from the inputs due to the high current gain of the input transistors. In order to increase the input impedance of the differential amplifier further, it is possible to replace the input transistors with Darlington or Sziklai circuits ([1], p.178). To expand the differential amplifier to 6 inputs, input transistors with emitter resistors are again added according to the same scheme. According to this scheme, the number of inputs can be expanded by any number of multiples of 2. A higher number of inputs causes a slight increase in the Background noise and power consumption. In addition, no negative influences are known. Further embodiments of circuits according to the invention have bipolar transistors. The circuit concept can, however, also be applied to field effect transistors. The two current mirrors of the circuit can be replaced by any complex current mirror shapes. The constant current sources of the circuit concept can be implemented in any form.

In a first embodiment, an electrical circuit according to the invention for a complementary differential amplifier comprises: two differential input stages with a first connection, a second connection, a third connection, a fourth connection, a fifth connection and a sixth connection, comprising: a first n-transistor connection with a first connection, a second connection and a third connection, the third connection of the first n-transistor interconnection being electrically conductively connected to the first connection of the differential input stages; a first p-transistor connection, with a first connection, a second connection and a third connection, the third connection of the first p-transistor connection being electrically conductively connected to the third connection of the differential input stages, and the second connection of the first n-transistor connection being connected to is electrically conductively connected to the second connection of the first p-transistor connection and to the fifth connection of the differential input stages; a second n-transistor connection, with a first connection, a second connection and a third connection, the third connection of the second n-transistor connection being electrically conductively connected to the second connection of the differential input stages; a second p-transistor connection, with a first connection, a second connection and a third connection, the third connection of the second p-transistor connection being electrically conductively connected to the fourth connection of the differential input stages, and the second connection of the second n-transistor connection being connected to is electrically conductively connected to the second connection of the second p-transistor connection and to the sixth connection of the differential input stages; four resistor connections, each with a first connection and a second connection, the first connection being the first resistor connection is electrically conductively connected to the first connection of the first n-transistor interconnection, the second connection of the second resistor interconnection being electrically conductively connected to the first connection of the second n-transistor interconnection, the first connection of the third resistor interconnection with the first connection of the first p- Transistor interconnection is electrically conductively connected, and wherein the second terminal of the fourth resistor interconnection is electrically conductively connected to the first connection of the second p-transistor interconnection; a negative voltage supply set up in such a way that a negative electrical voltage can be provided and a positive voltage supply set up in such a way that a positive electrical voltage can be provided; a first constant current source, set up in such a way that an electric current can be provided, with a first connection and a second connection, the first connection of the first constant current source being connected in an electrically conductive manner to the second connection of the first resistance circuit and the first connection of the second resistance circuit, and wherein the second terminal of the first constant current source is electrically conductively connected to the negative voltage supply; and a second constant current source, set up in such a way that an electrical current can be provided, with a first connection and a second connection, the first connection of the second constant current source being connected in an electrically conductive manner to the second connection of the third resistance circuit and the first connection of the fourth resistance circuit, and wherein the second terminal of the second constant current source is electrically conductively connected to the positive voltage supply; a first input, a second input, a third input and a fourth input, each of the inputs being set up such that an electrical signal can be passed through each of the inputs, the first input being electrically conductive with the fifth connection of the first differential input stage is connected, the second input being electrically conductively connected to the sixth connection of the first differential input stage, the third input being electrically conductively connected to the fifth connection of the second differential input stage, and wherein the fourth input is electrically conductively connected to the sixth connection of the second differential input stage is; a first output, a second output, a third output and a fourth output, each of the outputs being set up such that an electrical signal can be passed through each of the outputs, the first output being connected to the first connection of the first and second differential input stage is electrically conductively connected, the second output being electrically conductively connected to the third connection of the first and second differential input stage, the third output being electrically conductively connected to the second connection of the first and second differential input stage, and the fourth output being connected to the fourth connection the first and second differential input stage is electrically conductively connected; a p-current mirror with a first connection, a second connection and a third connection, wherein the first connection is electrically conductively connected to the positive voltage supply, wherein the second connection is electrically conductive with the third output and with the second connection of the first and second differential input stage is connected, and wherein the third connection is electrically conductively connected to the first output and to the first connection of the first and second differential input stage; and an n-current mirror with a first connection, a second connection and a third connection, the first connection being electrically conductively connected to the negative voltage supply, the second connection being electrically connected to the second output and to the third connection of the first and second differential input stage is conductively connected, and wherein the third terminal is electrically conductively connected to the fourth output and to the fourth terminal of the first and second differential input stage. The first embodiment represents a complementary differential amplifier with two inverting and two non-inverting inputs. Compared to a complementary differential amplifier according to the prior art, this embodiment has two additional, freely connectable inputs. This expands the application possibilities of an amplifier equipped with it and also enables the construction of an inverting amplifier with high input impedance, high bandwidth, high maximum edge steepness, with low running time.

In a further, second embodiment of an electrical circuit according to the invention based on the first embodiment, the n-transistor interconnection of the differential input stages is each formed by means of an n-transistor with a first connection, a second connection and a third connection, the first connection of the n -Transistor interconnection is electrically conductively connected to the first connection of the n-transistor, the second connection of the n-transistor interconnection is electrically conductively connected to the second connection of the n-transistor, and the third connection of the n-transistor interconnection to the third connection of the n-transistor is electrically conductively connected; and wherein the p-transistor interconnection of the differential input stages is each formed by means of a p-transistor each with a first connection, a second connection and a third connection, the first connection of the p-transistor connection being electrically conductively connected to the first connection of the p-transistor wherein the second connection of the p-transistor interconnection is electrically conductively connected to the second connection of the p-transistor, and wherein the third connection of the p-transistor interconnection is electrically conductively connected to the third connection of the p-transistor. This second embodiment with individual input transistors ensures a lower input impedance of the circuit, with a shorter running time and a higher bandwidth compared to the third and fourth embodiments.

In a further, third embodiment of an electrical circuit according to the invention based on the first embodiment, the n-transistor interconnection of the differential input stages is each composed of a Darlington circuit, comprising a first n-transistor and a second n-transistor, each with a first connection and a second connection and a third connection, wherein the first connection of the first n-transistor is electrically conductively connected to the second connection of the second n-transistor, wherein the first connection of the n-transistor connection is electrically conductively connected to the first connection of the second n-transistor wherein the second connection of the n-transistor connection is electrically conductively connected to the second connection of the first n-transistor, and wherein the third connection of the n-transistor connection is electrically conductive with the third connection of the first n-transistor and the second n-transistor connected is t; and wherein the p-transistor interconnection of the differential input stages is each formed from a Darlington circuit comprising a first p-transistor and a second p-transistor, each with a first connection, a second connection and a third connection, the first connection of the first p -Transistor is electrically conductively connected to the second connection of the second p-transistor, wherein the first connection of the p-transistor interconnection is electrically conductively connected to the first connection of the second p-transistor, the second connection of the p-transistor interconnection with the second connection of the first p-transistor is connected in an electrically conductive manner, and wherein the third connection of the p-transistor interconnection is in each case connected in an electrically conductive manner to the third connection of the first p-transistor and the second p-transistor. This third embodiment with Darlington circuits at the input of the differential amplifier ensures a higher input impedance of the circuit with an increased transit time and a smaller bandwidth compared to the second embodiment.

In a further, fourth embodiment of an electrical circuit according to the invention based on the first embodiment, the n-transistor connection of the differential input stages is each composed of a Sziklai circuit comprising an n-transistor, each with a first connection, a second connection and a third connection, and a p-transistor, each with a first connection, a second connection and a third connection, the third connection of the n-transistor being connected in an electrically conductive manner to the second connection of the p-transistor, the first connection of the n-transistor interconnection with the first connection of the n-transistor and the third connection of the p-transistor is electrically conductively connected, the second connection of the n-transistor interconnection being electrically conductively connected to the second connection of the n-transistor, and the third connection of the n-transistor interconnection with the first connection of the p- Transistor is electrically conductively connected; and wherein the p-transistor interconnection of the differential input stages each consists of a Sziklai circuit comprising a p-transistor, each with a first connection, a second connection and a third connection, and an n-transistor, each with a first connection, a second connection and a third connection is formed, wherein the third connection of the p-transistor is electrically conductively connected to the second connection of the n-transistor, the first connection of the p-transistor interconnection with the first connection of the p-transistor and the third connection of the n -Transistor is electrically conductively connected, wherein the second connection of the p-transistor interconnection is electrically conductively connected to the second connection of the p-transistor, and wherein the third connection of the p-transistor interconnection is electrically conductively connected to the first connection of the n-transistor. This fourth embodiment with Sziklai circuits at the input of the differential amplifier ensures a higher input impedance of the circuit with an increased transit time and a smaller bandwidth compared to the second embodiment. The performance data are comparable to the third embodiment.

In a further, fifth embodiment of an electrical circuit according to the invention, based on one of the preceding, second to fourth embodiments, the p-current mirror, comprising a first p-transistor and a second p-transistor, each with a first connection, a second connection and a third connection, the first connection of the p-current mirror being electrically conductively connected to the first connection of the first p-transistor and the second p-transistor, the second connection of the p-current mirror being connected to the third connection of the second p Transistor and is electrically conductively connected to the second terminal of the first p-transistor and the second p-transistor, and wherein the third terminal of the p-current mirror is electrically conductively connected to the third terminal of the first p-transistor; and wherein the n-current mirror, comprising a first n-transistor and a second n-transistor, each with a first connection, a second connection and a third connection, is formed, the first connection of the n-current mirror being connected to the first connection of the first n-transistor and second n-transistor is electrically conductively connected, the second connection of the n-current mirror being electrically conductively connected to the third connection of the first n-transistor, and the third connection of the n-current mirror being connected to the third connection of the second n-transistor and is electrically conductively connected to the second connection of the first n-transistor and the second n-transistor. The use of current mirrors with two transistors leads to a reduced number of components compared to the following sixth and seventh embodiments.

In a further, sixth embodiment of an electrical circuit according to the invention based on one of the preceding, second to fourth embodiments, the p-current mirror is composed of a first p-transistor, a second p-transistor and a third p-transistor, each with a first connection, a second connection and a third connection, the second connection of the first p-transistor and the second p-transistor being electrically conductively connected to the first connection of the third p-transistor, the third connection of the third p-transistor being connected to the negative voltage supply is electrically conductively connected, the first connection of the p-current mirror being electrically conductively connected to the first connection of the first p-transistor and the second p-transistor, the second connection of the p-current mirror being connected to the second connection of the third p-transistor and the third connection of the second p-transistor is electrically conductively connected, and wherein the third connection of the p-current mirror is electrically conductively connected to the third connection of the first p-transistor; and wherein the n-current mirror is formed from a first n-transistor, a second n-transistor and a third n-transistor, each with a first connection, a second connection and a third connection, the second connection of the first n -Transistor and the second n-transistor are electrically conductively connected to the first connection of the third n-transistor, the third connection of the third n-transistor being electrically conductively connected to the positive voltage supply, the first connection of the n-current mirror with each the first connection of the first n-transistor and the second n-transistor is electrically conductively connected, the second connection of the n-current mirror being electrically conductively connected to the third connection of the first n-transistor, and the third connection of the n-current mirror to the second connection of the third n-transistor and the third connection of the second n-transistor electrically lei is efficiently connected. The use of 3-transistor current mirrors leads to improved linearity and common-mode rejection of the differential amplifier compared to the previous embodiment.

In a further, seventh embodiment of an electrical circuit according to the invention, based on one of the preceding, second to fourth embodiments, the p-current mirror is composed of a first p-transistor, a second p-transistor, a third p-transistor and a fourth p-transistor , each with a first connection, a second connection and a third connection, the second connection of the third p-transistor and fourth p-transistor, with the first connection of the second p-transistor and the third connection of the fourth p- Transistor are electrically conductively connected, the first terminal of the first p-transistor is electrically conductively connected to the third terminal of the third p-transistor, the second terminal of the first p-transistor, with the second terminal of the second p-transistor with the third connection of the second p-transistor and the second connection of the p-current mirror are electrically conductive is connected, the first connection of the p-current mirror being electrically conductively connected to the first connection of the third p-transistor and fourth p-transistor, and the third connection of the p-current mirror being electrically connected to the third connection of the first p-transistor is conductively connected; and wherein the n-current mirror is formed from a first n-transistor, a second n-transistor, a third n-transistor and a fourth n-transistor, each with a first connection, a second connection and a third connection, the second in each case Connection of the third n-transistor and fourth n-transistor are electrically conductively connected to the first connection of the second n-transistor and the third connection of the fourth n-transistor, the first connection of the first n-transistor and the third connection of the third n-transistor is electrically conductively connected, the second connection of the first n-transistor being connected in an electrically conductive manner to the second connection of the second n-transistor, to the third connection of the second n-transistor and the third connection of the n-current mirror, wherein the first connection of the n-current mirror is electrically connected to the first connection of the third n-transistor and fourth n-transistor is connected t capable, and wherein the second connection of the n-current mirror is electrically conductively connected to the third connection of the first n-transistor. The use of cascaded current mirrors leads to a linearity and common mode rejection of the differential amplifier comparable to the sixth embodiment. In contrast to the sixth embodiment, no additional electrically conductive connection to one of the operating voltages is required.

In a further embodiment of an electrical circuit according to the invention, based on one of the fifth to seventh embodiments, the number of differential input stages is extended to any number N greater than two and the number of inputs is extended to a number of 2N, with a running variable x (here x ∈ ℕ and 1 ≤ x ≤ N), where N represents a natural number, where x represents a natural number in the range from 1 to N, the first connections of all differential input stages with one another, with the third connection of the p-current mirror and with the first Output of the electrical circuit are electrically conductively connected, the second connections of all differential input stages being connected to each other, to the second connection of the p-current mirror and to the third output of the electrical circuit, the third connections of all differential input stages being connected to each other, to the second connection of the n-current mirror and are electrically conductively connected to the second output of the electrical circuit, the fourth connections of all differential input stages being electrically conductively connected to one another, to the third connection of the n-current mirror and to the fourth output of the electrical circuit, each odd-numbered (2x-1 ) -th input is electrically conductively connected to the fifth connection of the x-th differential input stage, and each even-numbered (2x) -th input is electrically conductively connected to the sixth connection of the x-th differential input stage. With this extension it is possible to increase the number of inverting and non-inverting inputs in pairs to any number. Depending on the number selected, there is little influence on the bandwidth, edge steepness and runtime.

In a further embodiment of an electrical circuit according to the invention based on the embodiment described above, N is in a range from 2 to 30.

A typical complementary amplifier structure consisting of differential amplifier, voltage amplifier and output stage is used for the subsequent interconnections or circuits. The circuit according to the invention is used as a differential amplifier for a differential amplifier.

A complementary amplifier provided with a circuit according to the invention can be used as an adder or subtracter with any number of inputs. For this purpose, as with a non-inverting amplifier ([1], p. 510), negative feedback is formed between the output of the amplifier and any inverting input of the amplifier in order to define the gain factor of the circuit. The input signals to be summed are each connected to one of the non-inverting inputs of the amplifier. The input signals to be subtracted are each connected to one of the inverting inputs of the amplifier, with the exception of the inverting input, which is used for negative feedback. The output of the amplifier forms the output of the circuit. Inputs of the amplifier that are not required can be deactivated by connecting them to the zero voltage potential. Due to the high input impedance of the invention, the input signals do not influence one another, which means that a previous impedance conversion of the input signals can be dispensed with.

A complementary amplifier with four inputs provided with a circuit according to the invention can be used as an instrumentation amplifier. For this purpose, as with a non-inverting amplifier ([1], p. 510), negative feedback is formed between the output of the amplifier and any inverting input of the amplifier in order to define the gain factor of the circuit. One of the non-inverting inputs can be used as a connection for the reference voltage. The remaining pair of inverting and non-inverting inputs of the amplifier serves as the differential input of the instrumentation amplifier. The output of the amplifier forms the output of the instrumentation amplifier. In contrast to ordinary instrumentation amplifiers, which are built up internally from two or three amplifier circuits, this instrumentation amplifier consists of a single amplifier. In addition to the reduced component costs, this results in a higher bandwidth, edge steepness and a reduced signal propagation time. This represents a significant improvement compared to the previous circuit concepts.

A complementary amplifier provided with a circuit according to the invention enables an averaging of any number of input signals, e.g. to be carried out by several sensor signals. For this purpose, all input signals are each connected to a non-inverting input of the amplifier and the same number of inverting inputs of the amplifier to the output of the amplifier. The output of the amplifier forms the output of the circuit. Inputs that are not required can be deactivated by connecting them to the zero voltage potential. Due to the multiple negative feedback, the sum of all input voltages is divided by the number of input voltages, which corresponds to a mean value formation. The advantage of this circuit lies in the high input impedance of the inputs, the high bandwidth, the steep edge steepness and the short transit time, which corresponds to a single amplifier.

A complementary amplifier provided with a circuit according to the invention makes it possible to detect deviations in an input signal for any even number 2N of input signals, e.g. with several sensor signals. For this purpose, as with a non-inverting amplifier ([1], p. 510), negative feedback is formed between the output of the amplifier and any inverting input of the amplifier in order to define the gain factor of the circuit. N input signals are each connected to an inverting input of the amplifier and the remaining N input signals are each connected to a non-inverting input of the amplifier. The output of the amplifier forms the output of the circuit. Inputs that are not required can be deactivated by connecting them to the zero voltage potential. Such a circuit sums up the N input signals at the non-inverting inputs of the amplifier and subtracts therefrom the sum of the N input signals at the inverting inputs of the amplifier. The resulting difference signal is amplified by the amplification factor of the amplifier. If all input signals are identical, the output voltage of the circuit is 0V. If one of the input signals deviates from the others, this results in an output voltage not equal to 0V. Such a circuit can, for example, be used on the input side in parallel with an averaging unit in order to be able to detect a sensor defect at an early stage. Due to the high input impedance of the circuit, the input signals are hardly influenced and a sensor defect can be detected in the run time of an individual amplifier.

A complementary amplifier provided with a circuit according to the invention can also be used in the field of analog computing for mathematical operations. With any number of high-resistance inputs, several input variables can be sampled, added and subtracted at the same time. By using logarithmizers, it is also possible to carry out multiplications and divisions. In this area of application, too, the advantage of the circuit concept lies in the high input impedance and bandwidth, the large number of inputs and the associated savings in signal transit time and component costs.

A complementary amplifier with four or more inputs provided with a circuit according to the invention enables several negative and positive feedbacks to be set up in parallel via the independent, inverting and non-inverting inputs. For example, passive filters can be used in the various negative and positive feedback, which do not influence one another due to the high input impedance of the inputs. Each filter stage is connected to the low-impedance output of the amplifier and one of the high-impedance inverting or non-inverting inputs. Since the inputs will hardly load the filter circuits, they can be designed using common filter equations. In this way it is possible to set up any complex active filter with just a single amplifier. Input signals can be connected to both non-inverting and inverting inputs of the amplifier. The output of the amplifier forms the output of the circuit. Inputs that are not required can be deactivated by connecting them to the zero voltage potential.

Here, the term “constant current source” is to be understood as an electrical device which provides a constant output current.

Here, the term “resistor interconnection” is to be understood as an electrical unit or at least one electrical component that exhibits the behavior of an electrical resistance at its connections or provides a previously determinable electrical resistance.

Here, the term “current mirror” is to be understood as an electrical circuit that makes it possible to derive a further current from an existing reference current and thus represents a current-controlled current source.

Here, the term “voltage supply” is to be understood as an electrical unit which provides a previously determinable electrical voltage.

Here, the term “n-transistor connection” is to be understood as an electrical connection that has an equivalent electrical transmission behavior between its three electrical connections, such as an NPN bipolar transistor or an n-field effect transistor.

Here, the term “p-transistor connection” is to be understood as an electrical connection that has an equivalent electrical transmission behavior between its three electrical connections, such as a PNP bipolar transistor or a p-field effect transistor.

The term “n-transistor” here means either an NPN bipolar transistor or an n-field effect transistor, each with three connections. In the case of an NPN bipolar transistor, the first connection is referred to as the emitter, the second connection as the base and the third connection as the collector. In the case of an n-type field effect transistor, the first connection is referred to as the source, the second connection as the gate and the third connection as the drain.

Here, the term “p-transistor” is to be understood as meaning a PNP bipolar transistor or a p-field effect transistor, each with three connections. In the case of a PNP bipolar transistor, the first connection is referred to as the emitter, the second connection as the base and the third connection as the collector. In the case of an n-type field effect transistor, the first connection is referred to as the source, the second connection as the gate and the third connection as the drain.

Here, the term “differential amplifier” is to be understood as an electrical circuit that is located at the input of an amplifier circuit and provides one or more inverting and non-inverting inputs. In a complementary structure, a differential amplifier has two inverting and two non-inverting outputs, which are connected to the inputs of the voltage amplifier. Depending on the common mode rejection, a differential amplifier only amplifies the difference between the input signals.

Here, the term “differential input stage” is to be understood as an electrical connection that is part of a differential amplifier according to the invention and that provides a single inverting input and a single non-inverting input. Two or more of these electrical circuits are part of a differential amplifier according to the invention.

Figure list

Further details and features of the present invention emerge from the following description of a preferred exemplary embodiment, in particular in conjunction with the dependent claims. The respective features can be implemented individually or in combination with one another. The invention is not limited to the exemplary embodiments or forms.

The exemplary embodiments and forms are shown schematically in the following figures. Here, the same reference numerals in the figures denote the same or functionally identical elements or elements that correspond to one another with regard to their functions.

• 1 eine schematische Darstellung einer ersten Ausführungsform einer erfindungsgemäßen elektrischen Schaltung eines komplementären Differenzverstärkers mit 4 Eingängen;
• 2 eine schematische Darstellung einer Ausführungsform einer erfindungsgemäßen Differenzeingangsstufe;
• 3 drei schematische Darstellungen (140a - 140c) einer Ausführungsform einer n-Transistorverschaltung;
• 4 drei schematische Darstellungen (150a - 150c) einer Ausführungsform einer p-Transistorverschaltung;
• 5 drei schematische Darstellungen (120a - 120c) einer Ausführungsform eines p-Stromspiegels;
• 6 drei schematische Darstellungen (130a - 130c) einer Ausführungsform eines n-Stromspiegels;
• 7 eine schematische Darstellung einer zweiten Ausführungsform einer erfindungsgemäßen elektrischen Schaltung eines komplementären Differenzverstärkers mit N-Eingängen

For the purposes of illustration and without restrictive effect, further features and advantages of the invention emerge from the description of the accompanying drawings. Show in it:

• 1 a schematic representation of a first embodiment of an electrical circuit according to the invention of a complementary differential amplifier with 4 inputs;
• 2 a schematic representation of an embodiment of a differential input stage according to the invention;
• 3 three schematic representations ( 140a - 140c ) an embodiment of an n-transistor circuit;
• 4th three schematic representations ( 150a - 150c ) an embodiment of a p-transistor interconnection;
• 5 three schematic representations ( 120a - 120c ) an embodiment of a p-current mirror;
• 6 three schematic representations ( 130a - 130c ) an embodiment of an n-current mirror;
• 7th a schematic representation of a second embodiment of an electrical circuit according to the invention of a complementary differential amplifier with N inputs

Detailed description

1 Figure 3 schematically shows an embodiment of an electrical circuit according to the invention 100 for a complementary differential amplifier according to the subject matter of independent claim 1. As in 1 shown schematically, includes the electrical circuit 100 two differential input stages 110 , a first entrance E1 , a second entrance E2 , a third entrance E3 , a fourth entrance E4 , a first exit A1 , a second exit A2 , a third exit A3 , a fourth exit A4 , a p-current mirror 120 , an n-current mirror 130 , a negative and a positive voltage supply, -Ub and + Ub .

The differential input stages 110 each make a first connection 111 , a second port 112 , a third port 113 , a fourth port 114 , a fifth port 115 and a sixth port 116 ready. The differential input stage is part of a differential amplifier according to the invention and each provides a single inverting and a single non-inverting input.

Two or more of these electrical circuits are part of a differential amplifier according to the invention.

Each of the entrances, E1 , E2 , E3 and E4 , the electrical circuit 100 for a complementary differential amplifier is set up in such a way that each of the inputs, E1 , E2 , E3 and E4 , an electrical signal can be passed through. This is the first entrance E1 is with the fifth connector 115 the first differential input stage 110 , the second entrance E2 with the sixth connection 116 the first differential input stage 110 , the third entrance E3 with the fifth connection 115 the second differential input stage 110 and the fourth entrance E4 with the sixth connection 116 the second differential input stage 110 electrically conductively connected.

Each of the exits, A1 , A2 , A3 and A4 , the electrical circuit 100 for a complementary differential amplifier is set up in such a way that through each of the outputs, A1 , A2 , A3 and A4 , an electrical signal can be passed through. This is the first exit A1 with the first connection 111 the first and second differential input stage 110 , the second exit A2 with the third connection 113 the first and second differential input stage 110 , the third exit A3 with the second connection 112 the first and second differential input stage 110 and the fourth exit A4 with the fourth port 114 the first and second differential input stage 110 electrically conductively connected.

The p-current mirror 120 provides a first connection 121 , a second port 122 and a third port 123 ready. This is the first connection 121 with the positive power supply + Ub , the second port 122 with the third exit A3 and with the second connection 112 the first and second differential input stage 110 and the third connector 123 with the first exit A1 and with the first connection 111 the first and second differential input stage 110 electrically conductively connected.

The n-current mirror 130 provides a first connection 131 , a second port 132 and a third port 133 ready. This is the first connection 131 with the negative power supply -Ub , the second port 132 with the second exit A2 and with the third connection 113 the first and second differential input stage 110 and the third connector 133 with the fourth exit A4 and with the fourth port 114 the first and second differential input stage 110 electrically conductively connected

A current mirror is an electrical circuit that makes it possible to derive a further current from an existing reference current. It thus represents a current-controlled power source.

2 Fig. 3 schematically shows an embodiment of an electrical circuit according to the invention 110 for a differential input stage 110 as in 2 shown schematically, includes the differential input stages 110 a first and a second n-transistor connection 140 , a first and a second p-transistor connection 150 , four resistor connections 180 , a negative and a positive voltage supply, -Ub and + Ub , and a first and second constant current source, 160 and 170 .

The first n-transistor connection 140 provides a first connection 141 , a second port 142 and a third connector 143 ready. Here is the third connection 143 the first n-transistor interconnection 140 with the first connection 111 of the differential input stages 110 electrically conductively connected.

The first p-transistor connection 150 provides an initial connection 151 , a second port 152 and a third port 153 ready. Here are the third connection 153 the first p-transistor connection 150 with the third connection 113 of the differential input stages 110 and the second port 142 the first n-transistor interconnection 140 with the second connection 152 the first p-transistor connection 150 and with the fifth connector 115 of the differential input stages 110 electrically conductively connected.

The second n-transistor connection 140 provides a first connection 141 , a second port 142 and a third port 143 ready. Here is the third port 143 the second n-transistor circuit 140 with the second connection 112 of the differential input stages 110 electrically conductively connected.

The second p-transistor connection 150 provides a first connection 151 , a second port 152 and a third port 153 ready. Here is the third port 153 of the second p-transistor connection 150 with the fourth port 114 of the differential input stages 110 electrically conductively connected. The second connection 142 the second n-transistor circuit 140 is with the second connector 152 of the second p-transistor connection 150 and with the sixth connection 116 of the differential input stages 110 electrically conductively connected.

A p-transistor connection represents an electrical connection that has an equivalent electrical transfer behavior between its three electrical connections such as a PNP bipolar transistor or a p-field effect transistor, and an n-transistor connection an electrical connection that has an equivalent electrical transfer behavior between its has three electrical connections such as an NPN bipolar transistor or an n-type field effect transistor.

The four resistor connections 180 each make a first connection 181 and a second port 182 ready. A resistance circuit represents an electrical unit or at least one electrical component which has the behavior of an electrical resistance at its connections or provides a previously determinable electrical resistance.

This is the first connection 181 the first resistor circuit 180 with the first connection 141 the first n-transistor interconnection 140 , the second port 182 the second resistor circuit 180 with the first connection 141 the second n-transistor circuit 140 , the first connection 181 the third resistor circuit 180 with the first connection 151 the first p-transistor connection 150 and the second port 182 the fourth resistor circuit 180 with the first connection 151 of the second p-transistor connection 150 electrically conductively connected.

The negative power supply -Ub is set up in such a way that a negative electrical voltage can be provided and the positive voltage supply + Ub is set up in such a way that a positive electrical voltage can be provided.

The first constant current source 160 is set up in such a way that an electrical current can be provided and provides a first connection 161 and a second port 162 ready. This is the first connection 161 the first constant current source 160 with the second connection 182 the first resistor circuit 180 and the first connection 181 the second resistor circuit 180 electrically conductively connected. In addition is the second connector 162 the first constant current source 160 with the negative power supply -Ub electrically conductively connected.

The second constant current source 170 is set up in such a way that an electrical current can be provided and a first connection 171 and a second port 172 provides. This is the first connection 171 the second constant current source 170 with the second connection 182 the third resistor circuit 180 and the first connection 181 the fourth resistor circuit 180 electrically conductively connected. In addition is the second connector 172 the second constant current source 170 with the positive power supply + Ub electrically conductively connected.

3 provides three possible schematic forms of performance ( 140a , 140b and 140c ) an electrical circuit according to the invention 140 for an n-transistor connection 140 as in 3 shown schematically, comprises the first embodiment 140a an n-type transistor TN with a first connection TNa , a second port TNb and a third port TNc , the second embodiment 140b comprises first and second n-type transistors TN each with a first connection TNa , a second port TNb and a third port TNc and the third embodiment 140c comprises an n-type transistor with a first terminal TNa , a second port TNb and a third port TNc and a p-type transistor TP with a first connection TPa , a second port TPb and a third port TPc .

It represents an n-transistor TN either an NPN bipolar transistor or an n-field effect transistor, each with three connections. The first connection in an NPN bipolar transistor TNa as an emitter, the second connection TNb as the base and the third connection TNc referred to as a collector. In the case of an n-type field effect transistor, the first connection is TNa as source, the second connection TNb as the gate and the third connection TNc referred to as the drain.

It represents a p-transistor TP a PNP bipolar transistor or a p-field effect transistor, each with three connections. The first connection in a PNP bipolar transistor TPa as an emitter, the second connection TPb as the base and the third connection TPc referred to as a collector. In the case of an n-type field effect transistor, the first connection is TPa as source, the second connection TPb as the gate and the third connection TPc referred to as the drain.

In the first embodiment 140a is the first connection TNa of the n-transistor TN with the first connection 141 the n-transistor interconnection 140a , the second port TNb of the n-transistor TN with the second connection 142 the n-transistor interconnection 140a and the third connector TNc of the n-transistor TN with the third connection 143 the n-transistor interconnection 140a electrically conductively connected.

In the second embodiment 140b is the first connection TNa of the first n-transistor TN with the second connection TNb of the second n-transistor TN and the first connection TNa of the second n-transistor TN with the first connection 141 the n-transistor interconnection 140b electrically conductively connected. The third connection 143 the n-transistor interconnection 140b is with the third connection TNc of the first and second n-type transistors TN and the second port 142 the n-transistor interconnection 140b is with the second connector TNb of the first n-transistor TN electrically conductively connected. The second embodiment 140b is called a Darlington pair. It has a higher gain than the first embodiment. This corresponds to the product of the current gain of both n-type transistors TN .

In the third embodiment 140c is the third port TNc of the n-transistor TN with the second connection TPb of the p-transistor TP and the first connection TPa of the p-transistor TP with the third connection 143 the n-transistor interconnection 140c electrically conductively connected. The first connection 141 the n-transistor interconnection 140c is with the first connection TNa of the n-transistor TN and the third port TPc of the p-transistor TP electrically connected and the second connection 142 the n-transistor interconnection 140c is with the second connector TNb of the n-transistor TN electrically conductively connected. The third embodiment 140c is called a Sziklai circuit. It has a higher gain than the first embodiment. This corresponds to the product of the current gain of the n-transistor TN and p-transistor TP .

4th represents three possible schematic embodiments ( 150a , 150b and 150c ) an electrical circuit according to the invention 150 for a p-transistor connection 150 as in 4th shown schematically, comprises the first embodiment 150a a p-type transistor TP with a first connection TPa , a second connection TPb and a third port TPc , the second embodiment 150b comprises first and second p-type transistors TP each with a first connection TPa , a second port TPb and a third port TPc and the third embodiment 150c comprises a p-type transistor with a first terminal TPa , a second port TPb and a third port TPc and an n-type transistor TN with a first connection TNa , a second port TNb and a third port TNc .

It represents an n-transistor TN either an NPN bipolar transistor or an n-field effect transistor, each with three connections. The first connection in the case of an NPN bipolar transistor TNa as an emitter, the second connection TNb as the base and the third connection TNc referred to as a collector. In the case of an n-type field effect transistor, the first connection is TNa as source, the second connection TNb as the gate and the third connection TNc referred to as the drain.

It represents a p-transistor TP a PNP bipolar transistor or a p-field effect transistor, each with three connections. The first connection in a PNP bipolar transistor TPa as an emitter, the second connection TPb as the base and the third connection TPc referred to as a collector. In the case of an n-type field effect transistor, the first connection is TPa as source, the second connection TPb as the gate and the third connection TPc referred to as the drain.

In the first embodiment 150a is the first connection TPa of the p-transistor TP with the first connection 151 the p-transistor connection 150a , the second port TPb of the p-transistor TP with the second connection 152 the p-transistor connection 150a and the third connector TPc of the p-transistor TP with the third connection 153 the p-transistor connection 150a electrically conductively connected.

In the second embodiment 150b is the first connection TPa of the first p-transistor TP with the second connection TPb of the second p-transistor TP and the first connection TPa of the second p-transistor TP with the first connection 151 the p-transistor connection 150b electrically conductively connected. The third connection 153 the p-transistor connection 150b is with the third connection TPc of the first and second p-transistor TP and the second port 152 the p-transistor connection 150b is with the second connector TPb of the first p-transistor TP electrically conductively connected. The second embodiment 150b is called a Darlington pair. It has a higher gain than the first embodiment. This corresponds to the product of the current gain of both p-transistors TP .

In the third embodiment 150c is the third port TPc of the p-transistor TP with the second connection TNb of the n-transistor TN and the first connection TNa of the n-transistor TN with the third connection 153 the p-transistor connection 150c electrically conductively connected. The first connection 151 the p-transistor connection 150c is with the first connection TPa of the p-transistor TP and the third port TNc of the n-transistor TN electrically connected and the second connection 152 the p-transistor connection 150c is with the second connector TPb of the p-transistor TP electrically conductively connected. The third embodiment 150c is called a Sziklai circuit. It has a higher gain than the first embodiment. This corresponds to the product of the current gain of the n-transistor TN and p-transistor TP .

5 provides three possible schematic forms of performance ( 120a , 120b and 120c ) an electrical circuit according to the invention 120 for a p-current mirror 120 as in 5 shown schematically, comprises the first embodiment 120a a first p-type transistor TP and a second p-type transistor TP each with a first connection TPa , a second port TPb and a third port TPc , the second embodiment 120b comprises a first p-type transistor TP , a second p-type transistor TP and a third p-type transistor TP each with a first connection TPa , a second port TPb and a third port TPc and the third embodiment 120c comprises a first p-type transistor TP , a second p-type transistor TP , a third p-type transistor TP and a fourth p-type transistor TP each with a first connection TPa , a second port TPb and a third port TPc .

In the first embodiment 120a is the second port 122 of the p-current mirror 120a with the third connection TPc of the second p-transistor TP and with the second connection TPb of the first p-transistor TP and the second p-type transistor TP electrically conductively connected. The first connection 121 of the p-current mirror 120a is with each the first connection TPa of the first p-transistor TP and the second p-type transistor TP electrically connected and the third connection 123 of the p-current mirror 120a is with the third connector TPc of the first p-transistor TP electrically conductively connected.

In the second embodiment 120b is the second port 122 of the p-current mirror 120b with the third connection TPc of the second p-transistor TP and with the second connection TPb of the third p-transistor TP electrically conductively connected. The first connection 121 of the p-current mirror 120b is in each case with the first connection TPa of the first p-transistor TP and the second p-type transistor TP electrically connected and the third connection 123 of the p-current mirror 120b is connected to the third terminal TPc of the first p-transistor TP electrically conductively connected. The second connection TPb of the first p-transistor TP is with the second connector TPb of the second p-transistor TP and the first connection TPa of the third p-transistor TP electrically connected and the third connection TPc of the third p-transistor TP is with the negative power supply -Ub electrically conductively connected.

In the third embodiment 120c is the second port 122 of the p-current mirror 120c with the third connection TPc of the second p-transistor TP and with the second connection TPb of the first p-transistor TP and the second p-type transistor TP electrically conductively connected. The first connection 121 of the p-current mirror 120c is with the first connection TPa of the third p-transistor TP and the fourth p-transistor TP electrically connected and the third connection 123 of the p-current mirror 120c is with the third connector TPc of the first p-transistor TP electrically conductively connected. The third connection TPc of the third p-transistor TP is with the first connection TPa of the first p-transistor TP electrically connected and the first connection TPa of the second p-transistor TP is with the third connector TPc of the fourth p-transistor TP and the second connection TPb of the third p-transistor TP and the fourth p-transistor TP electrically conductively connected.

6 provides three possible schematic forms of performance ( 130a , 130b and 130c ) an electrical circuit according to the invention 130 for an n-current mirror 130 as in 6 shown schematically, comprises the first embodiment 130a a first n-type transistor TN and a second n-type transistor TN each with a first connection TNa , a second port TNb and a third port TNc , the second embodiment 130b comprises a first n-type transistor TN , a second n-type transistor TN and a third n-type transistor TN each with a first connection TNa , a second port TNb and a third port TNc and the third embodiment 130c comprises a first n-type transistor TN , a second n-type transistor TN , a third n-type transistor TN and a fourth n-type transistor TN each with a first connection TNa , a second port TNb and a third port TNc .

In the first embodiment 130a is the third port 133 of the n-current mirror 130a with the third connection TNc of the second n-transistor TN and with the second connection TNb of the first n-transistor TN and the second n-type transistor TN electrically conductively connected. The first connection 131 of the n-current mirror 130a is with the first connection TNa of the first n-transistor TN and the second n-type transistor TN electrically connected and the second connection 132 of the n-current mirror 130a is with the third connector TNc of the first n-transistor TN electrically conductively connected.

In the second embodiment 130b is the third port 133 of the n-current mirror 130b with the third connection TNc of the second n-transistor TN and with the second connection TNb of the third n-transistor TN electrically conductively connected. The first connection 131 of the n-current mirror 130b is in each case with the first connection TNa of the first n-transistor TN and the second n-type transistor TN electrically connected and the second connection 132 of the n-current mirror 130b is connected to the third terminal TNc of the first n-transistor TN electrically conductively connected. The second connection TNb of the first n-transistor TN is with the second connector TNb of the second n-transistor TN and the first connection TNa of the third n-transistor TN electrically connected and the third connection TNc of the third n-transistor TN is with the positive power supply + Ub electrically conductively connected.

In the third embodiment 130c is the third port 133 of the n-current mirror 130c with the third connection TNc of the second n-transistor TN and with the second connection TNb of the first n-transistor TN and the second n-type transistor TN electrically conductively connected. The first connection 131 of the n-current mirror 130c is with the first connection TNa of the third n-transistor TN and the fourth n-type transistor TN electrically connected and the second connection 132 of the n-current mirror 130c is with the third connector TNc of the first n-transistor TN electrically conductively connected. The third connection TNc of the third n-transistor TN is with the first connection TNa of the first n-transistor TN electrically connected and the first connection TNa of the second n-transistor TN is with the third connector TNc of the fourth n-transistor TN and the second connection TNb of the third n-transistor TN and the fourth n-type transistor TN electrically conductively connected.

7th Fig. 3 schematically shows an embodiment of an electrical circuit according to the invention 800 for a complementary differential amplifier with N differential input stages according to the subject matter of independent claims 8 and 9. As in 7th shown schematically, the electrical circuit 800 comprises N differential input stages 110 {N ∈ ℕ ∩ N ≥ 2}, 2N inputs (a first input E1 to 2N-th Input E (2N)), a first output A1 , a second exit A2 , a third exit A3 , a fourth exit A4 , a p-current mirror 120 , an n-current mirror 130 , a negative power supply -Ub and a positive power supply + Ub . Each of the N input stages represents a first connection 111 , a second port 112 , a third port 113 , a fourth port 114 , a fifth port 115 and a sixth port 116 . The p-current mirror 120 provides a first connection 121 , a second port 122 and a third port 123 and the n-current mirror 130 provides a first connection 131 , a second port 132 and a third port 133 ready. The third connection 123 of the p-current mirror 120 is with the first exit A1 and each with the first connection 111 of the N differential input stages 110 electrically connected and the second connection 122 of the p-current mirror 120 is with the third exit A3 and each with the second connection 112 of the N differential input stages 110 electrically conductively connected. The first connection 121 of the p-current mirror 120 is with the positive power supply + Ub electrically conductively connected. The odd-numbered inputs E (2x-1) {x ∈ N} are each connected to the fifth connection 115 the respective xth differential input stage 110 electrically connected and the even-numbered inputs E (2x) {x ∈ N} are each connected to the sixth connection 116 the respective xth differential input stage 110 electrically conductively connected. Here x represents a natural number in the range from 1 to N and acts as a running variable. The third connection 133 of the n-current mirror 130 is with the fourth exit A4 and each with the fourth connection 114 of the N differential input stages 110 electrically connected and the second connection 132 of the n-current mirror 130 is with the second exit A2 and each with the third connection 113 of the N differential input stages 110 electrically conductively connected. The first connection 131 of the n-current mirror 130 is with the negative power supply -Ub electrically conductively connected.

Reading list

• [1] Tietze, Ulrich; Schenk, Christoph: "Semiconductor circuit technology."; 11. Berlin; Heidelberg; New York: Springer-Verlag, 1999. - ISBN 3-540-64192-0
• [2] Stonchino, Giovanni: “Ultra-fast Amplifier.” In: ELEC-TRONICS WORLD (1995), 10, pp. 835-841

List of reference symbols

100

a first embodiment of an electrical circuit of a differential amplifier;

110

Differential input stage

111

Electrical conductive connection from the differential input stage 110

112

Electrical conductive connection from the differential input stage 110

113

Electrical conductive connection from the differential input stage 110

114

Electrical conductive connection from the differential input stage 110

115

Electrical conductive connection from the differential input stage 110

116

Electrical conductive connection from the differential input stage 110

120

p-current mirror

121

Electrical conductive connection of the p current mirror 120

122

Electrical conductive connection of the p current mirror 120

123

Electrical conductive connection of the p current mirror 120

130

n-current mirror

131

Electrical conductive connection of the n current mirror 130

132

Electrical conductive connection of the n current mirror 130

133

Electrical conductive connection of the n current mirror 130

140

n-transistor connection

141

Electrically conductive connection of the n-transistor interconnection 140

142

Electrically conductive connection of the n-transistor interconnection 140

143

Electrically conductive connection of the n-transistor interconnection 140

150

p-transistor connection

151

Electrically conductive connection of the p-transistor connection 150

152

Electrically conductive connection of the p-transistor connection 150

153

Electrically conductive connection of the p-transistor connection 150

160

First constant current source

161

Electrical conductive connection from the first constant current source 160

162

Electrical conductive connection from the first constant current source 160

170

Second constant current source

171

Electrical conductive connection from the second constant current source 170

172

Electrical conductive connection from the second constant current source 170

180

Resistor connection

181

Electrical conductive connection from the resistor circuit 180

182

Electrical conductive connection from the resistor circuit 180

TN

n-transistor, which can be implemented either as an NPN bipolar transistor or as an n-field effect transistor, each with three connections

TNa

First connection of the n-transistor TN This is called the emitter for an NPN bipolar transistor and the source for an n-type field effect transistor

TNb

Second connection of the n-transistor TN This is called the base for an NPN bipolar transistor and the gate for an n-type field effect transistor

TNc

Third connection of the n-transistor TN , whereby this is called the collector for an NPN bipolar transistor and the drain for an n-field effect transistor

TP

p-transistor, which can be implemented either as a PNP bipolar transistor or as a p-field effect transistor, each with three connections

TPa

First connection of the p-transistor TP This is called the emitter for a PNP bipolar transistor and the source for a p-type field effect transistor

TPb

Second connection of the p-transistor TP , with this

TPc

for a PNP bipolar transistor as the base and for a p-field effect transistor as the gate, the third connection of the p-transistor TP This is called the collector for a PNP bipolar transistor and the drain for a p-field effect transistor

-Ub.

Negative voltage source

+ Ub

Positive voltage source

E1-E4

Inputs of the differential amplifier

Ex)

x-th input of the differential amplifier

A1-A4

Outputs of the differential amplifier

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• DE 3232442 A1 [0011]
• US 4780630 [0012]

Non-patent literature cited

• Tietze, Ulrich; Schenk, Christoph: "Semiconductor circuit technology."; 11. Berlin; Heidelberg; New York: Springer-Verlag, 1999. - ISBN 3-540-64192-0 [0087]
• Stonchino, Giovanni: "Ultra-fast Amplifier." In: ELEC-TRONICS WORLD (1995), 10, pp. 835-841 [0087]

Claims (9)

Electrical circuit (100) for a complementary differential amplifier, comprising: 1.1. two differential input stages (110) with a first connection (111), a second connection (112), a third connection (113), a fourth connection (114), a fifth connection (115) and a sixth connection (116), comprising: 1.1.1. a first n-transistor connection (140) with a first connection (141), a second connection (142) and a third connection (143), 1.1.1.1. wherein the third connection (143) of the first n-transistor connection (140) is electrically conductively connected to the first connection (111) of the differential input stages (110); 1.1.2. a first p-transistor connection (150) with a first connection (151), a second connection (152) and a third connection (153), 1.1.2.1. wherein the third connection (153) of the first p-transistor connection (150) is connected to the third connection (113) of the differential input stages (110) in an electrically conductive manner, and 1.1.2.2. wherein the second connection (142) of the first n-transistor connection (140) is electrically conductively connected to the second connection (152) of the first p-transistor connection (150) and to the fifth connection (115) of the differential input stages (110); 1.1.3. a second n-transistor connection (140) with a first connection (141), a second connection (142) and a third connection (143), 1.1.3.1. wherein the third connection (143) of the second n-transistor interconnection (140) is electrically conductively connected to the second connection (112) of the differential input stages (110); 1.1.4. a second p-transistor connection (150) with a first connection (151), a second connection (152) and a third connection (153), 1.1.4.1. wherein the third connection (153) of the second p-transistor connection (150) is connected to the fourth connection (114) of the differential input stages (110) in an electrically conductive manner, and 1.1.4.2. wherein the second connection (142) of the second n-transistor connection (140) is electrically conductively connected to the second connection (152) of the second p-transistor connection (150) and to the sixth connection (116) of the differential input stages (110); 1.1.5. four resistor circuits (180), each with a first connection (181) and a second connection (182), 1.1.5.1. wherein the first connection (181) of the first resistor circuit (180) is connected to the first connection (141) of the first n-transistor circuit (140) in an electrically conductive manner, 1.1.5.2. wherein the second connection (182) of the second resistor connection (180) is connected in an electrically conductive manner to the first connection (141) of the second n-transistor connection (140), 1.1.5.3. wherein the first connection (181) of the third resistor connection (180) is connected in an electrically conductive manner to the first connection (151) of the first p-transistor connection (150), and 1.1.5.4. wherein the second connection (182) of the fourth resistor connection (180) is connected in an electrically conductive manner to the first connection (151) of the second p-transistor connection (150); 1.1.6. a negative voltage supply (-Ub) set up in such a way that a negative electrical voltage can be provided and a positive voltage supply (+ Ub) set up in such a way that a positive electrical voltage can be provided; 1.1.7. a first constant current source (160), set up in such a way that an electrical current can be provided, with a first connection (161) and a second connection (162), 1.1.7.1. wherein the first connection (161) of the first constant current source (160) is electrically conductively connected to the second connection (182) of the first resistance circuit (180) and the first connection (181) of the second resistance circuit (180), and 1.1.7.2. wherein the second connection (162) of the first constant current source (160) is electrically conductively connected to the negative voltage supply (-Ub); and 1.1.8. a second constant current source (170), set up in such a way that an electrical current can be provided, with a first connection (171) and a second connection (172), 1.1.8.1. wherein the first connection (171) of the second constant current source (170) is electrically conductively connected to the second connection (182) of the third resistance circuit (180) and the first connection (181) of the fourth resistance circuit (180), and 1.1.8.2. wherein the second connection (172) of the second constant current source (170) is electrically conductively connected to the positive voltage supply (+ Ub); 1.2. a first input (E1), a second input (E2), a third input (E3) and a fourth input (E4), each of the inputs (E1, E2, E3, E4) being set up so that through each of the inputs (E1, E2, E3, E4) an electrical signal can each be passed through, 1.2.1. wherein the first input (E1) is electrically conductively connected to the fifth connection (115) of the first differential input stage (110), 1.2.2. the second input (E2) being electrically conductively connected to the sixth connection (116) of the first differential input stage (110), 1.2.3. the third input (E3) being electrically conductively connected to the fifth connection (115) of the second differential input stage (110), and 1.2.4. wherein the fourth input (E4) is electrically conductively connected to the sixth connection (116) of the second differential input stage (110); 1.3. a first output (A1), a second output (A2), a third output (A3) and a fourth output (A4), each of the outputs (A1, A2, A3, A4) being set up in such a way that through each of the outputs (A1, A2, A3, A4) an electrical signal can each be passed through, 1.3.1. wherein the first output (A1) is electrically conductively connected to the first connection (111) of the first and second differential input stage (110), 1.3.2. the second output (A2) being electrically conductively connected to the third connection (113) of the first and second differential input stage (110), 1.3.3. wherein the third output (A3) is electrically conductively connected to the second connection (112) of the first and second differential input stage (110), and 1.3.4. wherein the fourth output (A4) is electrically conductively connected to the fourth connection (114) of the first and second differential input stage (110); 1.4. a p-current mirror (120) with a first connection (121), a second connection (122) and a third connection (123), 1.4.1. the first connection (121) being connected to the positive voltage supply (+ Ub) in an electrically conductive manner, 1.4.2. wherein the second connection (122) is electrically conductively connected to the third output (A3) and to the second connection (112) of the first and second differential input stage (110), and 1.4.3. wherein the third connection (123) is electrically conductively connected to the first output (A1) and to the first connection (111) of the first and second differential input stage (110); and 1.5. an n-current mirror (130) with a first connection (131), a second connection (132) and a third connection (133), 1.5.1. wherein the first connection (131) is connected to the negative voltage supply (-Ub) in an electrically conductive manner, 1.5.2. wherein the second connection (132) is electrically conductively connected to the second output (A2) and to the third connection (113) of the first and second differential input stage (110), and 1.5.3. wherein the third connection (133) is electrically conductively connected to the fourth output (A4) and to the fourth connection (114) of the first and second differential input stage (110). Electrical circuit (200) according to Claim 1 , 2.1. wherein the n-transistor interconnection (140, 140a) of the differential input stages (110) is formed by means of an n-transistor (TN) each with a first connection (TNa), a second connection (TNb) and a third connection (TNc), 2.1 .1. wherein the first connection (141) of the n-transistor interconnection (140, 140a) is connected in an electrically conductive manner to the first connection (TNa) of the n-transistor (TN), 2.1.2. the second connection (142) of the n-transistor interconnection (140, 140a) being connected in an electrically conductive manner to the second connection (TNb) of the n-transistor (TN), and 2.1.3. wherein the third connection (143) of the n-transistor interconnection (140, 140a) is electrically conductively connected to the third connection (TNc) of the n-transistor (TN); and 2.2. the p-transistor interconnection (150, 150a) of the differential input stages (110) each being formed by means of a p-transistor (TP) each having a first connection (TPa), a second connection (TPb) and a third connection (TPc), 2.2 .1. wherein the first connection (151) of the p-transistor interconnection (150, 150a) is connected to the first connection (TPa) of the p-transistor (TP) in an electrically conductive manner, 2.2.2. wherein the second connection (152) of the p-transistor interconnection (150, 150a) is connected to the second connection (TPb) of the p-transistor (TP) in an electrically conductive manner, and 2.2.3. wherein the third connection (153) of the p-transistor interconnection (150, 150a) is connected in an electrically conductive manner to the third connection (TPc) of the p-transistor (TP). Electrical circuit (300) according to Claim 1 , 3.1. wherein the n-transistor interconnection (140, 140b) of the differential input stages (110) each consists of a Darlington circuit, comprising a first n-transistor (TN) and a second n-transistor (TN) each with a first connection (TNa), a second connection (TNb) and a third connection (TNc), 3.1.1. wherein the first connection (TNa) of the first n-transistor (TN) is electrically conductively connected to the second connection (TNb) of the second n-transistor (TN), 3.1.2. the first connection (141) of the n-transistor interconnection (140, 140b) being connected in an electrically conductive manner to the first connection (TNa) of the second n-transistor (TN), 3.1.3. wherein the second connection (142) of the n-transistor connection (140, 140b) is connected in an electrically conductive manner to the second connection (TNb) of the first n-transistor (TN), and 3.1.4. wherein the third connection (143) of the n-transistor interconnection (140, 140b) is in each case connected in an electrically conductive manner to the third connection (TNc) of the first n-transistor (TN) and the second n-transistor (TN); and 3.2. wherein the p-transistor interconnection (150, 150b) of the differential input stages (110) each consists of a Darlington circuit, comprising a first p-transistor (TP) and a second p-transistor (TP) each with a first connection (TPa), a second connection (TPb) and a third connection (TPc), 3.2.1. wherein the first connection (TPa) of the first p-transistor (TP) is electrically conductively connected to the second connection (TPb) of the second p-transistor (TP), 3.2.2. the first connection (151) of the p-transistor interconnection (150, 150b) being connected in an electrically conductive manner to the first connection (TPa) of the second p-transistor (TP), 3.2.3. wherein the second connection (152) of the p-transistor connection (150, 150b) is connected to the second connection (TPb) of the first p-transistor (TP) in an electrically conductive manner, and 3.2.4. wherein the third connection (153) of the p-transistor interconnection (150, 150b) is electrically conductively connected to the third connection (TPc) of the first p-transistor (TP) and the second p-transistor (TP). Electrical circuit (400) according to Claim 1 , 4.1. the n-transistor interconnection (140, 140c) of the differential input stages (110) each consisting of a Sziklai circuit comprising an n-transistor (TN), each with a first connection (TNa), a second connection (TNb) and a third connection (TNc), and a p-transistor (TP), each with a first connection (TPa), a second connection (TPb) and a third connection (TPc) is formed, 4.1.1. the third connection (TNc) of the n-transistor (TN) being connected in an electrically conductive manner to the second connection (TPb) of the p-transistor (TP), 4.1.2. wherein the first connection (141) of the n-transistor interconnection (140, 140c) is connected in an electrically conductive manner to the first connection (TNa) of the n-transistor (TN) and the third connection (TPc) of the p-transistor (TP), 4.1 .3. the second connection (142) of the n-transistor interconnection (140, 140c) being connected in an electrically conductive manner to the second connection (TNb) of the n-transistor (TN), and 4.1.4. wherein the third connection (143) of the n-transistor interconnection (140, 140c) is electrically conductively connected to the first connection (TPa) of the p-transistor (TP); and 4.2. the p-transistor circuit (150, 150c) of the differential input stages (110) each consisting of a Sziklai circuit comprising a p-transistor (TP), each with a first connection (TPa), a second connection (TPb) and a third connection (TPc), and an n-type transistor (TN), each with a first connection (TNa), a second connection (TNb) and a third connection (TNc) is formed, 4.2.1. wherein the third connection (TPc) of the p-transistor (TP) is electrically conductively connected to the second connection (TNb) of the n-transistor (TN), 4.2.2. wherein the first connection (151) of the p-transistor interconnection (150, 150c) is electrically conductively connected to the first connection (TPa) of the p-transistor (TP) and the third connection (TNc) of the n-transistor (TN), 4.2.3. wherein the second connection (152) of the p-transistor connection (150, 150c) is connected in an electrically conductive manner to the second connection (TPb) of the p-transistor (TP), and 4.2.4. wherein the third connection (153) of the p-transistor circuit (150, 150c) is connected in an electrically conductive manner to the first connection (TNa) of the n-transistor (TN). Electrical circuit (500) according to one of the preceding Claims 2 to 4th , 5.1. wherein the p-current mirror (120, 120a), comprising a first p-transistor (TP) and a second p-transistor (TP), each with a first connection (TPa), a second connection (TPb) and a third connection ( TPc), is formed, 5.1.1. wherein the first connection (121) of the p-current mirror (120, 120a) is connected in an electrically conductive manner to the first connection (TPa) of the first p-transistor (TP) and the second p-transistor (TP), 5.1.2. wherein the second connection (122) of the p-current mirror (120, 120a) with the third connection (TPc) of the second p-transistor (TP) and in each case with the second connection (TPb) of the first p-transistor (TP) and the second p-transistor (TP) is connected in an electrically conductive manner, and 5.1.3. wherein the third connection (123) of the p-current mirror (120, 120a) is connected in an electrically conductive manner to the third connection (TPc) of the first p-transistor (TP); and 5.2. wherein the n-current mirror (130, 130a), comprising a first n-transistor (TN) and a second n-transistor (TN), each with a first connection (TNa), a second connection (TNb) and a third connection ( TNc), 5.2.1. wherein the first connection (131) of the n-current mirror (130, 130a) is connected in an electrically conductive manner to the first connection (TNa) of the first n-transistor (TN) and the second n-transistor (TN), 5.2.2. wherein the second connection (132) of the n-type current mirror (130, 130a) is connected in an electrically conductive manner to the third connection (TNc) of the first n-transistor (TN), and 5.2.3. wherein the third connection (133) of the n-type current mirror (130, 130a) with the third connection (TNc) of the second n-transistor (TN) and in each case with the second connection (TNb) of the first n-transistor (TN) and the second n-transistor (TN) is connected in an electrically conductive manner. Electrical circuit (600) according to one of the preceding Claims 2 to 4th , 6.1. wherein the p-current mirror (120, 120b) consists of a first p-transistor (TP), a second p-transistor (TP) and a third p-transistor (TP), each with a first connection (TPa), a second connection (TPb) and a third connection (TPc), 6.1.1. the second connection (TPb) of the first p-transistor (TP) and the second p-transistor (TP) being connected in an electrically conductive manner to the first connection (TPa) of the third p-transistor (TP), 6.1.2. wherein the third connection (TPc) of the third p-transistor (TP) is connected to the negative voltage supply (-Ub) in an electrically conductive manner, 6.1.3. wherein the first connection (121) of the p-current mirror (120, 120b) is connected in an electrically conductive manner to the first connection (TPa) of the first p-transistor (TP) and the second p-transistor (TP), 6.1.4. wherein the second connection (122) of the p-current mirror (120, 120b) is electrically conductively connected to the second connection (TPb) of the third p-transistor (TP) and to the third connection (TPc) of the second p-transistor (TP) , and 6.1.5. wherein the third connection (123) of the p-current mirror (120, 120b) is connected in an electrically conductive manner to the third connection (TPc) of the first p-transistor (TP); and 6.2. wherein the n-current mirror (130, 130b) consists of a first n-transistor (TN), a second n-transistor (TN) and a third n-transistor (TN), each with a first connection (TNa), a second connection (TNb) and a third connection (TNc), 6.2.1. the second connection (TNb) of the first n-transistor (TN) and the second n-transistor (TN) being connected in an electrically conductive manner to the first connection (TNa) of the third n-transistor (TN), 6.2.2. wherein the third connection (TNc) of the third n-transistor (TN) is connected to the positive voltage supply (+ Ub) in an electrically conductive manner, 6.2.3. wherein the first connection (131) of the n-current mirror (130, 130b) is electrically conductively connected to the first connection (TNa) of the first n-transistor (TN) and the second n-transistor (TN), 6.2.4. wherein the second connection (132) of the n-type current mirror (130, 130b) is connected in an electrically conductive manner to the third connection (TNc) of the first n-type transistor (TN), and 6.2.5. wherein the third connection (133) of the n-current mirror (130, 130b) is electrically conductively connected to the second connection (TNb) of the third n-transistor (TN) and to the third connection (TNc) of the second n-transistor (TN) . Electrical circuit (700) according to one of the preceding Claims 2 to 4th , 7.1. wherein the p-current mirror (120, 120c) from a first p-transistor (TP), a second p-transistor (TP), a third p-transistor (TP) and a fourth p-transistor (TP), each with one first connection (TPa), a second connection (TPb) and a third connection (TPc), 7.1.1. wherein the second connection (TPb) of the third p-transistor (TP) and fourth p-transistor (TP), with the first connection (TPa) of the second p-transistor (TP) and the third connection (TPc) of the fourth p -Transistors (TP) are connected in an electrically conductive manner, 7.1.2. wherein the first connection (TPa) of the first p-transistor (TP) is electrically conductively connected to the third connection (TPc) of the third p-transistor (TP), 7.1.3. wherein the second connection (TPb) of the first p-transistor (TP), with the second connection (TPb) of the second p-transistor (TP), with the third connection (TPc) of the second p-transistor (TP) and the second Connection (122) of the p-current mirror (120, 120c) is electrically conductively connected, 7.1.4. wherein the first connection (121) of the p-current mirror (120, 120c) is electrically conductively connected to the first connection (TPa) of the third p-transistor (TP) and fourth p-transistor (TP), and 7.1.5. wherein the third connection (123) of the p-current mirror (120, 120c) is connected in an electrically conductive manner to the third connection (TPc) of the first p-transistor (TP); and 7.2. wherein the n-current mirror (130, 130c) comprises a first n-transistor (TN), a second n-transistor (TN), a third n-transistor (TN) and a fourth n-transistor (TN), each with a first Connection (TNa), a second connection (TNb) and a third connection (TNc) is formed, 7.2.1. wherein the second connection (TNb) of the third n-transistor (TN) and fourth n-transistor (TN), with the first connection (TNa) of the second n-transistor (TN) and the third connection (TNc) of the fourth n -Transistors (TN) are electrically connected, 7.2.2. the first connection (TNa) of the first n-transistor (TN) and the third connection (TNc) of the third n-transistor (TN) being connected in an electrically conductive manner, 7.2.3. wherein the second connection (TNb) of the first n-transistor (TN), with the second connection (TNb) of the second n-transistor (TN), with the third connection (TNc) of the second n-transistor (TN) and the third Connection (133) of the n-current mirror (130, 130c) is connected in an electrically conductive manner, 7.2.4. wherein the first connection (131) of the n-current mirror (130, 130c) is electrically conductively connected to the first connection (TNa) of the third n-transistor (TN) and fourth n-transistor (TN), and 7.2.5. wherein the second connection (132) of the n-current mirror (130) is electrically conductively connected to the third connection (TNc) of the first n-transistor (TN). Electrical circuit (800) based on one of the electrical circuits (500, 600, 700) according to one of the preceding Claims 5 to 7th , the number of differential input stages (110) being expanded to any number N greater than two and the number of inputs being expanded to a number of 2N, with a run variable x 8.1. where N represents a natural number, 8.2. where x represents a natural number in the range from 1 to N, 8.3. wherein the first connections (111) of all differential input stages (110) are electrically conductively connected to one another, to the third connection (123) of the p-current mirror (120) and to the first output (A1) of the electrical circuit (800), 8.4. wherein the second connections (112) of all differential input stages (110) are electrically conductively connected to one another, to the second connection (122) of the p-current mirror (120) and to the third output (A3) of the electrical circuit (800), 8.5. wherein the third connections (113) of all differential input stages (110) are electrically conductively connected to one another, to the second connection (132) of the n-current mirror (130) and to the second output (A2) of the electrical circuit (800), 8.6. wherein the fourth connections (114) of all differential input stages (110) are electrically conductively connected to one another, to the third connection (133) of the n-current mirror (130) and to the fourth output (A4) of the electrical circuit (800), 8.7. wherein each odd-numbered input (E (2x-1)) is in each case connected in an electrically conductive manner to the fifth connection (115) of the x-th differential input stage (110), and 8.8. wherein each even-numbered input (E (2x)) is in each case connected in an electrically conductive manner to the sixth connection (116) of the x-th differential input stage (110). Electrical circuit (900) according to Claim 8 , 9.1. where N ranges from 2 to 30.

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