DE102016003366B4 - Lesepegelgruppierung für erhöhte flash-leistung - Google Patents

Lesepegelgruppierung für erhöhte flash-leistung Download PDF

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Publication number
DE102016003366B4
DE102016003366B4 DE102016003366.5A DE102016003366A DE102016003366B4 DE 102016003366 B4 DE102016003366 B4 DE 102016003366B4 DE 102016003366 A DE102016003366 A DE 102016003366A DE 102016003366 B4 DE102016003366 B4 DE 102016003366B4
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word line
read
read level
error
word lines
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DE102016003366.5A
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DE102016003366A1 (de
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Seyhan Karakulak
Anthony Dwayne WEATHERS
Richard David Barndt
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Sandisk Technologies Inc NDGesD Staates Us
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Western Digital Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0409—Online test

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE102016003366.5A 2015-03-20 2016-03-18 Lesepegelgruppierung für erhöhte flash-leistung Active DE102016003366B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/664,768 2015-03-20
US14/664,768 US9720754B2 (en) 2014-11-20 2015-03-20 Read level grouping for increased flash performance

Publications (2)

Publication Number Publication Date
DE102016003366A1 DE102016003366A1 (de) 2016-09-22
DE102016003366B4 true DE102016003366B4 (de) 2020-10-29

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Country Status (6)

Country Link
JP (1) JP6218195B2 (ko)
KR (1) KR101831209B1 (ko)
CN (1) CN105989891B (ko)
DE (1) DE102016003366B4 (ko)
FR (1) FR3033927B1 (ko)
GB (1) GB2537484B (ko)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10229740B2 (en) * 2016-10-17 2019-03-12 SK Hynix Inc. Memory system of 3D NAND flash and operating method thereof
CN108257642B (zh) * 2016-12-29 2021-08-17 北京忆恒创源科技股份有限公司 读阈值设置方法与装置
US10452480B2 (en) 2017-05-25 2019-10-22 Micron Technology, Inc. Memory device with dynamic processing level calibration
US10140040B1 (en) 2017-05-25 2018-11-27 Micron Technology, Inc. Memory device with dynamic program-verify voltage calibration
US10402272B2 (en) * 2017-05-25 2019-09-03 Micron Technology, Inc. Memory device with dynamic programming calibration
US10347344B2 (en) * 2017-08-29 2019-07-09 Micron Technology, Inc. Read voltage calibration based on host IO operations
KR102395196B1 (ko) 2017-10-17 2022-05-06 삼성전자주식회사 파라미터 교정 기능을 갖는 스토리지 장치 및 상기 스토리지 장치의 동작 방법
CN110010170B (zh) * 2018-01-05 2021-04-02 旺宏电子股份有限公司 存储装置的操作方法及其存储系统
US10910061B2 (en) * 2018-03-14 2021-02-02 Silicon Storage Technology, Inc. Method and apparatus for programming analog neural memory in a deep learning artificial neural network
US10566063B2 (en) 2018-05-16 2020-02-18 Micron Technology, Inc. Memory system with dynamic calibration using a trim management mechanism
US10664194B2 (en) 2018-05-16 2020-05-26 Micron Technology, Inc. Memory system with dynamic calibration using a variable adjustment mechanism
CN108777156A (zh) * 2018-05-31 2018-11-09 郑州云海信息技术有限公司 一种闪存数据处理方法及装置
US10990466B2 (en) 2018-06-20 2021-04-27 Micron Technology, Inc. Memory sub-system with dynamic calibration using component-based function(s)
US11188416B2 (en) 2018-07-12 2021-11-30 Micron Technology, Inc. Enhanced block management for a memory sub-system
CN110908825B (zh) * 2018-09-17 2024-03-01 兆易创新科技集团股份有限公司 一种数据读取方法、装置、存储设备及存储介质
US10936246B2 (en) 2018-10-10 2021-03-02 Micron Technology, Inc. Dynamic background scan optimization in a memory sub-system
US11367488B2 (en) * 2018-12-11 2022-06-21 SK Hynix Inc. Memory system and method for read operation based on grouping of word lines
CN110473588A (zh) * 2019-08-15 2019-11-19 山东华芯半导体有限公司 一种SSD中在线校准NAND Flash读参考电压的方法
US11264103B2 (en) * 2019-08-28 2022-03-01 International Business Machines Corporation Hybrid read voltage calibration in non-volatile random access memory
US10957407B1 (en) * 2019-10-30 2021-03-23 International Business Machines Corporation Calculating corrective read voltage offsets in non-volatile random access memory
DE102020100541A1 (de) 2020-01-13 2021-07-15 Infineon Technologies Ag Bestimmung eines resultierenden datenworts beim zugriff auf einen speicher
US11189351B2 (en) 2020-03-27 2021-11-30 Sandisk Technologies Llc Peak and average current reduction for sub block memory operation
CN112216333B (zh) * 2020-09-30 2024-02-06 深圳市宏旺微电子有限公司 芯片测试方法及装置
CN115101113A (zh) * 2022-07-08 2022-09-23 山东华芯半导体有限公司 一种分析qlc阈值分布在各种条件下变化的方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100118608A1 (en) * 2008-11-10 2010-05-13 Samsung Electronics Co., Ltd. Non-volatile memory device, memory card and system, and method determining read voltage in same
US8072805B2 (en) * 2009-08-18 2011-12-06 Skymedi Corporation Method and system of finding a read voltage for a flash memory
US20130227200A1 (en) * 2012-02-23 2013-08-29 Stec, Inc. Determining bias information for offsetting operating variations in memory cells based on wordline address
US8630121B2 (en) * 2009-06-03 2014-01-14 Marvell World Trade Ltd. Reference voltage optimization for flash memory

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7554853B2 (en) * 2006-12-30 2009-06-30 Sandisk Corporation Non-volatile storage with bias based on selective word line
US8874825B2 (en) * 2009-06-30 2014-10-28 Sandisk Technologies Inc. Storage device and method using parameters based on physical memory block location
US8427875B2 (en) * 2010-12-07 2013-04-23 Silicon Motion Inc. Method and memory controller for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory
US9047955B2 (en) * 2011-03-30 2015-06-02 Stec, Inc. Adjusting operating parameters for memory cells based on wordline address and cycle information
CN102831932B (zh) * 2011-06-14 2015-11-18 群联电子股份有限公司 数据读取方法、存储器控制器及存储器储存装置
US9135106B2 (en) * 2012-05-22 2015-09-15 Hgst Technologies Santa Ana, Inc. Read level adjustment using soft information
KR101984900B1 (ko) * 2012-07-24 2019-05-31 삼성전자 주식회사 메모리 장치 및 상기 메모리 장치의 독출 전압 결정 방법
US8811076B2 (en) * 2012-07-30 2014-08-19 Sandisk Technologies Inc. Systems and methods of updating read voltages
US8879324B2 (en) * 2013-02-01 2014-11-04 Lsi Corporation Compensation loop for read voltage adaptation
US20140359202A1 (en) 2013-05-31 2014-12-04 Western Digital Technologies, Inc. Reading voltage calculation in solid-state storage devices
KR102192910B1 (ko) * 2013-09-10 2020-12-18 에스케이하이닉스 주식회사 반도체 장치, 메모리 시스템 및 이의 동작 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100118608A1 (en) * 2008-11-10 2010-05-13 Samsung Electronics Co., Ltd. Non-volatile memory device, memory card and system, and method determining read voltage in same
US8630121B2 (en) * 2009-06-03 2014-01-14 Marvell World Trade Ltd. Reference voltage optimization for flash memory
US8072805B2 (en) * 2009-08-18 2011-12-06 Skymedi Corporation Method and system of finding a read voltage for a flash memory
US20130227200A1 (en) * 2012-02-23 2013-08-29 Stec, Inc. Determining bias information for offsetting operating variations in memory cells based on wordline address

Also Published As

Publication number Publication date
FR3033927B1 (fr) 2019-10-11
JP2016177860A (ja) 2016-10-06
DE102016003366A1 (de) 2016-09-22
JP6218195B2 (ja) 2017-10-25
GB2537484A (en) 2016-10-19
CN105989891B (zh) 2020-11-24
KR20160113051A (ko) 2016-09-28
GB201604222D0 (en) 2016-04-27
FR3033927A1 (ko) 2016-09-23
KR101831209B1 (ko) 2018-02-23
GB2537484B (en) 2019-07-03
CN105989891A (zh) 2016-10-05

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