DE102015120541B4 - SEMICONDUCTOR CHIP - Google Patents

Abstract

A semiconductor chip (300), comprising: a semiconductor body region (111) which has a first surface and a second surface opposite the first surface; a capacitive structure (230) for detecting crack propagation into the semiconductor body region (111 ), the capacitive structure (230) having a first electrode region (230a) which at least partially surrounds the semiconductor body region (111) and which extends at least substantially from the first surface to the second surface; andwherein the capacitive structure (230) further comprises a second electrode region (230b), which is arranged next to the first electrode region (230a), and an electrically insulating region (230i), which lies between the first electrode region (230a) and the second electrode region (230b ), the capacitive structure (230) having a trench which has the first electrode region (230a), the second electrode region (230b) and the electrically insulating region (230i).

Description

Various embodiments generally relate to a semiconductor chip.

In general, a semiconductor chip (also referred to as an integrated circuit, IC, chip or microchip) can be processed in semiconductor technology on and / or in a wafer (or a substrate or a carrier). The wafer can contain several semiconductor chips in corresponding areas of the wafer. The semiconductor chip can be damaged by mechanical stress during processing. For example, mechanical stress can e.g. during dicing of the semiconductor chip from the wafer, during handling of the semiconductor chip by positioning systems (also called pick-and-place applications) or during heat treatment of the semiconductor chip, e.g. during encapsulation or soldering of the semiconductor chip.

Such mechanical stress can cause crack formation and crack propagation in the semiconductor chip. The impact of a crack on a semiconductor chip (or a device that operates the semiconductor chip) can lead to uncontrolled or undefined behavior, e.g. failure or malfunction of the semiconductor chip. Conventional methods or sensors for detecting chip cracks in a semiconductor chip can be limited in their reliability, which leads to cracks which are not detected, and an increase in their reliability can be time-consuming and cost-intensive.

From the document US 2007/0 262 370 A1 a semiconductor chip with a capacitive structure for detecting crack formation in the semiconductor chip is known.

According to various embodiments, a semiconductor chip includes: a semiconductor body region having a first surface and a second surface opposite the first surface; a capacitive structure for detecting crack propagation in the semiconductor body region; wherein the capacitive structure may include a first electrode region that at least partially surrounds the semiconductor body region and at least substantially extends from the first surface to the second surface; wherein the capacitive structure may further include a second electrode region disposed adjacent to the first electrode region and an electrically insulating region that extends between the first electrode region and the second electrode region, the capacitive structure having a trench that defines the first electrode region , the second electrode region and the electrically insulating region.

According to various embodiments, the second electrode region can at least partially surround the semiconductor body region.

According to various embodiments, the second electrode region can extend at least substantially from the first surface to the second surface.

According to various embodiments, the semiconductor chip can further include a first contact pad and a second contact pad, wherein the first electrode region can be electrically coupled to the first contact pad; and wherein the second electrode region can be electrically coupled to the second contact pad; wherein the first contact pad and the second contact pad can be designed for electrical coupling to a measuring circuit in order to measure a parameter of the capacitive structure.

According to various embodiments, the semiconductor chip may further include the measuring circuit, which is designed to measure a value of the parameter of the capacitive structure by electrically characterizing the capacitive structure; wherein the measuring circuit can also be designed to determine a crack on the basis of the measured value of the parameter.

According to various embodiments, the first electrode region can contain a first material and the second electrode region can contain a second material.

According to various embodiments, the first material can be a first metal or a first metal alloy and the second material can be a second metal or a second metal alloy.

According to various embodiments, the first material and the second material can be the same material.

According to various embodiments, the first material can be a doped semiconductor of a first conductivity type (e.g. n-type doped) and the second material can be a doped semiconductor of a second conductivity type (e.g. p-type doped).

According to various embodiments, the first material can be a metal or a metal alloy and the second material can be a doped semiconductor.

According to various embodiments, the electrically insulating region can contain a dielectric material.

According to various embodiments, the first electrode region may include a first metal or metal alloy that at least fills the trench, and the second electrode region may include a second metal or metal alloy that at least partially fills the trench.

According to various embodiments, the first electrode region may include a first semiconductor region of a first conductivity type that contains a sidewall of the trench, wherein the second electrode region may include a second semiconductor region of a second conductivity type; and wherein the electrically insulating region may include a depletion region formed by the first semiconductor region and the second semiconductor region.

According to various embodiments, the capacitive structure may include a first trench that contains the first electrode region, wherein the capacitive structure may include a second trench that contains the second electrode region.

According to various embodiments, the first electrode region may contain a first metal or a first metal alloy that at least partially fills the first trench, and the second electrode region may include a second metal or a second metal alloy that at least partially fills the second trench crowded.

According to various embodiments, the semiconductor chip may further include a third electrode region, which is arranged next to the first electrode region, and a further electrically insulating region, which extends between the third electrode region and the first electrode region.

According to various embodiments, the third electrode region and the second electrode region can be arranged on opposite sides of the first electrode region.

According to various embodiments, the first electrode region and second electrode region form a p-n junction, wherein the electrically insulating region can contain a depletion region of the p-n junction.

According to various embodiments, a doped part of the semiconductor body region can form the second electrode region.

According to various embodiments, an oxidized part of the semiconductor body region, e.g. an oxide of the doped part of the semiconductor body region, which form the electrically insulating region.

According to various embodiments, the first electrode region can form a side wall of the semiconductor chip or a side wall of the semiconductor body region.

According to various embodiments, the second electrode region can form a side wall of the semiconductor chip or a side wall of the semiconductor body region. The second electrode region can be arranged between the first electrode region and the semiconductor chip or the semiconductor body region.

According to various embodiments, a semiconductor chip includes a semiconductor body region that includes a first surface and a second surface opposite the first surface; a capacitive structure for detecting crack propagation in the semiconductor body region; wherein the capacitive structure may include a first electrode region containing a first metal or a first metal alloy and a second electrode region containing a second metal or a second metal alloy disposed adjacent to the first electrode region, the first and second electrode regions at least partially surround the semiconductor body region and at least substantially extend from the first surface to the second surface; and wherein the capacitive structure may further include an electrically insulating region disposed between the first electrode region and the second electrode region, the capacitive structure having a trench that includes the first electrode region, the second electrode region and the electrically insulating region.

Different embodiments according to the invention relate to a semiconductor chip according to claims 1 and 19. Refinements result according to the dependent claims.

According to various embodiments, a semiconductor chip may include: a semiconductor body region that includes an upper side, a lower side opposite the upper side, and a side side that extends between the upper side and the lower side; wherein the side (e.g., a sidewall) can surround the semiconductor body region; a capacitive structure for detecting crack propagation in the semiconductor body region; the capacitive structure may include a metal electrode over the side and an electrically insulating layer disposed between the metal electrode and the side; and wherein the capacitive structure may further include a semiconductor electrode formed by a doped part of the semiconductor body region.

According to various embodiments, the electrically insulating layer can contain an oxide of the doped part of the semiconductor body region.

According to various embodiments, a semiconductor chip may include: a semiconductor body region that includes a first surface and a second surface opposite the first surface; a crack absorption region that at least partially surrounds the semiconductor body region, wherein the crack absorption region can extend from the first surface in a direction to the second surface; wherein the crack absorption area can contain a greater elongation at break than the semiconductor body area.

According to various embodiments, the crack absorption area can extend essentially from the first surface to the second surface.

According to various embodiments, the crack absorption area can extend at least substantially from the first surface to the second surface.

According to various embodiments, the crack absorption area may include a deformable material.

According to various embodiments, the crack absorption area can contain an elastomer.

According to various embodiments, the crack absorption area can contain a polymer.

According to various embodiments, the crack absorption area may include a trench that is at least partially filled with at least one of a deformable material, an elastomer, and a polymer.

According to various embodiments, the crack absorption region can form a side wall of the semiconductor chip.

According to various embodiments, the semiconductor chip may further include a first electrode region and a second electrode region, wherein the crack absorption region can extend between the first electrode region and the second electrode region, and wherein the first electrode region, the crack absorption region and the second electrode region have a capacitive structure for detecting a crack propagation in can form the semiconductor body region.

According to various embodiments, the crack absorption area may include a dielectric elastomer.

According to various embodiments, a method for processing a semiconductor chip can include forming a trench in the semiconductor chip, wherein the trench can at least partially surround a semiconductor body region of the semiconductor chip and at least essentially move from a first surface of the semiconductor body region to one may extend second surface of the semiconductor body region opposite the first surface; forming a capacitive structure including a first electrode region, a second electrode region, and an electrically insulating region that extends between the first electrode region and the second electrode region; wherein at least the first electrode area can be formed at least in or on the trench, so that the first electrode area can at least partially surround the semiconductor body area and can extend at least substantially from the first surface to the second surface.

According to various embodiments, the second electrode region can be formed in the trench, so that the second electrode region can at least partially surround the semiconductor body region and can at least substantially extend from the first surface to the second surface.

According to various embodiments, the first electrode region can contain a first metal or a metal alloy, the second electrode region can contain a second metal or a metal alloy and the electrically insulating region can contain a dielectric material.

According to various embodiments, the method can further include: forming a further trench in the semiconductor chip, the further trench being able to at least partially surround the semiconductor body region of the semiconductor chip and at least substantially extending from the first surface of the semiconductor body region to the second surface of the semiconductor body region; wherein the second electrode region can be formed in the further trench, so that the second electrode region can at least partially surround the semiconductor body region and at least essentially extend from the first surface of the semiconductor body region to the second surface of the semiconductor body region. Can extend territory; wherein the electrically insulating region can be formed from a part of the semiconductor chip between the trench and the further trench.

According to various embodiments, the first electrode region can be a first metal or contain a metal alloy, the second electrode region can contain a second metal or a metal alloy, and the electrically insulating region can contain a dielectric material.

According to various embodiments, the second electrode region can be formed next to the first electrode region and in such a way that the second electrode region can at least partially surround the semiconductor body region; wherein the first electrode region may include a first semiconductor of a first conductivity type, the second electrode region may include a second semiconductor of a second conductivity type, and the electrically insulating region may include a depletion region formed by the first and second semiconductors.

According to various embodiments, forming the capacitive structure may include: depositing a dopant into the trench; and diffusing out a dopant from the doping material into a side wall of the trench, wherein the first electrode region can be formed from the out-diffused dopant.

According to various embodiments, the diffusion of the dopant from the doping material may include heating the doping material.

According to various embodiments, forming the capacitive structure may further include removing the dopant from the trench after the dopant has diffused out of the dopant and at least partially filling the trench with a filler. The filler material can contain a conductive material.

According to various embodiments, forming the capacitive structure may include: depositing another dopant into the further trench; and diffusing out another doping agent from the further doping material into a side wall of the further trench, wherein the second electrode region can be formed from the further doping agent diffused out.

According to various embodiments, the formation of the capacitive structure may further include removing the further doping material from the further trench after the further doping agent has diffused out of the further doping material and at least partially filling the further trench with a filling material.

According to various embodiments, forming the capacitive structure may further include: forming a third electrode region adjacent to the first electrode region, wherein the third electrode region and the second electrode region may be arranged on opposite sides of the first electrode region; and forming another electrically insulating region between the third electrode region and the first electrode region.

According to various embodiments, the third electrode region can include a third metal or a metal alloy or a semiconductor of a third conductivity type. The third conductivity type can be the same as the second conductivity type. The third metal or metal alloy may be the same as the second metal or metal alloy.

According to various embodiments, the semiconductor chip may be part of a wafer and the method may further include separating the semiconductor chip from the wafer after the capacitive structure has been formed.

According to various embodiments, a method for processing a semiconductor chip may include forming a capacitive structure on a side wall of the semiconductor chip; wherein the capacitive structure may include a semiconductor electrode formed by a doped portion of the side wall, a metal electrode disposed over the side wall, and an electrically insulating layer disposed between the metal electrode and the side wall; forming a first contact pad that is in electrical contact with the metal electrode; and forming a second contact pad in electrical contact with the semiconductor electrode, wherein the first and second contact pads may be configured to be electrically coupled to a measuring device to apply a voltage between the metal electrode and the semiconductor electrode.

According to various embodiments, forming the electrically insulating layer may include oxidizing the sidewall of the semiconductor chip. The side wall of the semiconductor chip can contain a side wall of the semiconductor body or a side wall of the semiconductor body region.

The side wall of the semiconductor chip can include a side side of the semiconductor chip, a side side of the semiconductor body or a side side of the semiconductor body region.

According to various embodiments, the semiconductor chip can be part of a wafer and the method can furthermore separate the Contain semiconductor chips from the wafer after forming the capacitive structure.

According to various embodiments, a method for processing a wafer may include: forming a trench between a first semiconductor chip of the wafer and a second semiconductor chip of the wafer; wherein the trench may extend substantially from a first surface of the wafer to a second surface of the wafer opposite the first surface; Forming a capacitive structure in the trench; and separating the first semiconductor chip from the second semiconductor chip, wherein the capacitive structure can remain attached to the first semiconductor chip.

According to various embodiments, a capacitive structure may include at least two electrode areas, e.g. a first electrode area and a second area. Furthermore, a capacitive structure may contain more than two electrode areas, e.g. three electrode areas, e.g. a first electrode area, a second area and a third area. Furthermore, a capacitive structure can have four electrode regions, five electrode regions, or more than five electrode regions, e.g. ten electrode areas, e.g. twenty electrode areas included.

According to various embodiments, the method can further include: forming a further capacitive structure in the trench, which contains, for example, at least two further electrodes; wherein the first semiconductor chip can be separated from the second semiconductor chip, so that the further capacitive structure remains on the second semiconductor chip. The further capacitive structure can contain the third electrode region and the further electrically insulating region (see for example 8B) ,

The first capacitive structure can at least substantially surround the first semiconductor chip, wherein the second capacitive structure can at least substantially surround the second semiconductor chip.

According to various embodiments, a method for processing a wafer may include forming a trench next to a semiconductor chip of the wafer; wherein the trench may extend substantially from a first surface of the wafer to a second surface of the wafer opposite the first surface; forming a capacitive structure in the trench, the capacitive structure comprising a first electrode region, a second electrode region arranged on a first side of the first electrode region, a third electrode region arranged on a second side of the first electrode region, a first electrically insulating one May include an area extending between the first electrode area and the second electrode area and a second electrically insulating area extending between the first electrode area and the third electrode area; wherein at least one of the first, second and third electrode regions extends substantially from the first surface of the wafer to the second surface of the wafer opposite the first surface; and cutting the wafer through the trench, wherein at least the first electrode region and the second electrode region can remain attached to the semiconductor chip.

According to various embodiments, the first surface of the wafer may include a first surface of the semiconductor chip or first surface of the semiconductor body region, e.g. when the semiconductor chip is part of the wafer. The second surface of the wafer may include a second surface of the semiconductor chip or a second surface of the semiconductor body region, e.g. the semiconductor chip is part of the wafer.

According to various embodiments, a method for processing a wafer may include forming a trench next to a semiconductor chip of the wafer; forming a crack absorption area in the trench, wherein the crack absorption area may extend from the first surface in a direction toward the second surface; wherein the crack absorption area can contain an elongation at break greater than the semiconductor chip. For example, the crack absorption area may contain a greater elongation at break than the semiconductor body area.

According to various embodiments, a method of processing a semiconductor chip may include: forming a trench in the semiconductor chip; wherein the trench can at least partially surround a semiconductor body region of the semiconductor chip and can extend from a first surface of the semiconductor body region in a direction to a second surface of the semiconductor body region opposite the first surface; Forming a crack absorption area in the trench, wherein the crack absorption area can contain a greater elongation at break than the semiconductor body area.

• 1A und 1B jeweils einen Halbleiterchip zeigen, der einen herkömmlichen Risssensor enthält;
• 2A bis 2C jeweils einen Halbleiterchip gemäß verschiedenen Ausführungsformen zeigen;
• 3A und 3B jeweils einen Halbleiterchip gemäß verschiedenen Ausführungsformen zeigen;
• 4A bis 4F jeweils einen Halbleiterchip in verschiedenen Stufen während einer Bearbeitung gemäß verschiedenen Ausführungsformen zeigen;
• 5A bis 5C jeweils einen Halbleiterchip in verschiedenen Stufen während einer Bearbeitung gemäß verschiedenen Ausführungsformen zeigen;
• 6A bis 6C jeweils einen Halbleiterchip in verschiedenen Stufen während einer Bearbeitung gemäß verschiedenen Ausführungsformen zeigen;
• 7A bis 7C jeweils einen Halbleiterchip in verschiedenen Stufen während einer Bearbeitung gemäß verschiedenen Ausführungsformen zeigen;
• 8A und 8B jeweils einen Halbleiterchip in verschiedenen Stufen während einer Bearbeitung gemäß verschiedenen Ausführungsformen zeigen;
• 9A und 9B jeweils einen Halbleiterchip gemäß verschiedenen Ausführungsformen zeigen;
• 10A bis 10C jeweils einen Halbleiterchip in verschiedenen Stufen während einer Bearbeitung gemäß verschiedenen Ausführungsformen zeigen;
• 11A bis 11C jeweils einen Halbleiterchip in verschiedenen Stufen während einer Bearbeitung gemäß verschiedenen Ausführungsformen zeigen;
• 12 ein schematisches Flussdiagramm eines Verfahrens zur Bearbeitung eines Halbleiterchips gemäß verschiedenen Ausführungsformen zeigt;
• 13 ein schematisches Flussdiagramm eines Verfahrens zur Bearbeitung eines Halbleiterchips gemäß verschiedenen Ausführungsformen zeigt;
• 14 ein schematisches Flussdiagramm eines Verfahrens zur Bearbeitung eines Wafers gemäß verschiedenen Ausführungsformen zeigt;
• 15 ein schematisches Flussdiagramm eines Verfahrens zur Bearbeitung eines Wafers gemäß verschiedenen Ausführungsformen zeigt;
• 16 ein schematisches Flussdiagramm eines Verfahrens zur Bearbeitung eines Wafers gemäß verschiedenen Ausführungsformen zeigt; und
• 17 ein schematisches Flussdiagramm eines Verfahrens zur Bearbeitung eines Halbleiterchips gemäß verschiedenen Ausführungsformen zeigt.

In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not to scale, rather the focus is generally on illustrating the principles of the invention. In the following description, various embodiments of the invention are illustrated with reference to the following drawings, in which:

• 1A and 1B each show a semiconductor chip containing a conventional crack sensor;
• 2A to 2C each show a semiconductor chip according to various embodiments;
• 3A and 3B each show a semiconductor chip according to various embodiments;
• 4A to 4F each show a semiconductor chip in different stages during processing according to various embodiments;
• 5A to 5C each show a semiconductor chip in different stages during processing according to various embodiments;
• 6A to 6C each show a semiconductor chip in different stages during processing according to various embodiments;
• 7A to 7C each show a semiconductor chip in different stages during processing according to various embodiments;
• 8A and 8B each show a semiconductor chip in different stages during processing according to various embodiments;
• 9A and 9B each show a semiconductor chip according to various embodiments;
• 10A to 10C each show a semiconductor chip in different stages during processing according to various embodiments;
• 11A to 11C each show a semiconductor chip in different stages during processing according to various embodiments;
• 12 5 shows a schematic flow diagram of a method for processing a semiconductor chip according to various embodiments;
• 13 5 shows a schematic flow diagram of a method for processing a semiconductor chip according to various embodiments;
• 14 5 shows a schematic flow diagram of a method for processing a wafer in accordance with various embodiments;
• 15 5 shows a schematic flow diagram of a method for processing a wafer in accordance with various embodiments;
• 16 5 shows a schematic flow diagram of a method for processing a wafer in accordance with various embodiments; and
• 17 5 shows a schematic flow diagram of a method for processing a semiconductor chip in accordance with various embodiments.

The following detailed description refers to the accompanying drawings which show, by way of example, specific details and embodiments in which the invention may be carried out.

The word “exemplary” is used here to mean “serving as an example, case, or illustration”. Each embodiment or design described here as “exemplary” is not necessarily to be interpreted as preferred or advantageous over other embodiments or designs.

The word "over" used with respect to a deposited material that is formed "over" a side or surface can be used here to mean that the deposited material "directly on", e.g. can be formed in direct contact with, the said side or surface. The word "about" used with respect to a deposited material that is formed "over" a side or surface can be used here to mean that the deposited material is "indirectly" formed on the named side or surface can, one or more additional layer (s) can be arranged between said side or surface and the deposited material.

The term "sideways", which is used to refer to the "lateral" expansion of a structure (or a substrate, a wafer or a carrier), or "sideways" next to, can mean an expansion or a positional relationship along a surface a substrate, a wafer or a carrier. This means that a surface of a substrate (eg a surface of a carrier or a surface of a wafer) can serve as a reference, which is generally referred to as the main processing surface of the substrate (or the main processing surface of the carrier or wafer). Furthermore, the term "width" used with respect to a "width" of a structure (or a structural element) can be used here to mean the lateral extent of a structure. Furthermore, the term "height" used with respect to a height of a structure (or a structural element) is used here to mean an expansion of a structure along a direction perpendicular to the surface of a substrate (eg perpendicular to the main machining surface of a substrate). The term "thickness" used in relation to a "thickness" of a layer can be used here to mean the spatial extent of the layer perpendicular to the surface of the support (of the material) on which the layer is deposited , If the surface of the overlay is parallel to the surface of the substrate (eg, the main machining surface), the "thickness" of the layer deposited on the overlay can be the same as the height of the layer. Furthermore, a "vertical" structure may be referred to as a structure that extends in a direction perpendicular to the lateral direction (eg perpendicular to the main machining surface of a substrate) and a "vertical" extent may be referred to as an extension along a direction perpendicular to the lateral direction (eg an extension perpendicular to the main processing surface of a substrate).

The term "forming" with respect to a layer, material or area can refer to positioning, arranging or depositing the layer, material or area. A method of forming e.g. a layer, a material, an area, etc., can contain various deposition processes, which can be among others: chemical vapor deposition, physical vapor deposition (e.g. for dielectric materials), electrodeposition (also known as electroplating, e.g. for metals or metal alloys) or spin coating (e.g. for fluid materials). In general, vapor phase deposition can be carried out by sputtering, laser ablation, arc evaporation or heat evaporation. A method of forming metals can include metal plating, e.g. Electroplating or chemical plating included.

The term "forming" with respect to a layer, a material or an area can also include a chemical reaction or production of a chemical composition, where e.g. at least part of the layer, material or area is formed by reshaping a set of chemical substances into the chemical composition. For example, "formation" can include changing the positions of electrons by breaking or forming chemical bonds between atoms of the set of chemical substances. "Formation" may also include oxidation and reduction, complex formation, precipitation, an acid-base reaction, a solid state reaction, substitution or doping, addition and elimination, diffusion or a photochemical reaction. For example, "education" can change the chemical and physical properties of the set of chemical substances that chemically form part of the layer, material, or area, which may include electrical conductivity, phase composition, optical properties, etc. For example, "education" can include applying a chemical reagent to a parent compound to change the chemical and physical properties of the parent compound.

According to various embodiments, a semiconductor chip can be diced from a wafer by removing material from a saw slot area of the wafer (also referred to as dicing or cutting the wafer). For example, material removal from the saw slot area of the wafer can be done by scribing and breaking, splitting, cutting with a blade, or mechanical sawing (e.g. using a saw). In other words, the semiconductor chip can be diced by a wafer dicing process. After the wafer dicing process, the semiconductor chip can be electrically connected and, e.g. by molding materials, encapsulated in a chip carrier (also referred to as a chip package) which is then suitable for use in electronic devices such as computers. For example, the semiconductor chip can be bonded to a chip carrier by wires and the chip carrier can be soldered to a printed circuit board.

According to various embodiments, a semiconductor chip may include a semiconductor body made of semiconductor materials of various types, including a Group IV semiconductor (e.g. silicon or germanium), a compound semiconductor, e.g. a Group III-V compound semiconductor (e.g., gallium arsenide) or other types including, for example, Group III semiconductors, Group V semiconductors, or polymers. In one embodiment, the semiconductor body consists of silicon (doped or undoped), in an alternative embodiment the semiconductor body is a silicon-on-insulator (SOI) wafer. Alternatively, any other suitable semiconductor material can be used for the semiconductor body, for example semiconductor connection material such as gallium phosphide (GaP), indium phosphide (InP), but also any suitable ternary semiconductor connection material or quaternary semiconductor connection material such as indium gallium arsenide (InGaAs).

According to various embodiments, a semiconductor chip can furthermore contain a passivation layer for protecting the semiconductor body of the semiconductor chip from environmental influences, for example oxidation. The passivation layer can be a metal oxide, contain an oxide of the semiconductor body, for example silicon oxide, a nitride, for example silicon nitride, a polymer, for example benzocyclobutene (BCB) or polyimide (PI), a resin, a photoresist or a dielectric material.

According to various embodiments, a semiconductor chip can contain a sealing ring for electrically grounding the semiconductor body of the semiconductor chip. The sealing ring can contain an electrical conductor (power metal) which runs on the semiconductor body and is electrically connected to a line structure in the semiconductor body. The line structure may include a metal or a metal alloy that extends into the semiconductor body. Furthermore, the sealing ring can have a protective structure, e.g. a cover layer containing imide.

According to various embodiments, a metal can contain an element from the following group of elements: aluminum, copper, nickel, magnesium, chromium, iron, zinc, tin, gold, silver, iridium, platinum or titanium. According to various embodiments, a metal alloy may contain one element or more than one element from the group of elements. For example, a metal alloy can be an intermetallic compound, e.g. contain an intermetallic compound of gold and aluminum, an intermetallic compound of copper and aluminum, an intermetallic compound of copper and zinc ("brass") or an intermetallic compound of copper and tin ("bronze").

According to various embodiments, a semiconductor chip may include an active chip area. The active chip area may be located in part of the semiconductor body (in other words, a semiconductor body region) and may include one or more transistors, resistors and capacitors that are designed to perform arithmetic or memory operations. The active chip area can be a few micrometers thick and can extend along an upper side of the semiconductor body. In other words, the active chip area can be part of a semiconductor body region or can relate to a semiconductor body region. A bottom part of the semiconductor body region can extend under the active chip area. The bottom part of the semiconductor body (also referred to as the base layer) can be thicker than the active chip area, e.g. several hundred micrometers thick, and may extend along a bottom side of the semiconductor body.

1A shows a semiconductor chip 100 which is a conventional crack sensor 130 contains, in a cross-sectional view during the processing of the semiconductor chip 100 , for example during a separation 112 of the semiconductor chip 100 from a wafer (compare e.g. 7A) by removing 112 of material from a saw slot area 142 of the wafer, in other words, during the cutting 112 of the wafer.

The semiconductor chip 100 can be a semiconductor body 102 with a semiconductor body area 111 contain. For example, the semiconductor body area 111 an active area of the semiconductor chip 100 contain. Furthermore, the semiconductor chip 100 a passivation layer 104 and a sealing ring 120 with a protective structure 122 over a power metal 124 included, the power metal 124 electrically to a line structure 126 connected.

During the processing of the semiconductor chip 100 (or a device that the semiconductor chip 100 operates) can crack a chip 110 (also as a crack 110 designated) occur, for example the chip crack 110 on a side wall 102s of the semiconductor chip 100 or a side wall 102s of the semiconductor body area 111 occur and get off the side wall 102s to the inside of the chip 100 spread. Such a chip crack 100 can due to numerous reasons and during numerous processes for processing the semiconductor chip 100 , for example during the cutting of the wafer or the handling of the semiconductor chip 100 (eg through a pick-and-place application) or the soldering of the semiconductor chip 100 (or a device that the semiconductor chip 100 operates), as described here.

The length of a chip crack 110 directly after processing the semiconductor chip 100 can be short and thus the chip crack 110 not yet in the semiconductor body area 111 (the active area) or one of the circuit components in the semiconductor body region 111 have spread. The length of a chip crack 110 can, however, during further processing of the semiconductor chip 100 or the operation of the semiconductor chip 100 increase itself, for example after encapsulating the semiconductor chip 100 and use of the semiconductor chip 100 in one device. As in 1A shown, there may be a chip crack 110 in the semiconductor body 102 of a semiconductor chip 100 spread 110a , further into the active chip area 111 spread 110b and can be in the active chip area 111 Pop up. Conventional screening methods for detecting chip cracks 110 , for example before the behavior of the semiconductor chip 100 or the functionality of the semiconductor chip 100 can be time-consuming, complicated, and unreliable.

A conventional screening method for electrically detecting a crack propagation 110 can be a stress test, in which, for example, the semiconductor chip 100 is loaded at elevated temperatures, a so-called stoving Stress test or applying multiple temperature cycles to the semiconductor chip 100 included by reflow soldering simulation. Applying the stress test to a semiconductor chip 100 with a chip crack 110 can spread the chip crack 110 cause until the chip crack 110 into a crack detection area, e.g. the active area 111 of the semiconductor chip 100 , arrives where the chip crack 110 can be detected and filtered by electrical test methods (for example by detecting a malfunction of circuit components in the active area 111 ).

Applying a stress test may be insufficient, for example, a test duration may be too short to cause chip crack propagation 110 trigger that continues into the crack detection area, through the active area 111 is provided. Thus, a chip crack 110 remain undetected, although stress tests on a semiconductor chip 100 were applied. The semiconductor chip 100 may be due to an undetected chip crack 110 fail because of the undetected chip crack 110 after operation of the semiconductor chip 100 over a period of time in the active chip area 111 can spread. The semiconductor chip 100 can fail, causing undefined behavior of the semiconductor chip 100 is caused.

In addition to chip cracks 110 that in the semiconductor chip 100 during the processing of the semiconductor chip 100 are present (e.g. if a stress test was insufficient, the chip crack 110 to detect), chip cracks 110 also during the operation of the semiconductor chip 100 (or a device that the semiconductor chip 100 operates), for example during a continuous operation or after the operation of the semiconductor chip 100 occur over a period of time that is longer than conventional stress tests can simulate.

A conventional crack sensor 130 (also referred to as a perimeter 130 ) for detecting chip cracks 110 may include a metal wire that runs along the surface of the semiconductor chip 100 (eg the surface of the silicon in the semiconductor body 102 ) runs, and can the active chip area 111 surround. A chip crack 110 which is the metal wire of the circumference 130 impaired, a change in the resistance of the circumference 130 cause and therefore the chip crack 110 based on the resistance of the circumference 130 be recorded. In response to a detected chip crack 110 can the semiconductor chip 100 (or a product that includes the semiconductor chip 100 operates) are switched to a correct operating mode in order to undefined behavior of the semiconductor chip 100 or avoid critical situations. For example, the semiconductor chip 100 be switched to a standby mode or switched off.

In other words, an undetected crack 110 can spread in the semiconductor chip during operation of the semiconductor chip, for example in an electrical device, as a result of which undefined behavior of the semiconductor chip or the electrical device is caused. An undefined behavior of the semiconductor chip or the device can lead to critical, for example life-threatening, situations if the undefined behavior remains undetected. For example, if the semiconductor chip is used in a car, undefined behavior could result in airbags being activated unintentionally.

1B shows a semiconductor chip 100 which is a conventional crack sensor 130 contains, in a cross-sectional view, with a chip crack 110 in the semiconductor body area 111 may have spread. Although a perimeter 130 used, it may be unsure whether the chip crack 110 is captured because the perimeter 130 only on the surface of the semiconductor chip 100 extends. Therefore, the chip crack 110 possibly on the circumference 130 walk past (without the metal wire of the circumference 130 to affect), such as by arrow 110c in 1B shown. As in an exemplary form in 1B shown, the chip crack 110 below the perimeter 130 run and get into the active area 111 spread without being recorded.

2A shows a semiconductor chip 200 according to various embodiments in a cross-sectional view along a line 201 (please refer 2 B or 2C ). The semiconductor chip 200 can be a capacitive structure 230 for detecting crack propagation in the semiconductor chip 200 contain. The semiconductor chip 200 can be a semiconductor body 102 with a semiconductor body area 111 contain, in other words, part 111 of the semiconductor body 102 ,

According to various embodiments, the semiconductor body region 111 an active area or an integrated circuit of the semiconductor chip 200 contain. The semiconductor body area 111 can be a first surface 102t (e.g. an upper page 102t of the semiconductor body area 111 ) and a second surface 102b (e.g. a lower page 102b of the semiconductor body area 111 ) compared to the first surface 102t contain. In other words, the semiconductor body area 111 can be between the first surface 102t and the second surface 102b extend.

According to various embodiments, the capacitive structure 230 a first electrode area 230a included, which is at least substantially from the first surface 102t to the second surface 102b extends. The first electrode region 230a can be an electrically conductive material, for example a metal, a metal alloy, a silicide (for example titanium silicide, molybdenum silicide, tantalum silicide or tungsten silicide), a conductive polymer, a polycrystalline semiconductor or a doped semiconductor, for example tungsten, aluminum, copper, polycrystalline silicon or doped silicon , contain. An electrically conductive material can have an electrical conductivity (measured at room temperature and constant electric field direction) of more than about 1 S / m, for example more than about 10 ² S / m, for example more than about 10 ⁴ S / m.

According to various embodiments, an extension from the first surface 102t to the second surface 102b as (vertical) expansion through the semiconductor body 102 of the semiconductor chip 200 be understood. An area, for example the first electrode area 230a that is at least essentially from the first surface 102t to the second surface 102b extends as an extension of the area in one direction from the first surface 102t to the second surface 102b can be understood, for example in the direction perpendicular to the first surface 102t (in other words, a vertical extension). The extent of the area, which is at least substantially from the first surface 102t to the second surface 102b extends, can be more than about 80% of a distance between the first surface 102t and the second surface 102b towards the first surface 102t to the second surface 102b be, for example, more than about 90%, for example, more than about 95%. According to various embodiments, the area can extend completely from the first surface 102t to the second surface 102b extend. In other words, the area can extend through the entire thickness of the semiconductor body 102 or the semiconductor body region 111 extend.

According to various embodiments, the capacitive structure 230 further a second electrode area 230b included next to the first electrode area 230a is arranged. The second electrode area 230b may contain an electrically conductive material, similar to the first electrode area 230a , The first electrode area 230a can be at a distance from the second electrode area 230b be spaced.

According to various embodiments, the capacitive structure 230 also an electrically insulating area 230i included, which is between the first electrode area 230a and the second electrode area 230b extends. The electrically insulating area 230i can contain an electrically insulating material, for example a dielectric material, for example a dielectric with a high dielectric constant (high-k) or a dielectric with a low dielectric constant (low-k). For example, the electrically insulating material may be a resin, a photoresist, a semiconductor oxide, a metal oxide, a ceramic, a semiconductor nitride, a metal nitride, a semiconductor carbide, a metal carbide, a glass, for example fluorosilicate glass (FSG), a silicate, for example hafnium silicate or zirconium silicate , a silicon oxynitride, a transition metal oxide, for example hafnium dioxide or zirconium dioxide, an electrically insulating polymer, for example benzocyclobutene (BCB) or polyimide (PI), or an undoped semiconductor (for example undoped silicon), for example an undoped part of the semiconductor body 102 between the first electrode area 230a and the second electrode area 230b , for example an oxidized part of the semiconductor body 102 between the first electrode area 230a and the second electrode area 230b contain. An electrically insulating material can have an electrical conductivity (measured at room temperature and constant electric field direction) of less than about 10 ^-2 S / m, for example less than about 10 ^-5 S / m, for example less than about 10 ^-7 S / m ,

According to various embodiments, the electrically insulating area 230i for electrically isolating the first electrode area 230a from the second electrode area 230b be designed. Furthermore, the electrically insulating area 230i electrical properties, e.g. a dielectric strength or a leakage current, of the capacitive structure 230 define. In other words, the electrically insulating area 230i can be an electric field between the first electrode area 230a and the second electrode area 230b withstand up to a certain field strength without collapsing (in other words, without experiencing a failure of its insulating properties, e.g. without essentially changing its electrical conductivity). The electric field between the first electrode area 230a and the second electrode area 230b can by applying an electrical voltage between the first electrode area 230a and the second electrode area 230b , for example, a bias can be provided.

According to various embodiments, a chip crack 110 that is in the first electrode area 230a or in the electrically insulating area 230i spreads the electrical properties of the capacitive structure 230 to change. For example, the dielectric strength of the capacitive structure 230 changed (eg reduced) if the electrically insulating area 230i is impaired, for example due to a crack 110 that is in the electrically insulating area 230i spreads.

2 B shows a semiconductor chip 200 according to various embodiments in a plan view or in a cross-sectional view along a line 205 (please refer 2A) , The first electrode area 230a and the second electrode area 230b can the semiconductor body area 111 in a side Direction. In other words, the capacitive structure 230 can be formed as a ring structure, for example the capacitive structure 230 extend along a closed path, the closed path being the semiconductor body region 111 surrounds.

The first electrode area 230a can the second electrode area 230b surrounded as in 2 B shown. Alternatively, the second electrode area 230b according to various embodiments, the first electrode area 230a partially surrounded. Both designs can lead to a capacitive structure 230 lead, at least in part, to the semiconductor body area 111 surrounds in a sideways direction.

A capacitive structure 230 may be undetected chip cracks according to various embodiments 110 overcome that as described here in the semiconductor body area 111 spread. Stress tests with the semiconductor chip 200 applied to spread a chip crack 110 Continuing into the crack detection area may become unnecessary as the crack detection area is affected by the capacitive structure 230 , as in 2A and 2 B shown, is provided, can expand into the area where a chip crack propagates 110 occurs initially. A chip crack 110 that is in the semiconductor body area 111 can spread, at least in part, through the capacitive structure 230 have to go to the semiconductor body area 111 penetrate. For example, chip cracks 110 , which run below the chip detection area, can be avoided because of the capacitive structure 230 essentially through the semiconductor body 102 can extend.

2C shows a semiconductor chip 250 according to various embodiments in a plan view or in a cross-sectional view along a line 205 (please refer 2A) , The first electrode area 230a and the second electrode area 230b can spread out along the side wall 102s of the semiconductor body 102 extend. A chip crack 110 that on the side wall 102s of the semiconductor body 102 (eg after sawing into the wafer) can occur due to the capacitive structure 230 go because of the capacitive structure 230 next to the side wall 102s of the semiconductor body 102 can be arranged. An occurrence of chip cracks can also occur 110 that run below the chip detection area can be reduced because of the capacitive structure 230 essentially from the first surface 102t to the second surface 102b as described here.

According to various embodiments, the capacitive structure 230 be formed as a ring structure that has an opening 230o or a crack 230o contains. The opening 230o can be an opening width (eg a gap width) of the capacitive structure 230 define. The opening width can be the distance between the parts of the capacitive structure 230 next to the opening 230o correspond. The opening 230o can provide an area (for example a passage) through which lines are routed in the semiconductor body 102 are embedded (or other embedded circuit structures) from outside the semiconductor body region 111 in the semiconductor body area 111 can extend.

According to various embodiments, a region, for example the first or the second electrode region 230a . 230b or the capacitive structure 230 that is at least partially the semiconductor body area 111 surrounds to be understood as an area that has an opening 230o contains, which interrupts the path along which the area is the semiconductor body area 111 surrounds. The width of the opening 230o may be less than the length of the path along which the area is the semiconductor body area 111 surrounds. The width of the opening 230o can be, for example, less than about 50%, for example less than about 25%, for example less than about 10% of the length of the path that the semiconductor body region 111 surrounds. An area that is at least partially the semiconductor body area 111 surrounds can also be understood as an area that has more than one opening 230o contains, for example, two, three, four or more than four openings 230o , According to various embodiments, at least partially surrounding the semiconductor body region 111s the case of completely surrounding the semiconductor body region 111 contain.

3A shows a semiconductor chip 300 according to various embodiments in a top view (similar 2 B and 2C ). The capacitive structure 230 can be electrically connected to a measuring circuit 310 be coupled. The measuring circuit 310 can be used to detect a chip crack that is in the capacitive structure 230 spread, be designed. The measuring circuit 310 can in the semiconductor chip 300 be integrated, for example in the semiconductor body area 111 be arranged. Alternatively, the measuring circuit 310 from the semiconductor chip 300 be separated, for example the measuring circuit 310 Be part of your own circuit, for example part of an external chip that electrically connects to the semiconductor chip 300 is coupled, for example a detection unit or a measuring device 310 (also referred to as a monitoring unit or watchdog).

The capacitive structure 230 can be a first electrode area 230a , a second electrode area 230b and an electrically insulating area 230i between the first electrode area 230a and the second electrode area 230b (not shown in 3A , see e.g. 2A to 2C ) contain. According to various embodiments, the measuring circuit 310 for electrical analysis of the capacitive structure 230 be designed, for example measuring the dielectric strength of the capacitive structure 230 or the leakage current of the capacitive structure 230 , in other words, between the first electrode area 230a and the second electrode area 230b , Therefore, the measuring circuit 310 for applying a voltage between the first electrode area 230a and the second electrode area 230b and measuring a parameter of the capacitive structure, for example a current between the first electrode region 230a and the second electrode area 230b , be designed, the current corresponding to the voltage. The measuring circuit 310 can also be used to identify a chip crack that is in the capacitive structure 230 or the semiconductor body area 111 spreads, be designed based on the measured current.

Alternatively, according to various embodiments, the measuring circuit 310 for applying a current between the first electrode area 230a and the second electrode area 230b (eg a bias current) and measuring a parameter of the capacitive structure 230 be designed, for example a voltage between the first electrode region 230a and the second electrode area 230b , where the voltage corresponds to the current. The measuring circuit 310 can also be used to identify a chip crack that is in the capacitive structure 230 or the semiconductor body area 111 spreads, be designed based on the measured voltage.

In other words, the measurement circuit 310 can be used to measure a value of the characteristic of the capacitive structure 230 by electrically characterizing the capacitive structure 230 be designed. Furthermore, the measuring circuit 310 be designed to determine a crack on the basis of the measured value of the parameter.

A layout of the measurement circuit 310 according to various embodiments is in the form of an example in 3A shown. Aside from the in 3A shown measuring circuit 310 can use other layouts of the measurement circuit 310 for electrical characterization of the capacitive structure 230 be used.

As in 3A shown, a measuring circuit 310 a first connector 310a that is electrically connected to the first electrode area 230a can be coupled, and a second connector 310b that is electrically connected to the second electrode area 230b can be coupled. Alternatively, the first connector 310a electrically to the second electrode area 230b be coupled and the second connector 310b can be electrically connected to the first electrode area 230a be coupled. Furthermore, the measuring circuit 310 a voltage source 312b , a comparator 316 and additional circuit components 314 included (e.g. a resistor, a capacitor, a diode, an inductor or other electrical components).

According to various embodiments, the measuring circuit 310 for applying a bias voltage between the first electrode area 230a and the second electrode area 230b be designed. Therefore, the first connector 310a to the voltage source 312b be coupled (for example to supply the bias) and the second connector 310b can be coupled to an electrical ground.

Furthermore, the first connector 310a to a first input of the comparator 316 be coupled. The comparator 316 can be used to compare an electrical voltage applied to the first input of the comparator 316 is coupled with a reference voltage 312r connected to a second input of the comparator 316 is coupled to be designed. The comparator 316 can also be configured to output a first signal if there is a voltage difference between the first and the second input of the comparator 316 is greater than a predetermined difference, and for outputting a second signal when the voltage difference between the first and the second input of the comparator 316 is less than the predetermined difference.

A chip crack that is in the capacitive structure 230 for example, the dielectric strength of the electrically insulating region 230i change, resulting in a change in the voltage difference between the first and second inputs of the comparator 316 leads. In response to the chip crack that is in the capacitive structure 230 spreads, the measuring circuit 310 output the first signal that can be further processed (or calculated) to determine the operating mode of the semiconductor chip 300 to change. The additional circuit components 314 can be used to adjust the detection behavior (also referred to as output behavior) of the measuring circuit 310 be designed, for example a detection time, detection delay or detection sensitivity.

According to various embodiments, the first signal and the second signal can be part of a watchdog signal that the measuring circuit 310 can provide. The watchdog signal can be further processed (or calculated) to determine the operating mode of the semiconductor chip 300 to control (e.g. to change).

According to various embodiments, a semiconductor chip can be part of a wafer 702 his, wherein the semiconductor chip from a saw slot area 142 (in a lateral direction) of the wafer 702 (not shown, see for example semiconductor chip 700 in 7A) can be surrounded. In the Säschllitz area 142 can the wafer 702 destined to be cut, sawn, milled, cut, etc. to remove the semiconductor chip from the wafer 702 (e.g. see 7A) to isolate. For the detection of chip cracks during the separation of the semiconductor chip from the wafer 702 can be generated, the capacitive structure 230 between the Säschllitz area 142 and the semiconductor body area 111 of the semiconductor chip.

According to various embodiments, the capacitive structure 230 between the Säschllitz area 142 and the sealing ring 120 of the semiconductor chip can be arranged as in 3A shown. Alternatively, according to various embodiments, the capacitive structure 230 between the sealing ring 120 of the semiconductor chip and the semiconductor body region 111 of the semiconductor chip.

3B shows a semiconductor chip 350 according to various embodiments in a top view (similar 2 B and 2C ), the semiconductor chip 350 an additional capacitive structure 330 can contain, at least partially, an additional semiconductor body region 311 of the semiconductor chip 350 can surround in a lateral direction. In one or more embodiments, the additional semiconductor body region may be 311 from the semiconductor body area 111 be surrounded.

Likewise, according to various embodiments, a semiconductor chip can contain a plurality of capacitive structures, wherein each capacitive structure of the plurality of capacitive structures can at least partially surround at least one semiconductor body region.

According to various embodiments, a first capacitive structure (e.g. 230 ) of the several capacitive structures a second capacitive structure (e.g. 330 ) surrounding the several capacitive structures, as in the form of an example in 3B is shown. Alternatively, according to various embodiments, the first capacitive structure (e.g. 230 ) of the multiple capacitive structures and the second capacitive structure (e.g. 330 ) of the several capacitive structures can be arranged side by side.

4A to 4F each show a semiconductor chip 400 in a cross-sectional view, for example in a cross-sectional view along a line 201 or in a cross-sectional view similar to a cross-sectional view along a line 201 or 301 , during processing of the semiconductor chip 400 , for example during a process for forming a capacitive structure 230 according to various embodiments.

4A shows the semiconductor chip 400 in a cross-sectional view in a processing stage. For example, the semiconductor chip 400 according to various embodiments, be a semiconductor chip in an initial processing stage, the semiconductor chip 400 to form an integrated circuit structure in the semiconductor chip 400 is determined (for example in a semiconductor body region 111 ). Alternatively, the semiconductor chip 400 according to various embodiments, be a fully machined semiconductor chip that includes an integrated circuit structure. For example, the semiconductor chip 400 part of a wafer 702 and can be designed from the wafer 702 to be separated, or the semiconductor chip 400 can be part of a wafer level package.

The semiconductor chip 400 can be a semiconductor body 102 with a semiconductor body area 111 contain. According to various embodiments, at least one trench 430 , eg a blind trench 430 (analogous to a blind hole), in the semiconductor body 102 next to the semiconductor body area 111 be formed. The ditch 430 can be a sidewall 430s in the semiconductor body field 111 define.

The ditch 430 can be formed so that the trench 430 from the first surface 302T (eg an upper surface) of the semiconductor chip 400 in the semiconductor body 102 can extend. In other words, the ditch 430 can be formed so that the trench 430 vertically into the semiconductor body 102 can extend. The ditch 430 can be formed by performing any method known in semiconductor technology, such as etching or sawing. The ditch 430 can be formed so that it is in a bottom part of the semiconductor body area 111 (also known as a deep trench). For example, the trench 430 be formed so that it is at least 50% of the thickness of the semiconductor body 102 , for example at least 60%, for example at least 70%, for example at least 80%, for example at least 90%.

According to various embodiments, the trench can be 430 at least essentially from the first surface 302T of the semiconductor body 102 to a second surface 302b of the semiconductor body 102 extend, the second surface 302b opposite the first surface 302T lies. The ditch 430 can be formed without going to the second surface 302b break through. The ditch 430 can be formed so that the trench 430 at least partially the semiconductor body area 111 of the semiconductor chip 400 can surround.

According to various embodiments, a doping material 402 (which can serve as a dopant donor) in the trench 430 be arranged. The doping material 402 can be arranged so that the side wall 430s can be at least substantially covered with the doping material. For example, the trench 430 at least essentially with the doping material 402 be filled as in 4B is shown.

According to various embodiments, “at least essentially filled” is to be understood to mean that part of an inner volume of a cavity, a depression or a trench is filled with a material, e.g. more than about 70% of the interior volume, e.g. more than about 80%, e.g. more than about 90%, e.g. about 100%.

The doping material 402 may contain a dopant (also referred to as a dopant). According to various embodiments, if the side wall 430s Contains group IV semiconductors (eg silicon or germanium), the doping material 402 contain a Group III element (p-type dopant) or a Group V element (n-type dopant), for example a chemical element from the following group of chemical elements: boron, arsenic, phosphorus, antimony, aluminum or gallium. Alternatively, according to various embodiments, if the side wall 430s contains a III-V compound semiconductor (eg gallium arsenide), the doping material 402 contain a chemical element from the following group of chemical elements: sulfur, selenium, tellurium, silicon, germanium, magnesium, zinc, cadmium. For example, the dopant 402 contain a glass (for example a boron glass) which contains boron as a dopant.

The dopant can be used to change the electrical properties of the side wall 430s be designed, eg load carriers in the side wall 430s use if the dopant in the side wall 430s is introduced. The dopant for doping at least the side wall 430s be designed to be a semiconductor 430a of the first doping type (also as the first semiconductor region 430a of a first conductivity type), for example an n-type semiconductor or a p-type semiconductor, in other words, around a doped side wall 430a from the side wall 430s to form as in 4C shown. In other words, the dopant can dope at least the side wall 430s be designed to be a first semiconductor region 430a a first conductivity type from the side wall 430s to build.

For example, the dopant 402 be annealed to the dopant in the sidewall 430s to be introduced, for example by temperature-induced diffusion 402d (also referred to as diffusing out) of the dopant into the side wall 403s , After introducing the dopant into the side wall 430s can the doping material 402 removed, for example, the doped side wall 430a expose. The endowed side wall 430a can be part of the first electrode area 230a his.

Alternatively, forming the first doping type semiconductor 430a implanting a dopant into the first electrode area 230a , for example by ion implantation or other known doping methods.

Furthermore, a filling material 432 , for example a polycrystalline semiconductor, for example polycrystalline silicon, or another electrically conductive material, for example a metal or a metal alloy, in the trench 430 be arranged as in 4D shown. The filling material 432 can be used for electrical contact with the doped sidewall 430a be designed. The filling material 432 can be part of the first electrode area 230a his.

Furthermore, a semiconductor of the second doping type 430b , for example an n-type semiconductor or a p-type semiconductor (also as a second semiconductor region 430b of a second conductivity type), close, for example next to, the semiconductor of the first doping type 430a be formed as in 4E shown. The formation of the second doping type semiconductor 430b may include forming a trench and doping a sidewall of the trench, similar to the first doping type semiconductor 430a , Alternatively, forming the second doping type semiconductor 430b implanting a dopant into the second electrode region 230b contain, for example by ion implantation or other known doping methods. According to various embodiments, the semiconductor can be of the second doping type 430b part of the second electrode area 230b his.

According to various embodiments, the semiconductor can be of the second doping type 430b be designed so that the semiconductor of the first doping type 430a and the second doping type semiconductor 430b provide a pn junction. For example, the semiconductor can be of the first doping type 430a Contain p-type doped silicon and the semiconductor of the second doping type 430b can contain n-type doped silicon. The first doping type semiconductor 430a and the second doping type semiconductor 430b can form a depletion area between them (or at their interface area). The depletion area can be the electrically insulating area 230i form or be part of the same and can the semiconductor from the first doping type 430a of the second doping type semiconductor 430b isolate.

A crack that extends into the depletion area (electrically insulating area 230i) propagates, a short circuit (electrical short circuit) between the semiconductor of the first doping type 430a and the second doping type semiconductor 430b or may cause an increase in the leakage current of the pn junction.

For example, according to various embodiments, the semiconductor of the first doping type 430a Part of a first semiconductor electrode 230a (of a first conductivity type) and the semiconductor of the second doping type 430b can be part of a second semiconductor electrode 230b (of a second conductivity type).

Furthermore, a first contact pad 434a are formed, for example on the semiconductor of the first doping type 430a is deposited as in 4F shown. The first contact pad 434a can with the semiconductor of the first doping type 430a to be in electrical contact. A second contact pad can also be used 434b are formed, the second contact pad 434b with the second doping type semiconductor 430b can be in electrical contact. The first contact pad 434a and the second contact pad 434b can contain an electrically conductive material (eg a metal or a metal alloy) or a metallized semiconductor. According to various embodiments, forming the first contact pad 434a and the second contact pad 434b arranging, for example depositing, for example plating, a metal or a metal alloy.

During the processing of the semiconductor chip 400 can the semiconductor body 102 of the semiconductor chip 400 eg by abrasive processing (eg grinding) or chemical processing (eg etching) eg to the level 450 be thinned. Thinning can be carried out if, for example, the thickness of the semiconductor body 102 is greater than the (planned) thickness of the fully processed semiconductor chip 400 , The thickness of the semiconductor body 102 , for example before thinning, can be considered a vertical expansion of the semiconductor body 102 can be understood, for example a distance from the first surface 302T of the semiconductor body 102 to the second surface 302b of the semiconductor body 102 , After thinning, the thickness may be reduced and may, for example, be a distance from the first surface 302T to the surface 302b ' (or the level 450 ) correspond.

According to various embodiments, the thickness of the semiconductor body 102 , for example before thinning out the semiconductor chip 400 , lie in a range from several hundreds of micrometers to approximately a few thousand micrometers, for example in the range from approximately 100 μm to approximately 5 mm, for example the thickness of the semiconductor body 102 be in the range from approximately 200 μm to approximately 1 mm, for example in the range from approximately 300 μm to approximately 800 mm.

According to various embodiments, the semiconductor chip 400 after forming the capacitive structure 230 be thinned. According to various embodiments, thinning the semiconductor chip 400 the bottom of the semiconductor body area 111 or the fully machined semiconductor chip 400 provide. For example, after thinning the surface 302b ' the bottom side 102b of the semiconductor body area 111 contain or correspond to this.

According to various embodiments, the depth of the trench 430 and the corresponding depth or vertical extent of the capacitive structure 230 (eg the first electrode area 230a or the second electrode area 230b) be in the range from about several micrometers to about several hundred micrometers, for example in the range from about 5 μm to about 500 μm, for example less than about 400 μm, for example less than about 100 μm, for example less than about 50 μm. For example, the capacitive structure 230 are formed so that by thinning the semiconductor chip 400 the capacitive structure 230 through the second surface 302b ' can break through.

According to various embodiments, the thickness of the semiconductor body region 111 , for example after thinning out the semiconductor chip 400 , can be in the range from approximately several micrometers to approximately several hundred micrometers, for example in the range from approximately 5 μm to approximately 500 μm, for example the thickness of the semiconductor body region 111 less than about 400 microns, for example less than about 100 microns, for example less than about 50 microns.

According to various embodiments, the second surface 302b of the semiconductor body 102 the second surface 102b of the semiconductor body area 111 provide if, for example, the semiconductor body 102 is already thinned out or no thinning out of the semiconductor body 102 is carried out. In other words, the thickness of the semiconductor body 102 can be the thickness of the fully machined semiconductor chips 400 his.

5A to 5C each show a semiconductor chip 500 in a cross-sectional view, for example in a cross-sectional view similar to a cross-sectional view along a line 201 or 301 , while processing the semiconductor chip 500 , for example during a process for forming a capacitive structure 230 according to various embodiments.

There can be a ditch 430 in a semiconductor body 102 (not shown, see 4A) be formed. According to various embodiments, an electrically insulating material 430i in the ditch 430 after making the trench 430 be arranged as in 5A shown. The electrically insulating material 430i can be part of the electrically insulating area 230i his. The electrically insulating material 430i can be arranged so that the side wall 430s of the trench 430 at least essentially from the electrically insulating material 430i can be covered (eg completely covered). The electrically insulating material 430i can be arranged so that a recess 530 in the electrically insulating material 430i is provided.

Alternatively, according to various embodiments, the electrically insulating material 430i from the side wall 430s the trench, for example by forming an oxide (by oxidizing) or by forming a nitride from the side wall 430s of the trench.

According to various embodiments, an electrically conductive material 532 in the recess 530 be arranged, for example a metal, a metal alloy or a polycrystalline silicon (as in 5B ) Shown. The electrically conductive material 532 may be part of the first electrode region in some embodiments 230a be (also as a metal electrode 230a designated).

Furthermore, a first contact pad 434a be formed, for example on the conductive material 532 be deposited as in 5C shown. The first contact pad 434a can with the conductive material 532 (for example the metal electrode 230a) to be in electrical contact. A second contact pad 434b can on the semiconductor body 102 be formed. The second contact pad 434b can with the semiconductor body 102 to be in electrical contact. The semiconductor body 102 with the second contact pad 434b in electrical contact may be part of the second electrode area 230b be (also as a semiconductor electrode 230b designated). According to various embodiments, the semiconductor body 102 contain a doped semiconducting material, for example an n-type semiconductor or a p-type semiconductor, with the second contact pad 434b is in contact.

In other words, the first electrode area 230a can contain a metal or metal alloy (around a metal electrode 230a to be provided) and the second electrode area 230b can contain a doped semiconductor, eg p-type doped silicon (to provide a semiconductor electrode). According to various embodiments, the semiconductor electrode 230b from a doped part of the semiconductor body region 111 be formed.

6A to 6C each show a semiconductor chip 600 in a cross-sectional view, for example in a cross-sectional view similar to a cross-sectional view along a line 201 or 301 , while processing the semiconductor chip 600 , for example during a process for forming a capacitive structure 230 according to various embodiments.

There can be a ditch 430 in a semiconductor body 102 (not shown, see 4A) be formed. According to various embodiments, a first electrically conductive material 532 after making the trench 430 in the ditch 430 be arranged as in 6A shown. The first electrically conductive material 532 can be part of the first electrode area 230a his. The first electrically conductive material 532 can be arranged so that the side wall 430s of the trench 430 at least essentially from the first electrically conductive material 532 is covered (e.g. completely covered). The first electrically conductive material 532 can be arranged so that a recess 530 in the first electrically conductive material 532 is provided. The first electrically conductive material 532 can be part of a first metal electrode 230a his.

Furthermore, an electrically insulating material 430i in the recess 530 be arranged as in 6B is shown. The electrically insulating material 430i can be part of the electrically insulating area 230i his. The electrically insulating material 430i can be arranged so that the first electrically conductive material 532 at least essentially from the electrically insulating material 430i is covered (e.g. completely covered). The electrically insulating material 430i can be arranged so that another depression 630 in the electrically insulating material 430 is provided.

According to various embodiments, the semiconductor body 102 be thinned, for example to a level 450 , as described here, with the further recess 630 in the electrically insulating material 430i the semiconductor body 102 can separate into two parts (the two separate semiconductor body regions 111 can form, one of the two separate semiconductor body regions 111 can be provided as in 7C shown), each of the two parts having a capacitive structure 230 contains.

In another embodiment, a second electrically conductive material 632 in the recess 630 be arranged as in 6C shown. The second electrically conductive material 632 can be part of the second electrode area 230b be (second in some embodiments metal electrode 230b designated). The second electrically conductive material 632 can be arranged so that the electrically insulating material 430i at least essentially of the second electrically conductive material 632 can be covered (for example completely covered, for example by essentially filling the depression 630 ). The semiconductor body 102 can, for example to a level 450 , be thinned to the bottom surface 102b of the semiconductor body area 111 provide. According to various embodiments, the second electrode area can be 230b essentially from the first surface 102t to the second surface 102b extend as in 6C shown.

Furthermore, the first electrically conductive material 532 and the second electrically conductive material 632 be electrically coupled to a contact pad as described here. According to various embodiments, the first electrode area 230a contain a first metal or a first metal alloy (around a first metal electrode 230a to be provided) and the second electrode area 230b may include a second metal or metal alloy (around a second metal electrode 230b provide).

7A to 7C each show a semiconductor chip 700 in a cross-sectional view, for example in a cross-sectional view similar to a cross-sectional view along a line 201 or 301 , while processing the semiconductor chip 700 , for example during a process for separating a semiconductor chip 700 from a wafer 702 and forming a capacitive structure 230 according to various embodiments.

For the separation of the semiconductor chip 700 from a wafer 702 can be a known process 112 for cutting the wafer in the saw slot area 142 be carried out, e.g. a process 112 for mechanical cutting of the wafer, e.g. mechanical sawing (e.g. using a saw 712 ), as in 7A represented, or other processes 112 for cutting the wafer (eg laser cutting).

After the process 112 the semiconductor body can be used to cut the wafer 102 of the semiconductor chip 700 a side wall 102s (side side 102s) included, which is between the top page 102t and the bottom 102b of the semiconductor body 102 extends as in 7B shown. Because of the process 112 a chip crack can be used to cut the wafer 110 occur, for example the chip crack 110 coming from the side wall 102s of the semiconductor chip 700 exit.

According to various embodiments, a capacitive structure 230 on the side wall 102s of the semiconductor chip 700 be formed as in 7C shown. The capacitive structure 230 can detect chip cracks 110 deploy that is already in the semiconductor chip 700 after cutting 112 are present, and also the detection of chip cracks 110 that during the operation of the fully machined semiconductor chip 700 , for example in an electrical device.

In other words, the capacitive structure 230 that on the side wall 102s of the semiconductor chip 700 is formed, a possibly existing chip crack 110 in the side wall 102s to capture. The chip crack 110 can the capacitive structure 230 , how it is formed, for example, shunt, or the chip crack 110 can the capacitive structure 230 affect if the chip crack 110 further into the semiconductor chip 700 spreads.

To form the capacitive structure 230 can be an electrically insulating material according to various embodiments 430i on the side wall 102s formed (eg deposited) so that the side wall 102s (side side 102s) at least essentially from the electrically insulating material 430i can be covered (eg completely covered). Alternatively, the side wall 102s of the semiconductor chip 700 are oxidized to form a semiconductor oxide layer. The term "essentially covered" can be understood to mean a surface, for example the surface of the side wall 102s or a surface of a trench 430 referred to, which can be more than 80%, for example more than 90%, for example completely covered. For example, the electrically insulating material 430i an electrically insulating layer 230i over the side wall 102s form, the electrically insulating material 430i the electrically insulating area 230i the capacitive structure 230 can provide.

Furthermore, an electrically conductive material 532 (eg forming a metal electrode 230a) over the electrically insulating material 430i formed (eg deposited) so that the electrically insulating material 430i at least essentially from the electrically conductive material 532 can be covered (eg completely covered). For example, the electrically conductive material 532 an electrically conductive layer over the electrically insulating layer 230i form. The electrically conductive material 532 can be the first electrode area 230a the capacitive structure 230 form.

In some embodiments, the capacitive structure 230 a metal electrode 230a over the side 102s and an electrically insulating layer 230i between the metal electrode 230a and the side 102s is arranged included.

According to various embodiments, a first electrical contact pad 434a are formed, the first electrical contact pad 434a with the metal electrode 230a (in other words, the electrically conductive material 532 ) is in electrical contact and it can have a second electrical contact pad 434b are formed, the second electrical contact pad 434b with part of the semiconductor body 102 , for example a doped part of the semiconductor body region 111 is in electrical contact as described here. The doped part of the semiconductor body region 111 can be a semiconductor electrode 230b deploy as described here.

The electrically conductive material 532 can contain a material that cracked in a chip 110 can flow through capillary flow (or creep, for example through plastic deformation of the material), so that the material with part of the semiconductor body 102 (or the semiconductor body area 111 ) next to the chip crack 110 comes into electrical contact. The capillary flow or the capillary movement can be seen as the ability of the material 532 be understood to flow into narrow spaces by capillary forces, without the help of and also counter to external forces such as gravity. For example, capillary flow may be due to cohesion and adhesion affecting the material 532 cause yourself into a chip crack 110 to move.

If there is a chip crack 110 in the electrically insulating material 430i spreads or a chip crack 110 already exists if the electrically insulating material 430i is formed, the chip crack 110 an opening of the electrically insulating material 430i cause (in other words, the opening in the electrically insulating material 430i can be part of the side wall 102s uncover). The material 532 can result from capillary flow in the opening in the electrically insulating material 430i move and can with the semiconductor electrode 230b (or the semiconductor body area 111 ) come into electrical contact. Therefore, the semiconductor electrode 230b to the electrically conductive material 532 be shunted.

In another embodiment, a semiconductor chip 700 , shown in 7C , by thinning out 450 of a semiconductor body 102 , as in 5C shown, and optional disconnect 112 , for example by cutting, the semiconductor body 102 through the first electrode area 230a to be provided. In other words, the side wall 430s of the trench 430 can be a side wall of the semiconductor body 102 after disconnecting 112 of the semiconductor body 102 form.

8A shows a semiconductor chip 800 according to various embodiments in a cross-sectional view (similar 2A or 7C ). The semiconductor chip 800 can be a capacitive structure 230 for detecting crack propagation in the semiconductor chip 800 contain. To provide a semiconductor chip 800 with a capacitive structure 230 , as in 8A shown, different methods for processing the semiconductor chip 800 be carried out as described here.

According to various embodiments, the semiconductor chip 800 , as in 8A represented by thinning 450 of a semiconductor body 102 , as in 6C shown, and optional disconnect 112 , for example by cutting, the semiconductor body 102 through the second electrically conductive material 632 to be provided. In other words, the side wall 430s of the trench 430 can be a side wall of the semiconductor body 102 after disconnecting 112 of the semiconductor body 102 form.

According to various embodiments, the semiconductor chip 800 , as in 8A shown, by arranging a second electrically conductive material 632 between the side wall 102s of a semiconductor body 102 , as in 7C shown, and the electrically insulating layer 430i to be provided.

The capacitive structure 230 can have two electrodes 230a . 230b (in other words, two electrode areas 230a . 230b ) contained by a separating layer 230i (in other words, an electrically insulating layer 230i ) are separated (e.g. electrically insulated). The capacitive structure 230 can at the transition area between the semiconductor chip 800 and the Säschllitz area 142 (also known as a saw frame 142 ) be arranged. The two electrodes 230a . 230b can the semiconductor body area 111 of the semiconductor chip 800 completely surrounded and can be seen from the top 102t to the bottom 102b of the semiconductor chip 800 extend.

A chip crack 110 coming from the side wall of the semiconductor chip 800 emerges (which is next to the saw frame 142 can be) due to the capacitive structure 230 spread out (also as a peripheral surface 230 designated). The chip crack 110 , which is characterized by the capacitive structure 230 spreads, the interface can 230i damage or destroy, as by an electrical characterization of the capacitive structure 230 , eg by a measuring circuit, eg measuring circuit 310 of 3A , can be recorded. The electrical characterization (for example providing a so-called failure mapping) can provide characteristic failure symptoms, for example a short circuit, a changed (for example increased) leakage current or a changed (for example reduced) dielectric strength of the capacitive structure 230 , An occurrence of an or Several characteristic failure symptoms can occur with the spread of chip cracks 110 correlate and can enable appropriate countermeasures to be initiated, for example changing the operating mode of the semiconductor chip 800 to undefined behavior of the semiconductor chip 800 to avoid.

According to various embodiments, the semiconductor chip 800 on a lead frame 802 for further processing of the semiconductor chip 800 arranged (e.g. fastened, e.g. glued or soldered), e.g. the lead frame 802 electrically with the semiconductor chip 800 come into contact. The lead frame 802 may include a metal structure (or a metal alloy structure) or a contact structure that is used to transmit signals to or from the semiconductor chip 800 can be designed. If, for example, the fully machined semiconductor chip 800 The lead frame can be encapsulated in a chip package 802 the transmission of signals between the outside of a chip package (for example a connection pad of the chip package) and the semiconductor chip 800 provide.

The bottom side 102b of the semiconductor body area 111 can through the bottom surface of the fully machined semiconductor chip 800 be defined on the lead frame 802 can be attached.

According to various embodiments, the electrically insulating layer 230i contain a viscous material. The viscous material can be designed to pass through an opening in an electrode area 230a . 230b (simply as an electrode 230a . 230b designated) licks. The opening in the electrode 230a . 230b can crack through a chip 110 caused. In other words, the viscous material may have a shear flow or other linear deformation over time when stress or force, such as gravity, is applied to the viscous material. The viscous material can pass through the opening in the electrode 230a . 230b lick what the electrical properties (e.g. dielectric strength) of the capacitive structure 230 (e.g. between the electrodes 230a . 230b in addition to the viscous material). The viscous material can contain a paste-like material, a gel-like material, a grease, a liquid material, or a mixture of a solid material and a liquid material. For example, the viscous material can include a glass, a polymer, or an oil

8B shows a semiconductor chip 850 , according to various embodiments, in a cross-sectional view (analog 2A or 6C ). The semiconductor chip 850 can be a capacitive structure 230 with multiple electrode areas 230a . 230b , ..., 230f (also as multiple electrodes 230a . 230b , ..., 230f designated) and several electrically insulating layers 230i contain.

According to various embodiments, the semiconductor chip 850 Be part of a wafer, the semiconductor chip 850 for separating the wafer 702 (eg by cutting the wafer, eg by sawing the wafer) can be determined. For example, the wafer 702 in the Säschllitz area 142 for separating the semiconductor chip 850 be cut.

According to various embodiments, a capacitive structure 230 with multiple electrode areas 230a . 230b , ..., 230f in the Säschllitz area 142 of the wafer 702 before cutting the wafer 702 to be provided. Six electrode areas 230a . 230b . 230c . 230d . 230e . 230f are in as an example 8B shown. However, the number of electrode areas can differ from six. The capacitive structure 230 can be provided so that the wafer 702 through the capacitive structure 230 cut, eg sawn 112 can be, with at least two electrode areas, eg 230a and 230b , separated by an electrically insulating layer 230i , on the semiconductor chip 850 stay attached as in 8B shown.

According to various embodiments, a method for processing a wafer 702 , eg forming the capacitive structure 230 with multiple electrode areas 230a . 230b , ..., 230f , forming a trench 430 next to the semiconductor chip 850 of the wafer 702 contain. The ditch 430 can in the Säschllitz area 142 be educated. The ditch 430 can essentially differ from a first surface 102t of the wafer 702 to a second surface 102b of the wafer 702 opposite the first surface 102 extend. The first surface 102t of the wafer 702 can be the first surface 102t of the semiconductor body area 111 included and the second surface 102b of the wafer 702 opposite the first surface 102 can the second surface 102b of the semiconductor body area 111 contain.

According to various embodiments, the method may further form a capacitive structure 230 in the ditch 430 contain the capacitive structure 230 can the multiple electrode areas 230a . 230b , ..., 230f with at least a first electrode area, eg 230a , a second electrode area, e.g. 230b that on a first side of the first electrode area, eg 230a , is arranged, and a third electrode area, eg 230c that on a second side of the first electrode area, eg 230a , is arranged, included. Furthermore, the capacitive structure 230 a first electrically insulating area 230i that is between the first electrode area, eg 230a , and the second Electrode area, e.g. 230b , extends, and a second electrically insulating region 230i that is between the first electrode area, eg 230a , and the third electrode area, e.g. 230c , stretches, included.

According to various embodiments, the capacitive structure 230 are formed such that at least one of the first, second, and third electrode regions extends substantially from the first surface 102t of the wafer to the second surface 102b of the wafer 702 opposite the first surface 102t extends.

According to various embodiments, the method may further cut the wafer 702 through the ditch 430 included to the semiconductor chip 850 from the wafer 702 to separate, with at least the first electrode area, eg 230a , and the second electrode area, e.g. 230b , on the semiconductor chip 850 can remain attached.

In other words, the multiple electrode areas 230a . 230b , ..., 230f and the multiple electrically insulating layers 230i can in the Säschllitz area 142 be arranged. The functionality of at least two electrode areas of the plurality of electrode areas 230a . 230b , ..., 230f can according to various embodiments, such as in 8B shown, possibly from the exact position of the saw (or saw blade 712 ) be independent. Therefore, a chip crack 110 which is characterized by at least one electrically insulating layer 230i of the several electrically insulating layers 230i spreads, a short circuit or a changed dielectric strength of the capacitive structure 230 cause.

According to various embodiments, the semiconductor chip 850 , as in 8B represented by a method described here, for example similar 6A to 6C , be provided, the plurality of electrode regions 230a . 230b , ..., 230f and the multiple electrically insulating layers 230i in the ditch 430 can be arranged.

According to various embodiments, the semiconductor chip 850 , as in 8B represented, for example by providing several trenches, similar to that in 4A illustrated trench 430 are provided, at least one electrode area of the plurality of electrode areas 230a . 230b , ..., 230f in a ditch 430 of the multiple trenches, similar to the first electrode area 230a , as in 5C or 6C shown.

9A shows a semiconductor chip 900 according to various embodiments in a cross-sectional view (similar 1A) , The semiconductor chip 900 can be a capacitive structure 230 included between the sealing ring 120 and the side wall 102s of the semiconductor chip 900 is arranged.

For example, the capacitive structure works 230 like a plate capacitor containing two electrodes 230a . 230b (which are also called peripheral surfaces 230a . 230b be designated). If the capacitive structure 230 at or near the side wall 102s of the semiconductor chip 900 is arranged, a chip crack 110 impairment of the electrically insulating area 230i between the two electrodes 230a . 230b lead (e.g. with zero hours of operating time or zero hours of test time). The impairment of the electrical insulating area 230i can by electrical characterization of the capacitive structure 230 be detectable.

According to various embodiments, on the one hand complicated stress tests, for example acceleration tests for early failure, for example burn-in, may not be necessary, while on the other hand detection reliability according to various embodiments compared to conventional methods for detecting chip cracks 110 can be bigger. Furthermore, a chip crack 110 that during the operation of a semiconductor chip 900 , for example on a side wall 102s of a semiconductor chip 900 , appears through a capacitive structure 230 according to various embodiments.

9B shows a semiconductor chip 950 according to various embodiments in a cross-sectional view (similar 1A) , The semiconductor chip 950 can be a capacitive structure 230 with multiple trenches included. In every ditch 430 of the multiple trenches can be a first electrode 230a (e.g. a metal electrode 230a or a semiconductor electrode 230a) and an electrically insulating layer 230i be arranged (similar 5B) , Furthermore, a second electrode can be formed, for example the second electrode 230b a doped part of the semiconductor body region 111 contain.

10A and 10B each show a semiconductor chip 1000 in a cross-sectional view during the processing of the semiconductor chip 1000 , for example during a process for forming a capacitive structure 230 according to various embodiments.

A trench with a side wall 430s can in a semiconductor body 102 be formed (not shown, see 4A) , According to various embodiments, a first electrode 230a and a second electrode 230b be formed in the trench, as in 10A shown. The first electrode 230a and the second electrode 230b can at least partially opposite sides of the side wall 430s of the trench. The first electrode 230a and the second electrode 230b can be arranged at a distance from each other. Furthermore, the first electrode 230a and the second electrode 230b a deepening 530 form and can on opposite sides of the recess 530 be arranged.

According to various embodiments, an electrically insulating area 230i in the recess 530 be formed as in 10B shown. The electrically insulating area 230i can at least partially the recess 530 to fill.

10C shows a semiconductor chip 1050 according to various embodiments in a cross-sectional view (analog 1A) , The semiconductor chip 1050 can contain multiple trenches, including a first trench 1030a and a second trench 1030b , The first ditch 1030a can be a first electrode area 230a the capacitive structure 230 contain; and the second ditch 1030b can be a second electrode area 230b the capacitive structure 230 contain.

According to various embodiments, the first trench 1030a at least partially filled with a first metal or a first metal alloy and the second trench 1030b can be at least partially filled with a second metal or a second metal alloy. The first metal or the first metal alloy and the second metal or the second metal alloy can be the same metal or the same metal alloy.

11A shows a semiconductor chip 1100 according to various embodiments in a cross-sectional view (analog 1A) , The semiconductor chip 1100 can be a crack absorption area 1130 contain. The semiconductor body area 111 of the semiconductor chip 1100 can be a first surface 102t , for example an upper surface 102t , and a second surface 102b , eg a lower surface 102b , opposite the first surface 102t , contain.

According to various embodiments, the crack absorption area 1130 at least partially the semiconductor body area 111 surround. Furthermore, the crack absorption area 1130 from the first surface 102t in one direction to the second surface 102b extend. The crack absorption area 1130 can be used to absorb a spread of the chip crack 110 be designed. In other words, the crack absorption area 1130 can be designed to resist breakage or to avoid cracking 110 through the crack absorption area 1130 spreads and / or avoids a crack 110 from the crack absorption area 1130 further into the semiconductor body area 111 spreads.

Therefore, the crack absorption area 1130 a crack absorption material 1132 , in other words, a crack stop material 1132 contain. The crack absorption material 1132 can define an elongation at break, in other words, an extent at which the crack absorption area breaks 1130 , which can be higher than the elongation at break of the semiconductor body region 111 , The elongation at break can be expressed as maximum elongation, in other words, maximum expansion, of the crack absorbing material 1132 be considered in which the crack absorption material 1132 withstands cracking. The elongation of a stretched body, for example a solid body, can be defined after the break with relative expansion, dL, of the body to the length of the body, L, before the expansion. In other words, stretching a solid body in a certain direction results in an increase in the length L of the solid body by dL in that direction. Elongation at break can be understood as the relative expansion at which cracks appear in solid bodies, in other words, until the expansion leads to material failure.

According to various embodiments, the crack absorption material 1132 contain an elongation at break of more than about 5%, for example more than about 10%, for example more than about 50%, for example more than about 100%, for example more than about 200%. According to various embodiments, the elongation at break of the crack absorption material is 1132 greater than an elongation at break of the semiconductor body 102 , for example more than twice the elongation at break of the semiconductor body 102 , for example more than five times the elongation at break of the semiconductor body 102 , for example more than ten times the elongation at break of the semiconductor body 102 , The elongation at break of the semiconductor body 102 can through the semiconductor material of the semiconductor body 102 , for example defined by an elongation at break of silicon.

According to various embodiments, the crack absorption material 1132 Contain material with low fragility, such as a deformable material or an elastic material. For example, the crack absorption material 1132 contain a composite material or an elastomer, a rubber, an imide, a metal, for example aluminum, a printable polymer, a polymer lacquer or a photoresist.

According to various embodiments, the crack absorption material 1132 a material with a fracture toughness greater than the fracture toughness of the semiconductor body region 111 , for example a metal or a metal alloy. Fracture toughness can be viewed as the ability of a material containing a crack to withstand fracture, e.g., to withstand a mechanical load (e.g., mechanical stress) without a To cause the crack to grow or to experience its mechanical properties without failure. The fracture toughness of a material can be determined from the stress near the tip of a crack in the material caused by a remote mechanical load or by residual stresses at which the crack in the material begins to grow. For example, the fracture toughness of the crack absorbent material 1132 more than about 10 MPa m ^1/2 , for example more than about 20 MPa m ^1/2 .

According to various embodiments, the crack absorption area can be different 1130 at least essentially from the first surface 102t to the second surface 102b extend. For example, the crack absorption area 1130 through the semiconductor body area 111 extend.

According to various embodiments, the crack absorption material 1132 in a ditch 430 (please refer 4A) be arranged. The ditch 430 can get into the semiconductor body 102 extend. The ditch 430 can at least partially with the crack absorption material 1132 be filled.

11B shows a semiconductor chip 1150 according to various embodiments in a cross-sectional view (similar 1A) , the crack absorption area 1130 a side wall 1130s of the semiconductor body area 111 can form. According to various embodiments, the crack absorption material 1132 on a side wall 102s of the semiconductor body area 111 be arranged, for example after the semiconductor chip has been separated 1150 from a wafer 702 , According to various embodiments, the semiconductor chip 1150 through the crack absorption material 1132 be separated, eg by cutting (eg by sawing) through the crack absorption material 1132 ,

11C shows a semiconductor chip 1170 according to various embodiments in a cross-sectional view (analog 1A) , the semiconductor chip 1170 also a first electrode area 230a and a second electrode area 230b contains, which can be designed according to various embodiments, as described here.

The first electrode area 230a and the second electrode area 230b can be arranged so that the crack absorption area 1130 between the first electrode area 230a and the second electrode area 230b extends. For example, the crack absorption material 1132 in a recess 530 be arranged by the first electrode area 230a and the second electrode area 230b can be formed (see 10A) ,

According to various embodiments, the first electrode area 230a , the crack absorption area 1130 and the second electrode area 230b a capacitive structure 230 to detect crack propagation into the semiconductor body region as described here. The electrical properties of the crack absorption area 1130 can have a dielectric strength of the capacitive structure 230 define. According to various embodiments, the crack absorption area 1130 a dielectric crack absorption material 1132 , for example, contain a dielectric elastomer or a dielectric polymer.

According to various embodiments, the crack absorption material 1132 contain an insulating material, for example an insulating polymer, for example benzocyclobutene (BCB), an imide (for example polyimide (PI) or other imide), a resin or a photoresist. The crack absorption material 1132 can be more deformable, for example more flexible, for example softer, than the semiconductor body 102 , for example as silicon. The crack absorption material 1132 can cause a "crack propagation energy" to be absorbed, which causes crack propagation in the crack absorption material 1132 allows. In other words, the crack absorbing material 1132 may be suitable for crack propagation through the crack absorption material 1132 to absorb or stop. The crack absorption material 1132 can also provide electrical insulation between the first electrode region 230a and the second electrode area 230b provide and may also allow measurement of changes in insulation, such as a crack in the crack absorbent material 1132 penetrates.

According to various embodiments, the crack absorption material 1132 contain a spin on glass material, for example a silicate or a siloxane or the like. For example, the crack absorption material 1132 (eg a spin on glass material or an imide) can be deposited or applied by rotation, for example by a rotation technique, for example in combination with a sol-gel technique. For example, the crack absorption material 1132 be provided in a liquid form, for example as a sol-gel or contained in a solvent, and in the trench 430 be introduced by flow movement. After insertion of the crack absorption material 1132 in the trench 430 can the crack absorption material 1132 are hardened, for example by tempering the crack absorption material 1132 or the entire semiconductor chip. Therefore, the crack absorption material 1132 after hardening in the trench 430 be attached. According to various embodiments, the crack absorption material 1132 be porous after hardening. A crack absorption material 1132 in porous form can be a moderate insulator due to its inhomogeneity, but porosity can increase the ability to stop or absorb a crack.

According to various embodiments, the crack absorption material 1132 contain a synthetic material, for example plastic, for example a polymer, as described above. For example, the crack absorption material 1132 in the trench 430 be introduced by injection molding.

12 shows a schematic flow diagram of a method 1200 for processing a semiconductor chip (in other words, an integrated circuit, IC, a chip or microchips), the method 1200 may contain: in 1202 Forming a trench in the semiconductor chip, the trench at least partially surrounding a semiconductor body region of the semiconductor chip and extending at least substantially from a first surface of the semiconductor body region to a second surface of the semiconductor body region opposite the first surface ; and in 1204 Forming a capacitive structure that includes a first electrode region, a second electrode region, and an electrically insulating region that extends between the first electrode region and the second electrode region; wherein at least the first electrode region is formed at least in one or at the trench, so that the first electrode region at least partially surrounds the semiconductor body region and extends at least substantially from the first surface to the second surface.

According to various embodiments, the first electrode region can be formed in the trench, for example deposited in the trench (for example similarly 6A) , The first electrode region can be formed on the trench, for example from a side wall of the trench (for example similarly 4B) , The procedure 1200 can also be designed according to one or more embodiment (s) described here.

13 shows a schematic flow diagram of a method 1300 for processing a semiconductor chip, the method 1300 may include: in 1302 forming a capacitive structure on a sidewall of the semiconductor chip; wherein the capacitive structure is a semiconductor electrode (also referred to as a second electrode region containing a semiconductor) formed by a doped part of the side wall, a metal electrode (also referred to as a first electrode region containing a metal or a metal alloy), which over the Side wall is arranged, and may contain an electrically insulating layer (also referred to as an electrically insulating region), which is arranged between the metal electrode and the side wall; in 1304 Forming a first contact pad that is in electrical contact with the metal electrode; and in 1306 Forming a second contact pad that is in electrical contact with the semiconductor electrode, wherein the first and second contact pads can be configured to be electrically coupled to a measuring device to apply a voltage between the metal electrode and the semiconductor electrode. The procedure 1300 can also be designed according to one or more embodiment (s) described here.

14 shows a schematic flow diagram of a method 1400 for processing a wafer (in other words, a carrier, for example a substrate), the method 1400 may contain: in 1402 Forming a trench between a first semiconductor chip of the wafer and a second semiconductor chip of the wafer; wherein the trench may extend substantially from a first surface of the wafer to a second surface of the wafer opposite the first surface; in 1404 Forming a capacitive structure in the trench; and in 1406 Separating the first semiconductor chip from the second semiconductor chip, the capacitive structure remaining attached to the first semiconductor chip. The procedure 1400 can also be designed according to one or more embodiment (s) described here.

15 shows a schematic flow diagram of a method 1500 for processing a wafer, the method 1500 may contain: in 1502 Forming a trench next to a semiconductor chip of the wafer; wherein the trench may extend substantially from a first surface of the wafer to a second surface of the wafer opposite the first surface; in 1504 Forming a capacitive structure in the trench, the capacitive structure comprising a first electrode region, a second electrode region that is arranged on a first side of the first electrode region, a third electrode region that is arranged on a second side of the first electrode region, a first electrically insulating region that extends between the first electrode region and the second electrode region and may include a second electrically insulating region that extends between the first electrode region and the third electrode region; wherein at least one of the first, second and third electrode regions extends substantially from the first surface of the wafer to the second surface of the wafer opposite the first surface; and in 1506 Cutting the wafer through the trench, at least the first electrode region and the second electrode region remaining attached to the semiconductor chip. The procedure 1500 can also be designed according to one or more embodiment (s) described here.

16 shows a schematic flow diagram of a method 1600 for processing a wafer, the method 1600 may contain: in 1602 Forming a trench next to a semiconductor chip of the wafer; and in 1604 forming a crack absorption area in the trench, the crack absorption area extending from the first surface in a direction toward the second surface; the crack absorption region can have a greater elongation at break than the semiconductor chip. The procedure 1600 can also be designed according to one or more embodiment (s) described here.

17 shows a schematic flow diagram of a method 1700 for processing a semiconductor chip, the method 1700 may contain: in 1702 Forming a trench in the semiconductor chip; wherein the trench can at least partially surround a semiconductor body region of the semiconductor chip and can extend from a first surface of the semiconductor body region in a direction to a second surface of the semiconductor body region opposite the first surface; and in 1704 Forming a crack absorption area in the trench, wherein the crack absorption area can have a greater elongation at break than the semiconductor body area. The procedure 1700 can also be designed according to one or more embodiment (s) described here.

Claims (19)

Semiconductor chip (300), comprising: a semiconductor body region (111) having a first surface and a second surface opposite the first surface; a capacitive structure (230) for detecting crack propagation into the semiconductor body region (111); wherein the capacitive structure (230) has a first electrode region (230a) that at least partially surrounds the semiconductor body region (111) and extends at least substantially from the first surface to the second surface; and the capacitive structure (230) further comprising a second electrode region (230b) which is arranged next to the first electrode region (230a) and an electrically insulating region (230i) which is between the first electrode region (230a) and the second electrode region (230b ) extends, has, wherein the capacitive structure (230) has a trench which has the first electrode region (230a), the second electrode region (230b) and the electrically insulating region (230i). Semiconductor chip (300) after Claim 1 wherein the second electrode region (230b) at least partially surrounds the semiconductor body region (111). Semiconductor chip (300) after Claim 1 or 2 , wherein the second electrode region (230b) extends at least substantially from the first surface to the second surface. Semiconductor chip (300) according to one of the Claims 1 to 3 , further comprising a first contact pad and a second contact pad, the first electrode region (230a) being electrically coupled to the first contact pad; and wherein the second electrode region (230b) is electrically coupled to the second contact pad; and wherein the first contact pad and the second contact pad are designed for electrical coupling to a measuring circuit (310) in order to measure a parameter of the capacitive structure (230). Semiconductor chip (300) after Claim 4 , wherein the semiconductor chip (300) further comprises the measuring circuit (310), which is designed to measure a value of the parameter of the capacitive structure (230) by electrically characterizing the capacitive structure (230), wherein the measuring circuit (310) further to determine a Cracks is designed based on the measured value of the parameter. Semiconductor chip (300) according to one of the Claims 1 to 5 , wherein the first electrode region (230a) has a first material and the second electrode region (230b) has a second material. Semiconductor chip (300) after Claim 6 , wherein the first material is a first metal or a first metal alloy and the second material is a second metal or a second metal alloy, or the first material is a doped semiconductor of a first conductivity type and the second material is a doped semiconductor of a second conductivity type, or the first material is a metal or a metal alloy and the second material is a doped semiconductor. Semiconductor chip (300) according to one of the Claims 1 to 7 , the electrically insulating region (230i) comprising a dielectric material. Semiconductor chip (300) according to one of the Claims 1 to 6 , wherein the first electrode region (230a) has a first metal or a first metal alloy that at least partially fills the trench, and the second electrode region (230b) has a second metal or a second metal alloy that at least partially Trench fills. Semiconductor chip (300) according to one of the Claims 1 to 9 , wherein the first electrode region (230a) has a first semiconductor region of a first conductivity type which has a side wall of the trench, the second electrode region (230b) having a second semiconductor region of a second conductivity type; and the electrically insulating Region (230i) has a depletion region which is formed by the first semiconductor region and the second semiconductor region. Semiconductor chip (300) according to one of the Claims 1 to 10 wherein the trench of the capacitive structure (230) has a first trench that has the first electrode region (230a); and has a second trench having the second electrode region (230b). Semiconductor chip (300) after Claim 11 , wherein the first electrode region (230a) comprises a first metal or a first metal alloy that at least partially fills the first trench, and the second electrode region (230b) comprises a second metal or a second metal alloy that at least partially fills the second trench. Semiconductor chip (300) according to one of the Claims 1 to 12 , further comprising a third electrode region which is arranged next to the first electrode region (230a) and a further electrically insulating region which extends between the third electrode region and the first electrode region (230a). Semiconductor chip (300) after Claim 13 wherein the third electrode region and the second electrode region (230b) are arranged on opposite sides of the first electrode region (230a). Semiconductor chip (300) according to one of the Claims 1 to 14 , wherein the first electrode region (230a) and the second electrode region (230b) form a pn junction, the electrically insulating region (230i) having a depletion region of the pn junction. Semiconductor chip (300) according to one of the Claims 1 to 15 , wherein a doped part of the semiconductor body region (111) forms the second electrode region (230b). Semiconductor chip (300) according to one of the Claims 1 to 16 , wherein an oxidized part of the semiconductor body region (111) forms the electrically insulating region (230i). Semiconductor chip (300) according to one of the Claims 1 to 17 , wherein the first electrode region (230a) forms a side wall of the semiconductor chip (300). Semiconductor chip (300), comprising: a semiconductor body region (111) having a first surface and a second surface opposite the first surface; a capacitive structure (230) for detecting crack propagation into the semiconductor body region (111); wherein the capacitive structure (230) has a first electrode region (230a), which has a first metal or a first metal alloy, and a second electrode region (230b), which has a second metal or a second metal alloy, which is adjacent to the first electrode region (230a ) is arranged, wherein the first and second electrode regions (230b) at least partially surround the semiconductor body region (111) and at least substantially extend from the first surface to the second surface; wherein the capacitive structure (230) further comprises an electrically insulating region (230i) arranged between the first electrode region (230a) and the second electrode region (230b), and wherein the capacitive structure (230) has a trench which has the first electrode region (230a), the second electrode region (230b) and the electrically insulating region (230i).

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