DE102021130953A1 - crack sensor - Google Patents

Abstract

A chip is provided, comprising core circuitry; a sealing ring at least partially surrounding the core circuitry; at least one crack sensor disposed outside of the sealing ring and the core circuitry, wherein the at least one crack sensor is electrically connected to the core circuitry via a semiconductor layer underlying metal layers. A method for determining a status of at least one crack sensor is also proposed.

Description

U.S. 8,253,420 B2 discloses a detection circuit and one or more wires or traces contained within a die. The combination is used to detect a mechanical failure of the substrate, eg silicon, after singulation of the die from the wafer. Defects can be detected at different regions or levels within the die, and the tests can be performed during operation of the packaged die and integrated circuit, even after installation and during operation of a larger electronic device in which it is housed become.

The task is to improve existing solutions for detecting mechanical failures and in particular to be able to detect cracks in the horizontal direction across a chip.

This is achieved according to the features of the independent claims. Further embodiments are evident from the dependent claims.

The examples proposed herein can be based in particular on at least one of the following solutions. Combinations of the following features can be used to achieve a desired result. The features of the method could be combined with any feature(s) of the device or vice versa.

• - eine Kernschaltlogik;
• - einen Dichtring, der die Kernschaltlogik zumindest teilweise umgibt;
• - zumindest einen Risssensor, der außerhalb des Dichtrings und der Kernschaltlogik angeordnet ist,
• - wobei der zumindest eine Risssensor über eine Halbleiterschicht, die sich unterhalb von Metallschichten befindet, elektrisch mit der Kernschaltlogik verbunden ist.

A chip is proposed comprising

• - a core circuitry;
• - a sealing ring at least partially surrounding the core circuitry;
• - at least one crack sensor, which is arranged outside of the sealing ring and the core switching logic,
• - wherein the at least one crack sensor is electrically connected to the core circuitry via a semiconductor layer located beneath metal layers.

The chip may be a semiconductor device comprising a semiconductor material, e.g., silicon, and multiple layers of metal forming electrical paths. The core circuitry is a section of the chip that implements electronic functionality. The core circuitry may include or be any processing device, controller, or combination circuitry.

According to one embodiment, the at least one crack sensor at least partially surrounds the sealing ring.

According to one embodiment, the crack sensor is electrically connected to the core circuitry without breaking the sealing ring.

According to one embodiment, the crack sensor is located at least partially in an AOI zone.

According to one embodiment, the crack sensor comprises an electrical connection via different metal layers.

According to one embodiment, the crack sensor includes an electrical connection that is tortuous over various metal layers.

• - ein dotiertes Substrat,
• - einen dotierten Bereich innerhalb des Substrats,
• - eine Polysiliziumschicht,
• - eine Salicide-Schicht.

According to one embodiment, the semiconductor layer comprises at least one of the following:

• - a doped substrate,
• - a doped region within the substrate,
• - a polysilicon layer,
• - a salicide layer.

According to one embodiment, the at least one crack sensor comprises different segments, each segment being arranged substantially parallel to an edge of the core circuitry.

According to one embodiment, each of the crack sensors is driven by a multiplexed signal.

According to one embodiment, the core circuitry is arranged to evaluate the status of the at least one crack sensor.

• - wobei sich der zumindest eine Risssensor in einem Chip befindet,
• - wobei der zumindest eine Risssensor außerhalb eines Dichtrings und einer Kernschaltlogik des Chips angeordnet ist, wobei der Dichtring die Kernschaltlogik zumindest teilweise umgibt,
• - wobei der zumindest eine Risssensor über eine Halbleiterschicht, die sich unterhalb von Metallschichten befindet, elektrisch mit der Kernschaltlogik verbunden ist,
• - wobei der Status des zumindest einen Risssensors durch die Kernschaltlogik bestimmt wird.

In addition, a method for determining a status of at least one crack sensor is provided,

• - wherein the at least one crack sensor is located in a chip,
• - wherein the at least one crack sensor is arranged outside of a sealing ring and a core circuitry of the chip, wherein the sealing ring at least partially surrounds the core circuitry,
• - wherein the at least one crack sensor is electrically connected to the core circuitry via a semiconductor layer located below metal layers,
• - wherein the status of the at least one crack sensor is determined by the core circuitry.

According to one embodiment, if a mechanical error in the at least one crack sensor is detected via the core circuitry, a predetermined action is triggered by the core circuitry.

The predetermined action may include: issuing an (alert) notification and/or powering down the affected core circuitry.

• 1 zeigt eine beispielhafte Anordnung, umfassend eine Kernschaltlogik, die von einem Dichtring und (zumindest teilweise) von einem Risssensor umgeben ist;
• 2 zeigt eine Auswahl des Risssensors in einem optionalen und beispielhaften Bereich 105 entlang der Schnittansicht C-C in der x-z-Ebene;
• 3 zeigt eine Auswahl des Risssensors in einem Bereich 104 entlang der Schnittansicht A-A in der x-z-Ebene;
• 4 zeigt eine Auswahl des Risssensors entlang der Schnittansicht B-B in der y-z-Ebene und
• 5 zeigt ein beispielhaftes Diagramm, umfassend die Kernschaltlogik mit einer Detektionseinheit, wobei verschiedene Risssensoren mit der Detektionseinheit verbunden sind.

Embodiments are shown and illustrated with reference to the drawings. The drawings are intended to illustrate the basic principle, so only aspects necessary for understanding the basic principle are illustrated. The drawings are not to scale. In the drawings, the same reference numbers designate the same features.

• 1 Figure 12 shows an exemplary arrangement including core circuitry surrounded by a sealing ring and (at least partially) a crack sensor;
• 2 shows a selection of the crack sensor in an optional and exemplary area 105 along the sectional view CC in the xz plane;
• 3 shows a selection of the crack sensor in a region 104 along the sectional view AA in the xz plane;
• 4 shows a selection of the crack sensor along the sectional view BB in the yz plane and
• 5 12 shows an exemplary diagram comprising the core circuitry with a detection unit, with various crack sensors connected to the detection unit.

In particular, examples described herein relate to a solution for (at least one) crack sensor that may partially or fully circumvent or surround core circuitry.

The proposed crack sensor may include a physical structure in close proximity to the core circuitry. Without deformation, the crack sensor includes at least one conductive path that is subject to potential failure. For example, if the conductive path is broken (or its resistance is changed or repeatedly degraded), the failure can be detected by the core circuitry.

A sealing ring may have a specific design surrounding the core circuitry to protect the core circuitry from external influences such as moisture or mechanical stress (cracking, peeling, delamination, etc.). Such protection can be implemented via a continuous metal protection ring consisting of metal strips connected by rods in all metal containing layers.

The sealing ring is located in particular between the at least one crack sensor and the core switching logic.

Mechanical defects at chip edges can be a result of separating, shipping, picking up and/or assembly. Critical defects can propagate horizontally from a sidewall into the active area of the chip, i.e. the core circuitry, causing reliability problems and yield loss. Such defects may be deeply buried within the (silicon) structure and may not be detectable by optical means.

• - eine Kernschaltlogik,
• - einen Dichtring, der die Kernschaltlogik zumindest teilweise umgibt, und
• - einen Risssensor, der den Dichtring (und somit die Kernschaltlogik) zumindest teilweise umgeben kann.

Examples described herein are particularly directed to a chip (or device) comprising

• - a core switching logic,
• - a sealing ring at least partially surrounding the core circuitry, and
• - A crack sensor that can at least partially surround the sealing ring (and thus the core switching logic).

The crack sensor is electrically connected to the core circuitry via a semiconductor layer located below (or above) the metal layers.

Thus, the crack sensor can be placed outside of the sealing ring (and the core circuitry). The crack sensor can encapsulate the core circuitry to detect mechanical failures before they reach the core circuitry.

As an option, the crack sensor can have a (partial) ring structure. In particular, the crack sensor may completely or partially encircle the core circuitry (and the sealing ring). It is also an option that the crack sensor has a linear or any structure other than the ring structure.

It is another option that different crack sensors are provided or that a crack sensor structure includes different crack sensors that (partially) circumscribe the core circuitry (and the sealing ring).

The crack sensor can be electrically connected to the core circuitry without breaking the sealing ring. This can be achieved by an electrical connection between the crack sensor and the core circuitry tunneled through a semiconductor layer of the chip.

The semiconductor layer may include at least one of: a doped substrate, a doped region within the substrate, a polysilicon layer, or a salicide layer.

The crack sensor can include sensor lines that are arranged in loops in such a way that parasitic coil and antenna effects are reduced, in particular minimized. Gaps between crack sensors and/or segments of a crack sensor can also be provided.

1 12 shows an exemplary arrangement comprising core circuitry 101 surrounded by a sealing ring 102. FIG. The combination of the core circuitry 101 and the sealing ring 102 is further (partially) surrounded by a crack sensor 103 .

It should be noted that crack sensor 103 refers to a physical structure that is connected to core circuitry 101 via connections 301,302. The crack sensor 103 includes a conductive path that may utilize metal layers in particular around the sealing ring 102 and - when not compromised due to cracks or other physical defects - provides an electrical connection for the core circuitry 101 to be evaluated. For example, an electrical signal may be applied to connection 301 of crack sensor 103 by core circuitry 101 . When the electrical signal arrives at connection 302, the core circuitry 101 determines that no error has occurred. Accordingly, if no signal is detected at connection 302, the core circuitry 101 may determine that the crack sensor 103 is open due to a mechanical failure. As an option, the electrical signal may be a modulated signal to also determine a resistance value and/or a change in resistance value across the crack sensor 103 .

In the 1 The exemplary arrangement shown is based on a Cartesian coordinate system with an x, y and z axis. 1 shows the xy-plane, while the z-axis is not shown because it extends perpendicularly to the plane of the drawing.

Sectional views A-A, B-B and C-C using different planes are shown in the figures below.

2 shows a selection of the crack sensor 103 in an optional and exemplary area 105 along the sectional view CC in the xz plane. In this example, the crack sensor 103 includes two sections 211 and 212 separated by a gap 201 . Sections 211 and 212 may be separately connected to core circuitry 101 or they may be connected to each other (and) to core circuitry 101 .

The chip comprises seven metal layers M1 to M7 in the z-direction. Each portion of the metal layer is electrically connected in the vertical z-direction via rods to another portion of an adjacent metal layer, as indicated by heavy lines 202 .

in the in 2 In the example shown, an electrical signal may arrive at 203 and be looped through the metal layers M5-M6-M7-M6-M5-M6-M7-M6-M5-M4-M3-M2-M1-M2-M3-M4-M3-M2- M1-M2-M3-M4 and exit the structure at 204.

Accordingly, an electrical signal may arrive at 205 and loop through the metal layers M5-M6-M7-M6-M5-M6-M7-M6-M5-M4-M3-M2-M1-M2-M3-M4-M3-M2-M1 -M2-M3-M4 and exit the structure at 206.

In this example, the crack sensor can use loops to avoid or reduce an antenna effect.

3 shows a selection of the crack sensor 103 in a region 104 along the sectional view AA in the xz plane. In this example, the crack sensor 103 comprises a single loop, and this can extend around the sealing ring 102, as in FIG 1 shown.

In addition to the in 2 includes metal layers shown by way of example 3 a semiconductor layer N-well extending below the sealing ring 102 and used to electrically connect the crack sensor 103 to the core circuitry 101 . Such electrical connections 301, 302 to the core switching logic 101 extend in the y-direction.

Thus, the crack sensor 301 starts in the in 3 shown example at the connection 301 and runs spirally around the sealing ring 102 to an end 303 and from there runs back to the connection 302.

However, it is an option that the crack sensor 301 comprises different sections that are connected to each other or that are connected to the core circuitry 101 respectively. The latter relates also refers to various crack sensors provided around the sealing ring 102 (and the core circuitry 101), each such crack sensor being electrically connected to the core circuitry 101.

It is an option to use different crack sensors. They can be arranged in sections around the sealing ring 102 and/or at least partially around one another.

For example, the crack sensor 103 can be divided into four segments, each segment along an edge of the core circuitry 101 . The four segments can be connected in parallel to share the same connections 301, 302 to the core circuitry 101. Such a segmentation enables an improved determination of the position of the defect.

In particular, it is an option to provide different crack sensors at different distances from the core circuitry.

Furthermore, the electrical signal can be provided to the crack sensors in a multiplexed manner. For example, time multiplexing can be used to apply the signal to different crack sensors at different time slices.

In addition, using different crack sensors allows the location of a defect to be determined or narrowed down.

The electrical signal supplied to the crack sensor can be provided by a (ring) oscillator, which enables a deterioration in the resistance of the crack sensor to be determined.

4 shows a selection of the crack sensor 103 along the sectional view BB in the yz plane.

Here it is shown how the connection 301 is routed from the crack sensor 103 to the core switching logic 101 using the N-well below the metal layers of the sealing ring 102 .

It is also shown that the sealing ring 102 comprises the metal layers M1 to M7 and two additional metal layers M8 and the “last metal” in the z-direction. The last metal layer can be aluminum or the like.

5 10 shows an exemplary diagram comprising the core circuitry 101 with a detection unit 501. Various crack sensors 103a, 103b and 103c are connected to the detection unit 501 of the core circuitry 101. FIG. The crack sensor 103a uses a first connection to the detection unit 501, and the crack sensors 103b and 103c are connected to the detection unit 501 in parallel.

It should be noted that the detection unit 501 may be an integral part of the core circuitry. In addition, more than two crack sensors can be used.

Each of the crack sensors 103a, 103b, and 103c may be located outside of the sealing ring 102 that encircles the core circuitry 101.

The detection unit 501 can include a (ring) oscillator and/or a multiplexer for providing the electrical signal to the crack sensors 103a and 103b/103c.

According to one example, the chip (comprising the core circuitry) can be checked for cracks during and/or after fabrication of a chip by activating the crack sensor. This can be done by an inspection unit, which has an over the connections (see 301 and 302 in 1 ) of the respective crack sensor checks the transmitted signal. In the event of an error, the chip could be discarded.

In another application, the crack sensor can be used after the manufacturing process, e.g. during the runtime of the core circuitry. A crack detected by the detection unit 501 can be further processed, e.g. by switching off the core circuitry that may be affected by the defect and/or by switching to another (redundant) chip and/or by initiating other predefined (safety) measures .

The crack sensor can be in an AOI zone (AOI: automatic optical inspection). The AOI zone can range in size from 4 µm to 10 µm, while the crack sensor can range in size from 0.8 µm to 3 µm (see Fig 4 ).

While various exemplary embodiments of the invention have been disclosed, it will be apparent to those skilled in the art that various changes and modifications can be made that will achieve some of the advantages of the invention without departing from the spirit and scope of the invention. It is obvious to a person skilled in the art that other components performing the same functions can be appropriately substituted. It should be noted that features explained with reference to a specific figure can be combined with features of other figures, even in cases where this is not explicitly mentioned. Furthermore, the methods of the invention can be used in either All software implementations, using the appropriate processor instructions, or in hybrid implementations that use a combination of hardware logic and software logic to achieve the same results. Such modifications of the inventive concept are intended to be covered by the appended claims.

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US8253420B2[0001]

Claims (12)

chip, comprehensive - a core circuitry; - a sealing ring at least partially surrounding the core circuitry; - at least one crack sensor, which is arranged outside of the sealing ring and the core switching logic, - wherein the at least one crack sensor is electrically connected to the core circuitry via a semiconductor layer located beneath metal layers. chip after claim 1 , In which the at least one crack sensor in each case at least partially surrounds the sealing ring. A chip as claimed in any preceding claim, wherein the crack sensor is electrically connected to the core circuitry without breaking the sealing ring. Chip according to one of the preceding claims, in which the crack sensor is located at least partially in an AOI zone. A chip according to any one of the preceding claims, wherein the crack sensor comprises an electrical connection via different metal layers. Chip according to one of the preceding claims, in which the crack sensor comprises an electrical connection which meanders over different metal layers. A chip according to any one of the preceding claims, wherein the semiconductor layer comprises at least one of: - a doped substrate, - a doped region within the substrate, - a polysilicon layer, - a salicide layer. The chip of any preceding claim, wherein the at least one crack sensor comprises multiple segments, each segment being substantially parallel to an edge of the core circuitry. Chip according to one of the preceding claims, in which each of the crack sensors is driven by a multiplexed signal. Chip according to one of the preceding claims, in which the core circuitry is provided for evaluating the status of the at least one crack sensor. Method for determining a status of at least one crack sensor, - in which the at least one crack sensor is located in a chip, - in which the at least one crack sensor is arranged outside of a sealing ring and a core circuitry of the chip, the sealing ring at least partially surrounding the core circuitry, - in which the at least one crack sensor is electrically connected to the core circuitry via a semiconductor layer located below metal layers, - In which the status of the at least one crack sensor is determined by the core switching logic. procedure after claim 11 , in which, when a mechanical error in the at least one crack sensor is detected via the core circuitry, a predetermined action is triggered based on the core circuitry.

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