CN115376905B - Cutting process of semiconductor wafer - Google Patents

Cutting process of semiconductor wafer Download PDF

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Publication number
CN115376905B
CN115376905B CN202211321975.5A CN202211321975A CN115376905B CN 115376905 B CN115376905 B CN 115376905B CN 202211321975 A CN202211321975 A CN 202211321975A CN 115376905 B CN115376905 B CN 115376905B
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Prior art keywords
metal layer
semiconductor wafer
groove
dielectric layer
capacitor
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CN202211321975.5A
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CN115376905A (en
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陈国栋
李洋
周淑霞
李兴坤
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Shandong Zhongqing Intelligent Technology Co ltd
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Shandong Zhongqing Intelligent Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention relates to a semiconductor wafer cutting process, and relates to the technical field of semiconductor packaging. In the semiconductor wafer cutting process, before the semiconductor wafer is cut, each active function area is pre-selected to comprise a plurality of active function units which are arranged in an array mode, so that a first capacitor and a second capacitor which are large in size can be arranged on the periphery of each active function area, and the difference between the performances of the first capacitor and the second capacitor is achieved by arranging that the thickness of the first dielectric layer is smaller than that of the second dielectric layer, and the material of the first dielectric layer is different from that of the second dielectric layer. And due to the existence of the first capacitor and the second capacitor, the cutting stress can be prevented from damaging the active functional region in the subsequent cutting process.

Description

Cutting process of semiconductor wafer
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a semiconductor wafer cutting process.
Background
Semiconductors are used in the fields of integrated circuits, consumer electronics, communication systems, photovoltaic power generation, lighting, high-power conversion, etc., for example, diodes are devices fabricated using semiconductors. The importance of semiconductors is enormous, both from a technological and economic point of view. Most electronic products, such as computers, mobile phones or digital audio recorders, have a core unit closely related to a semiconductor. Common semiconductor materials are silicon, germanium, gallium arsenide, etc., with silicon being the most influential of the various semiconductor material applications. In the specific use of semiconductor devices, a plurality of active devices are usually formed on a semiconductor wafer, and then the semiconductor wafer is cut to form a plurality of discrete active devices. At present, the cutting process of the semiconductor wafer has the defects of complex process, high cost, low yield and the like.
Disclosure of Invention
It is an object of the present invention to overcome the drawbacks of the prior art and to provide a semiconductor wafer dicing process and an active functional block.
More specifically, the present invention relates to a process for dicing a semiconductor wafer, comprising the steps of:
the utility model provides a semiconductor wafer, semiconductor wafer includes a plurality of active functional areas, every active functional area includes a plurality of active functional units that are the array and arrange, every not set up the cutting street between the adjacent active functional unit in the active functional area, every all set up electric capacity around the active functional area and set up district and cutting street, just electric capacity sets up the district and is located correspondingly active functional area with between the cutting street, every active functional area includes first side, second side, third side and fourth side.
Every the electric capacity sets up district and forms first recess and second recess, first recess centers on first side, second side and fourth side, the second recess centers on third side, second side and fourth side.
And forming a first metal layer, a first dielectric layer and a second metal layer which are arranged in a stacked manner in the first groove, wherein the first metal layer, the first dielectric layer and the second metal layer form a first capacitor.
And forming a third metal layer, a second dielectric layer and a fourth metal layer which are stacked in the second groove, wherein the third metal layer, the second dielectric layer and the fourth metal layer form a second capacitor.
The thickness of the first dielectric layer is smaller than that of the second dielectric layer, and the material of the first dielectric layer is different from that of the second dielectric layer.
And carrying out cutting processing on the semiconductor wafer along the cutting paths to form a plurality of separated active functional blocks.
According to an embodiment of the present invention, the semiconductor wafer is one of a silicon wafer, a gallium nitride wafer, a germanium wafer, a gallium arsenide wafer, and a silicon carbide wafer.
According to the embodiment of the invention, the plurality of active functional units arranged in an array comprises N × N active functional units, where N is an integer not less than 5.
According to an embodiment of the present invention, each of the capacitance arrangement regions is provided with a stopper separating the first recess and the second recess.
According to the embodiment of the invention, the first metal layer and the third metal layer are prepared and formed in the same metal deposition process, and the second metal layer and the fourth metal layer are prepared and formed in the same metal deposition process.
According to an embodiment of the present invention, before the first metal layer and the third metal layer are formed, a first electrical lead-out portion is formed at a bottom of the first groove, and a second electrical lead-out portion is formed at a bottom of the second groove, the first electrical lead-out portion being electrically connected to the first metal layer, the second electrical lead-out portion being electrically connected to the third metal layer.
According to the embodiment of the invention, a first gap is formed in the process of forming the second metal layer, a second gap is formed in the process of forming the fourth metal layer, and a buffer medium layer is formed to fill the first gap and the second gap before the semiconductor wafer is subjected to cutting processing.
The invention also relates to an active functional block which is formed by cutting through the semiconductor wafer cutting process.
Compared with the prior art, the invention has the following beneficial effects: in the semiconductor wafer cutting process, before the semiconductor wafer is cut, each active function area is pre-selected and arranged to comprise a plurality of active function units arranged in an array, and then a first capacitor and a second capacitor with large sizes can be arranged on the periphery of each active function area. The thickness of the first dielectric layer is smaller than that of the second dielectric layer, and the material of the first dielectric layer is different from that of the second dielectric layer, so that the performance of the first capacitor is different from that of the second capacitor. And due to the existence of the first capacitor and the second capacitor, the cutting stress can be prevented from damaging the active functional region in the subsequent cutting process.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic top view of a semiconductor wafer according to the present invention;
FIG. 2 is a schematic structural diagram of a first groove and a second groove formed in each capacitor disposition region according to the present invention;
FIG. 3 is a schematic diagram of a structure for forming a first capacitor and a second capacitor according to the present invention;
fig. 4 is a schematic diagram of a single active functional block in the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Furthermore, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Please refer to fig. 1 to 4. It should be noted that the drawings provided in the present embodiment are only for schematically illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
As shown in fig. 1 to 4, the present embodiment provides a semiconductor wafer dicing process, including the following steps:
as shown in fig. 1, a semiconductor wafer 10 is provided, where the semiconductor wafer 10 includes a plurality of active functional regions 100, each active functional region 100 includes a plurality of active functional units 101 arranged in an array, no scribe line is disposed between adjacent active functional units 101 in each active functional region 100, a capacitor setting region 201 and a scribe line 202 are disposed around each active functional region 100, the capacitor setting region 201 is located between the corresponding active functional region 100 and the scribe line 202, and each active functional region 100 includes a first side 1001, a second side 1002, a third side 1003, and a fourth side 1004.
In a specific embodiment, the semiconductor wafer 10 is one of a silicon wafer, a gallium nitride wafer, a germanium wafer, a gallium arsenide wafer, and a silicon carbide wafer.
In a specific embodiment, the plurality of active functional units 101 arranged in an array includes N × N active functional units, where N is an integer not less than 5. The arrangement of the structure can effectively save the occupied area of the cutting channels in the wafer, and further more active functional units 101 can be arranged, so that the occupied area of the wafer is increased, and the purpose of reducing the cost is achieved.
In a more preferred embodiment, the value of N is not greater than 30, thereby facilitating each active functional area 100 to have a suitable number of active functional units, thereby facilitating the free assembly of each active functional area 100 on a PCB board, thereby facilitating the flexible use of each active functional area 100.
As shown in fig. 2, a first groove 301 and a second groove 302 are formed in each of the capacitor placement areas 201, the first groove 301 surrounds the first side 1001, the second side 1002, and the fourth side 1004, and the second groove 302 surrounds the third side 1003, the second side 1002, and the fourth side 1004.
In a specific embodiment, the first recess 301 and the second recess 302 are formed simultaneously by a wet etching process, and more specifically, each of the capacitor disposition regions 201 of the semiconductor wafer 10 may be subjected to a wet etching process using a photoresist mask to form the first recess 301 and the second recess 302 simultaneously.
In a more preferred embodiment, the first recess 301 and the second recess 302 have the same size, so as to simplify the formation process of the first recess 301 and the second recess 302, and further, the ratio of the depth of the first recess 301 and the second recess 302 to the thickness of the semiconductor wafer 10 is 0.8-0.95, so as to form a large-sized first capacitor and a large-sized second capacitor.
In a specific embodiment, a carrier substrate may be disposed under the semiconductor wafer 10 to support the semiconductor wafer 10, and then the first groove 301 and the second groove 302 are formed.
In a specific embodiment, each of the capacitance setting regions 201 is provided with a barrier 303, and the barrier 303 separates the first groove 301 from the second groove 302, in a more specific embodiment, a partial region of the capacitance setting region 201 may not be etched to serve as the barrier 303, in other embodiments, the capacitance setting region 201 is etched in advance, and then a dielectric material such as silicon nitride, silicon oxide, aluminum oxide, or the like is deposited to serve as the barrier 303.
As shown in fig. 3, more specifically, fig. 3 isbase:Sub>A schematic enlarged cross-sectional view taken alongbase:Sub>A-base:Sub>A in fig. 2,base:Sub>A first metal layer 401,base:Sub>A first dielectric layer 402, andbase:Sub>A second metal layer 403 are formed inbase:Sub>A stacked manner in the first groove 301, the first metal layer 401, the first dielectric layer 402, and the second metal layer 403 formbase:Sub>A first capacitor,base:Sub>A third metal layer 501,base:Sub>A second dielectric layer 502, andbase:Sub>A fourth metal layer 503 are formed inbase:Sub>A stacked manner in the second groove 302, and the third metal layer 501, the second dielectric layer 502, and the fourth metal layer 503 formbase:Sub>A second capacitor.
In a specific embodiment, the first metal layer 401 and the third metal layer 501 are formed in the same metal deposition process, and the second metal layer 403 and the fourth metal layer 503 are formed in the same metal deposition process.
In a specific embodiment, the material of the first metal layer 401, the second metal layer 403, the third metal layer 501, and the fourth metal layer 503 is one or more of copper, aluminum, tungsten, titanium, nickel, and silicon, and the first metal layer 401, the second metal layer 403, the third metal layer 501, and the fourth metal layer 503 are formed by electroplating, chemical plating, physical vapor deposition, or chemical vapor deposition.
In a specific embodiment, before the first metal layer 401 and the third metal layer 501 are formed, a first electrical lead-out portion 601 is formed at the bottom of the first groove 301, and a second electrical lead-out portion 602 is formed at the bottom of the second groove 302, wherein the first electrical lead-out portion 601 is electrically connected to the first metal layer 401, and the second electrical lead-out portion 602 is electrically connected to the third metal layer 501.
In a specific embodiment, a first gap is formed during the process of forming the second metal layer 403, a second gap is formed during the process of forming the fourth metal layer 503, and before the semiconductor wafer is subjected to the dicing process, a buffer dielectric layer 700 is formed to fill the first gap and the second gap.
In a specific embodiment, the thickness of the first dielectric layer 402 is smaller than the thickness of the second dielectric layer 502, and the material of the first dielectric layer 402 is different from the material of the second dielectric layer 502, more specifically, the material of the first dielectric layer 402 is silicon nitride, silicon oxynitride or silicon oxide, and the material of the second dielectric layer 502 is zirconium oxide, aluminum oxide or hafnium oxide. The material of the first dielectric layer 402 and the second dielectric layer 502 are formed by a PECVD or ALD process.
As shown in fig. 3, the semiconductor wafer 10 is diced along the dicing streets 202 to form a plurality of separated active functional blocks 800, and a single active functional block 800 is shown in fig. 4.
In a specific embodiment, the carrier substrate is removed and then a dicing process is performed.
As shown in fig. 4, the present invention also provides an active functional block, which is formed by cutting through the above-mentioned semiconductor wafer cutting process.
In the semiconductor wafer cutting process, before the semiconductor wafer is cut, each active function area is pre-selected and arranged to comprise a plurality of active function units which are arranged in an array mode, so that a first capacitor and a second capacitor which are large in size can be arranged on the periphery of each active function area, and the performance difference of the first capacitor and the second capacitor is achieved by arranging that the thickness of the first dielectric layer is smaller than that of the second dielectric layer, and the material of the first dielectric layer is different from that of the second dielectric layer. And due to the existence of the first capacitor and the second capacitor, the active functional region can be prevented from being damaged by cutting stress in the subsequent cutting process.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (8)

1. A semiconductor wafer dicing process, characterized in that: the method comprises the following steps:
providing a semiconductor wafer, wherein the semiconductor wafer comprises a plurality of active function areas, each active function area comprises a plurality of active function units which are arranged in an array mode, a cutting channel is not arranged between every two adjacent active function units in each active function area, a capacitor setting area and a cutting channel are arranged on the periphery of each active function area, the capacitor setting area is located between the corresponding active function area and the cutting channel, and each active function area comprises a first side edge, a second side edge, a third side edge and a fourth side edge;
forming a first groove and a second groove in each capacitor arrangement area, wherein the first groove surrounds the first side edge, the second side edge and the fourth side edge, and the second groove surrounds the third side edge, the second side edge and the fourth side edge;
forming a first metal layer, a first dielectric layer and a second metal layer which are arranged in a stacked mode in the first groove, wherein the first metal layer, the first dielectric layer and the second metal layer form a first capacitor;
forming a third metal layer, a second dielectric layer and a fourth metal layer which are arranged in a stacked mode in the second groove, wherein the third metal layer, the second dielectric layer and the fourth metal layer form a second capacitor;
the thickness of the first dielectric layer is smaller than that of the second dielectric layer, and the material of the first dielectric layer is different from that of the second dielectric layer;
and carrying out cutting processing on the semiconductor wafer along the cutting paths to form a plurality of separated active functional blocks.
2. The process of dicing a semiconductor wafer according to claim 1, wherein: the semiconductor wafer is one of a silicon wafer, a gallium nitride wafer, a germanium wafer, a gallium arsenide wafer, and a silicon carbide wafer.
3. The process for dicing a semiconductor wafer according to claim 1, wherein: the active function units arranged in an array comprise N multiplied by N active function units, wherein N is an integer not less than 5.
4. The process for dicing a semiconductor wafer according to claim 1, wherein: each capacitor setting area is provided with a blocking block, and the first groove and the second groove are separated by the blocking blocks.
5. The process of dicing a semiconductor wafer according to claim 1, wherein: the first metal layer and the third metal layer are prepared and formed in the same metal deposition process, and the second metal layer and the fourth metal layer are prepared and formed in the same metal deposition process.
6. The process of dicing a semiconductor wafer according to claim 5, wherein: before the first metal layer and the third metal layer are formed, a first electric leading-out part is formed at the bottom of the first groove, a second electric leading-out part is formed at the bottom of the second groove, the first electric leading-out part is electrically connected with the first metal layer, and the second electric leading-out part is electrically connected with the third metal layer.
7. The process of dicing a semiconductor wafer according to claim 1, wherein: and forming a first gap in the process of forming the second metal layer, forming a second gap in the process of forming the fourth metal layer, and forming a buffer medium layer to fill the first gap and the second gap before the semiconductor wafer is cut.
8. An active functional block cut by the dicing process for a semiconductor wafer according to any one of claims 1 to 7.
CN202211321975.5A 2022-10-27 2022-10-27 Cutting process of semiconductor wafer Active CN115376905B (en)

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CN116913773B (en) * 2023-09-12 2024-01-26 威海市泓淋电力技术股份有限公司 Semiconductor chip and forming method thereof

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