DE102013109531B4 - Apparatus and method for a packaging reinforcement - Google Patents
Apparatus and method for a packaging reinforcement Download PDFInfo
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- DE102013109531B4 DE102013109531B4 DE102013109531.3A DE102013109531A DE102013109531B4 DE 102013109531 B4 DE102013109531 B4 DE 102013109531B4 DE 102013109531 A DE102013109531 A DE 102013109531A DE 102013109531 B4 DE102013109531 B4 DE 102013109531B4
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- package component
- electrical connections
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- potting
- package
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Abstract
Vorrichtung, die aufweist:
eine Packagekomponente, wobei die Packagekomponente eine erste Seite und eine zweite Seite sowie eine Dicke (T) aufweist;
eine Vielzahl elektrischer Verbindungen auf der zweiten Seite der Packagekomponente;
ein Bauteil, das mit der Vielzahl elektrischer Verbindungen elektrisch verbunden ist; eine Vergussmasse auf der zweiten Seite der Packagekomponente, wobei die Vergussmasse eine erste Höhe (H1) aufweist, und wobei sich die Vielzahl elektrischer Verbindungen durch die Vergussmasse erstreckt; und
eine Vergussunterfüllung zwischen der Vergussmasse und dem Bauteil, wobei die Vergussunterfüllung sämtliche oder eine Teilmenge der Vielzahl elektrischer Verbindungen verkapselt und sich mit einer zweiten Höhe (H2) entlang einer oder mehrerer vertikaler Seiten der Packagekomponente erstreckt,
dadurch gekennzeichnet, dass zwischen den Höhen (H1, H2) und der Dicke (T) ein Verhältnis von 1/3(H1 + T) ≤ (H1 +H2) < (H1 + T) besteht.
Apparatus comprising:
a package component, the package component having a first side and a second side and a thickness (T);
a plurality of electrical connections on the second side of the package component;
a component electrically connected to the plurality of electrical connections; a potting compound on the second side of the package component, the potting compound having a first height (H1), and the plurality of electrical connections extending through the potting compound; and
a potting underfill between the potting compound and the component, the potting underfill encapsulating all or a subset of the plurality of electrical connections and extending with a second height (H2) along one or more vertical sides of the package component
characterized in that between the heights (H1, H2) and the thickness (T) there is a ratio of 1/3 (H1 + T) ≤ (H1 + H2) <(H1 + T).
Description
Die Erfindung geht aus von einer Packagekomponente sowie einem Verfahren zur Herstellung der Packagekomponente, wobei die Packagekomponente eine erste Seite und eine zweite Seite sowie eine Vielzahl elektrischer Verbindungen auf der zweiten Seite der Packagekomponente aufweist. Außerdem weist die Packagekomponente ein Bauteil auf, das mit der Vielzahl elektrischer Verbindungen elektrisch verbunden ist sowie eine Vergussunterfüllung zwischen der Vergussmasse und dem Bauteil, wobei die Vergussunterfüllung eine Teilmenge der Vielzahl elektrischer Verbindungen verkapselt. Eine derartige Vorrichtung ist aus der Druckschrift
HINTERGRUNDBACKGROUND
Seit der Erfindung des integrierten Schaltkreises (IC) hat die Halbleiterindustrie aufgrund der fortwährenden Verbesserungen der Integrationsdichte verschiedener elektronischer Komponenten (d.h. Transistoren, Dioden, Widerstände, Kondensatoren, usw.) ein rasches Wachstum erfahren. Größtenteils ist diese Verbesserung der Integrationsdichte aus der wiederholten Verkleinerung der minimalen Bauteilgröße hervorgegangen, was es ermöglicht, dass mehr Komponenten in einen gegebenen Bereich integriert werden können. Diese kleineren elektronischen Komponenten haben zu kleineren Packages geführt, welche weniger Platz einnehmen als die zuvor verwendeten Packagearten. Einige kleinere Arten von Packages für Halbleiterbauteile umfassen Quad Flat Pack (QFP), Pin Grid Array (PGA), Ball Grid Array (BGA), Flip Chips (FC), dreidimensionale integrierte Schaltkreise (3D ICs), Waferlevelpackages (WLPs) sowie Package-auf-Package-Bauteile (PoP). Diese Packagearten sind anfällig gegenüber Verspannungen und Belastungen, wodurch die elektrischen Verbindungen zwischen einem Package und einem Bauteil, mit dem das Package elektrisch verbunden ist, beschädigt werden können.Since the invention of the integrated circuit (IC), the semiconductor industry has grown rapidly due to the continued improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has resulted from repeated downsizing of the minimum component size, which allows more components to be integrated into a given area. These smaller electronic components have resulted in smaller packages that take up less space than the previously used package types. Some smaller types of packages for semiconductor components include Quad Flat Pack (QFP), Pin Grid Array (PGA), Ball Grid Array (BGA), Flip Chips (FC), Three-Dimensional Integrated Circuits (3D ICs), Wafer Level Packages (WLPs), and Package on-package components (PoP). These types of packages are susceptible to tension and stress, as a result of which the electrical connections between a package and a component to which the package is electrically connected can be damaged.
Der Erfindung liegt daher die Aufgabe zugrunde, eine gattungsgemäße Packagekomponente sowie ein Verfahren zur Herstellung der Packagekomponente derart weiterzuentwickeln, dass diese eine hohe Stabilität aufweist.The invention is therefore based on the object of further developing a generic package component and a method for producing the package component in such a way that it has a high level of stability.
Diese Aufgabe wird von einer Packagekomponente nach Anspruch 1 sowie einem Verfahren zur Herstellung der Packagekomponente nach Anspruch 11 gelöst. Vorteilhafte Ausgestaltungen sind Gegenstand der abhängigen Ansprüche 2 bis 10 und 12 bis 15.This object is achieved by a package component according to claim 1 and a method for producing the package component according to claim 11. Advantageous refinements are the subject matter of the
Für ein umfassenderes Verständnis der vorliegenden Ausführungsformen sowie deren Vorteile wird nunmehr Bezug auf die nachstehende Beschreibung in Verbindung mit den begleitenden Zeichnungen genommen, bei welchen:
- die
1A eine Querschnittsansicht eines verstärkten Package gemäß einer Ausführungsform veranschaulicht; - die
1B eine vereinfachte Draufsicht auf die Oberseite der Vorrichtung gemäß1A veranschaulicht; - die
1C eine Teilquerschnittsansicht des verstärkten Package gemäß der1A veranschaulicht; - die
2A eine Querschnittsansicht eines weiteren verstärkten Package gemäß einer anderen Ausführungsform veranschaulicht; - die
2B eine vereinfachte Draufsicht auf die Vorrichtung gemäß2A veranschaulicht; - die
3A eine Querschnittsansicht eines weiteren verstärkten Package gemäß einer anderen Ausführungsform veranschaulicht; - die
3B eine vereinfachte Draufsicht auf die Oberseite der Vorrichtung gemäß3A veranschaulicht; - die
4 eine Teilquerschnittsansicht noch eines anderen verstärkten Package veranschaulicht, und - die
5 ein Verfahren gemäß einer Ausführungsform veranschaulicht.
- the
1A illustrates a cross-sectional view of a reinforced package according to an embodiment; - the
1B a simplified plan view of the top of the device according to1A illustrates; - the
1C FIG. 3 is a partial cross-sectional view of the reinforced package according to FIG1A illustrates; - the
2A illustrates a cross-sectional view of another reinforced package in accordance with another embodiment; - the
2 B a simplified plan view of the device according to2A illustrates; - the
3A illustrates a cross-sectional view of another reinforced package in accordance with another embodiment; - the
3B a simplified plan view of the top of the device according to3A illustrates; - the
4th FIG. 11 illustrates a partial cross-sectional view of yet another reinforced package, and FIG - the
5 illustrates a method according to an embodiment.
GENAUE BESCHREIBUNGPRECISE DESCRIPTION
Die Herstellung und die Verwendung der Ausführungsformen der vorliegenden Offenbarung werden nachstehend im Detail diskutiert. Es sollte jedoch anerkannt werden, dass die vorliegende Offenbarung viele anwendbare erfindungsgemäße Konzepte beschreibt, die auf einem breiten Gebiet spezifischer Zusammenhänge umgesetzt werden können. Die diskutierten, spezifischen Ausführungsformen sind lediglich veranschaulichend für besondere Weisen, um aus dem offenbarten Gegenstand Nutzen zu ziehen, sie sollen jedoch nicht den Umfang der verschiedenen Ausführungsformen beschränken. Über die verschiedenen Ansichten und veranschaulichenden Ausführungsformen hinweg werden identische Bezugszeichen dazu verwendet, identische Elemente zu bezeichnen.The making and using of the embodiments of the present disclosure are discussed in detail below. It should be recognized, however, that the present disclosure describes many applicable inventive concepts that can be practiced in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of particular ways to benefit from the disclosed subject matter, but are not intended to limit the scope of the various embodiments. Identical reference numbers are used to refer to identical elements throughout the several views and illustrative embodiments.
Die
Die MUF
Die
Die MUF
Bei verschiedenen Ausführungsformen kann die MUF
Die
Wie in
Bei verschiedenen Ausführungsformen kann, wie es nachstehend noch genauer diskutiert wird, das Package
Bei verschiedenen Ausführungsformen kann die Packagekomponente
Bei verschiedenen Ausführungsformen kann die Vergussmasse
Bei verschiedenen Ausführungsformen kann das Bauteil
Die Größe, Form, Art, Zusammensetzung und/oder Anordnung der Packagekomponente
Die
Wie in
Bei verschiedenen Ausführungsformen kann die MUF
Die
Die Konfiguration der MUF
Jeder der in
Die
Bei einer Ausführungsform kann die MUF
Bei verschiedenen Ausführungsformen kann die MUF
Die
Die Konfiguration der MUF
Wie in
Die
Über die Vielzahl elektrischer Verbindungen
Wie in
Bei verschiedenen Ausführungsformen kann die MUF
Bei verschiedenen Ausführungsformen kann das Substrat
Bei verschiedenen Ausführungsformen kann das Verbindungspad bzw. können die Anschlusspads
Bei verschiedenen Ausführungsformen kann die erste und/oder die zweite Passivierungsschicht
Bei verschiedenen Ausführungsformen kann die Vielzahl elektrischer Verbindungen
Bei verschiedenen Ausführungsformen sind die PPIs
Die
Das Verfahren
Die Vergussunterfüllung kann dazu ausgebildet werden, einen Teilsatz der elektrischen Verbindungen zu verkapseln. Beispielsweise kann die Vergussunterfüllung einen Teilsatz von X Reihen und Y Spalten der Vielzahl elektrischer Verbindungen entlang einem Umfang der Packagekomponente verkapseln. Die Anzahl der X Reihen kann kleiner als (N/2)-1 der Gesamtzahl der N Reihen, und die Anzahl der Y Spalten kann kleiner als (M/2)-1 der M Spalten der elektrischen Verbindungen sein.The potting underfill can be configured to encapsulate a subset of the electrical connections. For example, the potting underfill may encapsulate a subset of X rows and Y columns of the plurality of electrical connections along a perimeter of the package component. The number of X rows can be less than (N / 2) -1 of the total number of N rows, and the number of Y columns can be less than (M / 2) -1 of the M columns of electrical connections.
Das Volumen der zwischen der Packagekomponente und dem Substrat entlang dem Umfang injizierten Vergussunterfüllung kann dazu variiert werden, um die Anzahl der X Reihen und der Y Spalten elektrischer Verbindungen, welche von der Vergussunterfüllung vollständig verkapselt sind, anzupassen. Beispielsweise kann das Volumen der injizierten Vergussunterfüllung erhöht werden, um weitere der X Reihen und Y Spalten elektrischer Verbindungen entlang des Umfangs zu verkapseln, und es kann verringert werden, um weniger der X Reihen und Y Spalten elektrischer Verbindungen entlang des Umfangs der Packagekomponente zu verkapseln. Darüber hinaus können einige der elektrischen Verbindungen an der Innenseite der Packagekomponente von der Vergussunterfüllung kontaktiert sein, wobei sie jedoch nicht vollständig von der Vergussunterfüllung verkapselt sind. Es wird nochmals darauf hingewiesen, dass das Volumen der aufgebrachten Vergussunterfüllung zwischen der Packagekomponente und dem Substrat die Anzahl der elektrischen Verbindungen bestimmt, welche vollständig von der Vergussunterfüllung verkapselt sind, bzw. der elektrischen Verbindungen, die zwar kontaktiert, jedoch nicht vollständig verkapselt sind.The volume of the potting underfill injected along the circumference between the package component and the substrate can be varied in order to adapt the number of X rows and Y columns of electrical connections which are completely encapsulated by the potting underfill. For example, the volume of the injected potting underfill can be increased to encapsulate more of the X rows and Y columns of electrical connections along the perimeter, and it can be decreased to encapsulate fewer of the X rows and Y columns of electrical connections along the perimeter of the package component. In addition, some of the electrical connections on the inside of the package component can be contacted by the potting underfill, but they are not completely encapsulated by the potting underfill. It is pointed out once again that the volume of the potting underfill applied between the package component and the substrate determines the number of electrical connections that are completely encapsulated by the potting underfill or the electrical connections that are contacted but not completely encapsulated.
Bei einem anderen Beispiel kann die Vergussunterfüllung eine Vielzahl Teilsätze der Vielzahl elektrischer Verbindungen an einer Vielzahl Ecken der Packagekomponente verkapseln. Bei einer derartigen Ausführungsform kann jeder der Vielzahl Sätze einen Satz von X Reihen mal Y Spalten der Vielzahl elektrischer Verbindungen an einer Ecke der Packagekomponente aufweisen, wobei X zwischen 2 und (N/2)-1 der Gesamtzahl aus N Reihen und Y zwischen 2 und (N/2)-1 der Gesamtzahl M Spalten elektrischer Verbindungen liegen kann. Es kann wiederum das Volumen der zwischen der Packagekomponente und dem Substrat injizierten Vergussunterfüllung an einer bestimmten Ecke variiert werden, um die Anzahl der X Reihen und der Y Spalten elektrischer Verbindungen, welche vollständig von der Vergussunterfüllung verkapselt sind, anzupassen.In another example, the potting underfill may encapsulate a plurality of subsets of the plurality of electrical connections at a plurality of corners of the package component. In such an embodiment, each of the plurality of sets may include a set of X rows by Y columns of the plurality of electrical connections at a corner of the package component, where X is between 2 and (N / 2) -1 of the total of N rows and Y is between 2 and (N / 2) -1 of the total number of M columns of electrical connections. In turn, the volume of the potting underfill injected between the package component and the substrate can be varied at a certain corner in order to adapt the number of X rows and Y columns of electrical connections which are completely encapsulated by the potting underfill.
Gemäß einer Ausführungsform wird eine Vorrichtung bereitgestellt. Die erfindungsgemäße Vorrichtung umfasst: eine Packagekomponente, wobei die Packagekomponente eine erste Seite und eine zweite Seite sowie eine Dicke T aufweist; eine Vielzahl elektrischer Verbindungen auf der zweiten Seite der Packagekomponente; ein Bauteil, das mit der Vielzahl elektrischer Verbindungen elektrisch verbunden ist; eine Vergussmasse auf der zweiten Seite der Packagekomponente, wobei die Vergussmasse eine erste Höhe H1 aufweist, und wobei sich die Vielzahl elektrischer Verbindungen durch die Vergussmasse erstreckt; und eine Vergussunterfüllung zwischen der Vergussmasse und dem Bauteil, wobei die Vergussunterfüllung eine Teilmenge der Vielzahl elektrischer Verbindungen verkapselt und sich mit einer zweiten Höhe H2 entlang einer oder mehrerer vertikaler Seiten der Packagekomponente erstreckt, wobei zwischen den Höhen H1, H2 und der Dicke T ein Verhältnis von 1/3(H1 + T) ≤ (H1 +H2) < (H1 + T) besteht.According to one embodiment, an apparatus is provided. The device according to the invention comprises: a package component, the package component having a first side and a second side as well as a thickness T; a plurality of electrical connections on the second side of the package component; a component electrically connected to the plurality of electrical connections; a potting compound on the second side of the package component, the potting compound having a first height H1, and the plurality of electrical connections extending through the potting compound; and a potting underfill between the potting compound and the component, the potting underfill encapsulating a subset of the plurality of electrical connections and extending at a second height H2 along one or more vertical sides of the package component, with a ratio between the heights H1, H2 and the thickness T of 1/3 (H1 + T) ≤ (H1 + H2) <(H1 + T).
Bei einer anderen Ausführungsform wird eine andere Vorrichtung bereitgestellt. Die Vorrichtung umfasst: ein erstes Substrat, das eine erste Seite und eine zweite Seite aufweist; eine Vielzahl elektrischer Verbindungen, die auf der zweiten Seite des ersten Substrates ausgebildet sind; ein zweites Substrat, das mit der einen oder den mehreren elektrischen Verbindungen elektrisch verbunden ist; und eine Vergussunterfüllung, die unmittelbar zwischen dem ersten Substrat und dem zweiten Substrat angeordnet ist, wobei die Vergussunterfüllung zumindest einen Anschluss verkapselt, der über der zweiten Seite des ersten Substrates ausgebildet ist.In another embodiment, a different device is provided. The device includes: a first substrate having a first side and a second side; a plurality of electrical connections formed on the second side of the first substrate; a second substrate electrically connected to the one or more electrical connections; and a potting underfill, which is arranged directly between the first substrate and the second substrate, wherein the potting underfill encapsulates at least one connection that is formed over the second side of the first substrate.
Gemäß einer anderen Ausführungsform wird ein Verfahren bereitgestellt. Das Verfahren umfasst das Bereitstellen einer Packagekomponente mit einer Dicke T, wobei die Packagekomponente eine Vielzahl elektrischer Verbindungen und eine Vergussmasse auf einer ersten Seite aufweist, wobei sich die Vergussmasse bis zu einer ersten Höhe H1 erstreckt; das Verbinden der Packagekomponente mit einem Substrat unter Verwendung der Vielzahl elektrischer Verbindungen; und das Ausbilden einer Vergussunterfüllung, um eine Teilmenge der Vielzahl elektrischer Verbindungen zwischen der Packagekomponente und dem Substrat zu verkapseln, wobei die Vergussunterfüllung entlang einer oder mehrerer vertikaler Seiten der Packagekomponente mit einer Höhe H2 ausgebildet wird und zwischen den Höhen H1, H2 und der Dicke T ein Verhältnis von 1/3(H1 + T) ≤ (H1 +H2) < (H1 + T) besteht.According to another embodiment, a method is provided. The method comprises providing a package component with a thickness T, the package component having a plurality of electrical connections and a potting compound on a first side, the potting compound extending up to a first height H1; connecting the package component to a substrate using the plurality of electrical connections; and forming a potting underfill to encapsulate a subset of the plurality of electrical connections between the package component and the substrate, the potting underfill being formed along one or more vertical sides of the package component with a height H2 and between the heights H1, H2 and the thickness T. there is a ratio of 1/3 (H1 + T) ≤ (H1 + H2) <(H1 + T).
Claims (15)
Applications Claiming Priority (28)
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US201261746687P | 2012-12-28 | 2012-12-28 | |
US61/746,687 | 2012-12-28 | ||
US13/751,289 US9263839B2 (en) | 2012-12-28 | 2013-01-28 | System and method for an improved fine pitch joint |
US13/751,289 | 2013-01-28 | ||
US201361765322P | 2013-02-15 | 2013-02-15 | |
US61/765,322 | 2013-02-15 | ||
US201361776714P | 2013-03-11 | 2013-03-11 | |
US201361776684P | 2013-03-11 | 2013-03-11 | |
US201361776282P | 2013-03-11 | 2013-03-11 | |
US61/776,282 | 2013-03-11 | ||
US61/776,684 | 2013-03-11 | ||
US61/776,714 | 2013-03-11 | ||
US201361777709P | 2013-03-12 | 2013-03-12 | |
US201361778341P | 2013-03-12 | 2013-03-12 | |
US61/777,709 | 2013-03-12 | ||
US61/778,341 | 2013-03-12 | ||
US13/838,748 US9257333B2 (en) | 2013-03-11 | 2013-03-15 | Interconnect structures and methods of forming same |
US13/838,748 | 2013-03-15 | ||
US13/868,554 US8987058B2 (en) | 2013-03-12 | 2013-04-23 | Method for wafer separation |
US13/868,554 | 2013-04-23 | ||
US13/914,426 | 2013-06-10 | ||
US13/913,599 US10015888B2 (en) | 2013-02-15 | 2013-06-10 | Interconnect joint protective layer apparatus and method |
US13/913,599 | 2013-06-10 | ||
US13/914,426 US9589862B2 (en) | 2013-03-11 | 2013-06-10 | Interconnect structures and methods of forming same |
US13/934,562 US9401308B2 (en) | 2013-03-12 | 2013-07-03 | Packaging devices, methods of manufacture thereof, and packaging methods |
US13/934,562 | 2013-07-03 | ||
US13/939,966 US9287143B2 (en) | 2012-01-12 | 2013-07-11 | Apparatus for package reinforcement using molding underfill |
US13/939,966 | 2013-07-11 |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11163049A (en) * | 1997-11-28 | 1999-06-18 | Matsushita Electric Ind Co Ltd | Structure and method of mounting electronic component with bump |
US7118940B1 (en) * | 2005-08-05 | 2006-10-10 | Delphi Technologies, Inc. | Method of fabricating an electronic package having underfill standoff |
US20110128711A1 (en) * | 2009-11-30 | 2011-06-02 | Myung Jin Yim | Package including an underfill material in a portion of an area between the package and a substrate or another package |
US20140252601A1 (en) * | 2013-03-11 | 2014-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect Structures and Methods of Forming Same |
-
2013
- 2013-09-02 DE DE102013109531.3A patent/DE102013109531B4/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11163049A (en) * | 1997-11-28 | 1999-06-18 | Matsushita Electric Ind Co Ltd | Structure and method of mounting electronic component with bump |
US7118940B1 (en) * | 2005-08-05 | 2006-10-10 | Delphi Technologies, Inc. | Method of fabricating an electronic package having underfill standoff |
US20110128711A1 (en) * | 2009-11-30 | 2011-06-02 | Myung Jin Yim | Package including an underfill material in a portion of an area between the package and a substrate or another package |
US20140252601A1 (en) * | 2013-03-11 | 2014-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect Structures and Methods of Forming Same |
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