DE102008062452B4 - Method and device for frequency-independent regulation of the pulse duty factor - Google Patents

Abstract

Method for regulating the pulse duty factor of at least one periodic signal, in which the pulse duty factor is corrected to a predetermined target value using the ratio of the half-wave durations (t1-t8) of two half-waves (HW1-HW8) of the periodic signal (V_0) the half-wave duration (t1-t8) of a half-wave (HW1-HW8) to correct the duty cycle - a capacitor (812, 822) is brought into an initial state in which the capacitor (812, 822) is charged, - the capacitor (812, 822) is discharged during the half-wave duration (t1-t8) of the half-wave (HW1-HW8) starting from the initial state and based on the state of charge of the capacitor (812, 822) at the end of the half-wave (HW1-HW8), which is a characteristic value for the Half-wave duration (t1-t8) of the half-wave (HW1-HW8) represents the duty cycle is corrected, characterized in that to correct the duty cycle, a first capacitor (812) during the half-wave duration (t1, t3, t5 , t7) of a first half-wave (HW1, HW3, HW5, HW7) and a second capacitor (822) during the half-wave duration (t2, t4, t6, t8) of a second, from the first half-wave (HW1, HW3, HW5, HW7) different half-wave (HW2, HW4, HW6, HW8) is discharged, the state of charge of the first capacitor (812) at the end of the first half-wave (HW1, HW3, HW5, HW7) a characteristic value for the half-wave duration (t1, t3, t5, t7 ) of the first half-cycle (HW1, HW3, HW5, HW7) and the state of charge of the second capacitor (822) at the end of the second half-cycle (HW2, HW4, HW6, HW8) a characteristic value for the half-wave duration (t2, t4, t6, t8) of the second half-wave (HW2, HW4, HW6, HW8) and the duty cycle is corrected on the basis of the difference (DV) of the charge states of the two capacitors (812, 822).

Description

The invention relates to a method for regulating the pulse duty factor of at least one periodic signal according to the preamble of claim 1 and a device for controlling the pulse duty factor.

In a method of this type, the pulse duty factor is corrected to a predetermined desired value on the basis of the ratio of the half-wave durations of two half-waves of a periodic signal.

When regulating the speed of a motor, a rotary movement of a rotatable part of the motor (e.g. the motor shaft) is usually determined by recording two periodic sinusoidal signals that are phase-shifted by 90 °. The sinusoidal signals can be generated, for example, by offset sensors (e.g. Hall sensors) that record the movement of the moving part, each of which generates an approximately sinusoidal signal that is correlated with the rotary movement of the part. However, since the generated signals can be incorrect in their amplitude, their phase and their constant component (offset) and their shape can also be distorted, the signals must be corrected in order to be able to record the speed and position of the rotatable part exactly.

Simple correction methods, for example, adjust the amplitudes of a positive and a negative half-wave of the periodic signal to one another by shifting the signal as a whole by adjusting the constant component (offset). The detection of signal errors occurs only selectively with a fixed cycle or at fixed angular positions, so that in the case of distorted signals that deviate significantly from a sinusoidal shape, an incorrect correction value may be determined, which tends to worsen the signal shape and improve the accuracy in determining the speed and the position of the rotatable part decreases.

In order to ensure an exact determination of the speed and the position of the rotatable part of the motor, the generated periodic signals are therefore regulated and corrected in such a way that their pulse duty factor corresponds to a predetermined target value.

The duty cycle is to be understood here as the ratio of the time duration (half-wave duration) of two half-waves of the periodic signal. With a pulse duty factor of 1: 1, the half-wave durations of the half-waves of the periodic signal are identical and the zero crossings of the periodic signal are at the same distance.

With one from the DE 35 14 155 A1 known method for regulating the pulse duty factor in a position measuring system, a periodic signal is regulated to a constant target pulse duty factor by a control amplifier generating a difference signal by comparing the specified target pulse duty factor with an instantaneous actual pulse duty factor, which is fed to an actuating unit to generate an actuating signal . To correct the duty cycle, the control signal is then superimposed on the actual signal.

With one from the U.S. 4,475,086 A known method, a counter is used which counts incrementally upwards during a first half-cycle and incrementally downwards again during a subsequent second half-cycle. The counter value at the end of the second half-cycle indicates a key figure for the difference between the half-cycle durations of the two half-waves, and the duty cycle is adapted as a function of this key figure.

With one from the DE 103 20 794 B3 Known methods for correcting a pulse duty factor of a clock signal use a pulse duty factor changing device and pulse duty factor determination devices, a pulse duty factor of 50 percent being set.

Conventional methods that use a counter to determine and correct the pulse duty factor that determines a difference between the half-wave durations of two half-waves are frequency-dependent, due to the fact that at high frequencies of the periodic signal to be corrected, the difference in the half-wave durations is small, although that The pulse duty factor may deviate significantly from the setpoint to be set. The counter, which usually works linearly using a fixed clock, cannot detect such a small difference in the half-wave durations with sufficient accuracy, so that the sensitivity of the duty cycle correction decreases with increasing frequency.

The present invention is based on the object of creating a method and a device for regulating the duty cycle of at least one periodic signal which allow duty cycle correction largely independent of the frequency of the periodic signal with sufficient sensitivity even at high frequencies.

This object is achieved by a method with the features of claim 1.

• - ein Kondensator in einen Ausgangszustand gebracht wird, in dem der Kondensator geladen ist,
• - der Kondensator während der Halbwellendauer der Halbwelle ausgehend von dem Ausgangszustand entladen wird und
• - anhand des Ladezustands des Kondensators am Ende der Halbwelle, der einen Kennwert für die Halbwellendauer der Halbwelle darstellt, das Tastverhältnis korrigiert wird.

According to the invention it is provided that to determine a characteristic value for the Half-wave duration of a half-wave to correct the duty cycle

• - a capacitor is brought into an initial state in which the capacitor is charged,
• - The capacitor is discharged during the half-wave duration of the half-wave starting from the initial state and
• - The duty cycle is corrected based on the state of charge of the capacitor at the end of the half cycle, which represents a characteristic value for the half cycle duration of the half cycle.

The present invention is based on the idea of using a circuit arrangement with a capacitor instead of a counter for the (linear) determination of the half-wave duration of a half-wave and utilizing the characteristic curve of the discharge behavior of the capacitor in order to achieve sufficient accuracy in the duty cycle correction, especially in the case of periodic signals of high frequency to reach. To determine a characteristic value for the half-wave duration of a half-wave, the capacitor is first charged to a defined initial state by applying a voltage. During the half-wave duration of the half-wave, the capacitor is then discharged and at the end of the half-wave it is in a state of charge in which residual charge is still stored in the capacitor. This state of charge depends on the half-wave duration, which specifies the time during which the capacitor can discharge.

In order to increase the accuracy in the duty cycle correction, especially at high frequencies of the periodic signal, the (negative) exponential characteristic of the capacitor is used, which means that the capacitor initially discharges comparatively quickly during the half-wave duration to be recorded, but the discharge speed over time decreases. This means that in the case of high-frequency signals (whose half-waves have a short half-wave duration), a small time difference between the half-wave duration of two half-waves leads to a large difference in the states of charge at the end of the respective half-wave.

In principle, it is possible to correct the pulse duty factor of a periodic signal having two half-waves using just one capacitor. For this purpose, the characteristic value for the half-wave duration of the first half-wave can first be determined via the capacitor and temporarily stored by means of a so-called sample & hold element. The characteristic value for the second half-wave duration is then determined with the same capacitor and, if both characteristic values are available, the pulse duty factor is corrected. Alternatively, it is also possible to digitize and digitally process the charge states of the capacitor corresponding to the characteristic values at the end of the first half-cycle and at the end of the second half-cycle using an analog-digital converter.

In order to correct the duty cycle, two capacitors are provided, of which a first capacitor provides a characteristic value for the half-wave duration of a first half-cycle and a second capacitor a characteristic value for the half-wave duration of a second half-cycle different from the first half-cycle. The two half-waves represent a positive and a negative half-wave of the periodic signal, the duty cycle of which is to be regulated to a value of 1: 1, for example. As part of the duty cycle correction, the first capacitor is discharged during the half-wave duration of the first half-cycle and the second capacitor is discharged during the half-wave duration of the second half-cycle. The state of charge of the first capacitor at the end of the first half cycle indicates a characteristic value for the half cycle duration of the first half cycle, while the state of charge of the second capacitor at the end of the second half cycle provides a characteristic value for the half cycle duration of the second half cycle. The charge states of the capacitors at the end of the two half-waves are then stored in the capacitors, and the duty cycle is corrected based on the difference in the charge states of the two capacitors.

To correct the pulse duty factor, a control signal can be generated based on the difference in the charge states of the capacitors. The charge states of the capacitors can be compared with one another via at least one comparator, with the control signal incrementing, decrementing or unchanging the counter value of a correction counter for correcting the duty cycle, depending on the output value of the at least one comparator. Depending on the counter value of the correction counter, for example, the direct component (offset) of the periodic signal to be corrected is adapted, the correction being repeated until the pulse duty factor has reached the desired target value.

• - inkrementiert, wenn die Differenz der Ladezustände der Kondensatoren eine positive Relevanzschwelle überschreitet,
• - dekrementiert, wenn die Differenz der Ladezustände der Kondensatoren eine negative Relevanzschwelle unterschreitet,
• - unverändert lässt, wenn die Differenz der Ladezustände der Kondensatoren zwischen der positiven Relevanzschwelle und der negativen Relevanzschwelle liegt.

The charge states of the capacitors are advantageously compared with one another via two parallel comparators, the control signal being the counter value of a correction counter based on the output values of the two comparators

• - incremented when the difference in the charge states of the capacitors exceeds a positive relevance threshold,
• - decremented when the difference in the charge states of the capacitors falls below a negative relevance threshold,
• - leaves unchanged if the difference in the charge states of the capacitors is between the positive relevance threshold and the negative relevance threshold.

For this purpose, a voltage signal from the first capacitor (positive input of the first comparator) and a voltage signal from the second capacitor increased by the negative relevance threshold (negative input of the first comparator) can be applied to the first comparator. Conversely, the voltage signal of the second capacitor (positive input of the second comparator) and the voltage signal of the first capacitor increased by the positive relevance threshold (negative input of the second comparator) are applied to the second comparator.

To correct the duty cycle of the periodic signal, a square-wave signal is preferably formed from the periodic signal and the duty cycle is corrected on the basis of the square-wave signal. The capacitor can be connected in a circuit arrangement with switches which control the charging and discharging of the capacitor and whose switching states for charging and discharging the capacitor are switched via a control logic. From the square-wave signal, the control logic determines the edges of the square-wave signal and switches the switches based on the edges in order to charge the capacitor and start and end a discharge process.

For example, for charging, the capacitor can be connected to an output voltage via a first switch, which brings the capacitor into an output state with a predetermined charge. For discharging, the first switch is opened and the capacitor is connected to a resistor via a second switch, so that the capacitor forms an RC element together with the resistor. The capacitor is discharged via the resistor, and at the end of the half-cycle - determined by the control logic based on the corresponding edge of the square-wave signal - the second switch is also opened and the state of charge at the end of the half-cycle is thus stored in the capacitor.

In an advantageous method for correcting the duty cycle, the duty cycle is alternately corrected based on the ratio of the half-wave duration of a positive half-wave to the half-wave duration of a subsequent negative half-wave and the ratio of the half-wave duration of a negative half-wave to the half-wave duration of a subsequent positive half-wave.

This is based on the idea of not correcting the pulse duty factor in a fixed manner based on the ratio of a positive to a negative half-wave duration (or vice versa), but instead alternately. In a first step, for example, the duty cycle is initially corrected on the basis of the ratio of the half-wave duration of a positive half-wave to the half-wave duration of a subsequent negative half-wave. Then, conversely, the duty cycle is corrected based on the ratio of the half-wave duration of a negative half-wave to the half-wave duration of a subsequent positive half-wave. Then a positive half-wave is related to a negative, then a negative to a positive half-wave, and so on.

The alternating duty cycle correction carried out in this way has the effect that if the frequency of the periodic signal to be corrected changes - for example, if the frequency increases as a result of an acceleration of a moving part of a motor to be detected - a correction is made in different directions and thus overall an incorrect duty cycle correction as a result of a frequency-variable signal is avoided.

For example, in the case of a periodic signal with an increasing frequency, the half-wave durations of successive half-waves become shorter and shorter. The alternating duty cycle correction then initially determines a duty cycle that is too high, in the next step a duty cycle that is too small, then again a duty cycle that is too high, etc., so that the duty cycle correction takes place with different polarity and is balanced overall.

On the basis of the respective ratio of the half-wave durations of the periodic signal, a control signal for correcting the duty cycle of the periodic signal can be generated, with the control signal incrementing, decrementing or unchanged the counter value of a correction counter for correcting the duty cycle of the periodic signal, depending on the respective ratio of the half-wave durations. If the control signal has a step size that corresponds to a smallest bit (Least Significant Bit), the alternating duty cycle correction in the case of a periodic signal of variable frequency is negligible overall for the control of a motor.

• - den Kondensator in einen Ausgangszustand zu bringen, in dem der Kondensator geladen ist,
• - den Kondensator während der Halbwellendauer der Halbwelle ausgehend von dem Ausgangszustand zu entladen und
• - anhand des Ladezustands des Kondensators am Ende der Halbwelle einen Kennwert für die Halbwellendauer der Halbwelle zur Korrektur des Tastverhältnisses bereitzustellen.

The object is also achieved by a device for regulating the pulse duty factor of at least one periodic signal, with at least one circuit arrangement for correcting the pulse duty factor to a predetermined target value based on the ratio of the half-wave durations of two half-waves of the periodic signal. It is provided that the circuit arrangement has at least one capacitor for determining a characteristic value for the half-wave duration of a half-wave, the circuit arrangement being designed and provided,

• - to bring the capacitor into an initial state in which the capacitor is charged,
• - To discharge the capacitor during the half-wave duration of the half-wave starting from the initial state and
• - using the state of charge of the capacitor at the end of the half-wave to provide a characteristic value for the half-wave duration of the half-wave to correct the duty cycle.

The device is particularly suitable and designed for carrying out the method described above and, by utilizing the discharge characteristic of a capacitor, enables a duty cycle correction even at high frequencies with sufficient sensitivity and accuracy.

The device has two circuit arrangements, each with a capacitor for determining a characteristic value for the half-wave duration of two different half-waves of the periodic signal. The half-wave duration of a first half-wave is then deduced from the state of charge of the first capacitor and the half-wave duration of a second half-cycle is concluded from the state of charge of the second capacitor. The charge states of the capacitors of the two circuit arrangements can be compared by means of at least one comparator in order to determine an actuating signal for correcting the pulse duty factor from the output values of the at least one comparator by at least one evaluation logic.

• 1 eine grafische Darstellung eines periodischen Signals;
• 2 eine schematische Darstellung einer Vorrichtung zur Regelung des Tastverhältnisses eines periodischen Signals unter Verwendung zweier Zähler;
• 3 eine grafische Darstellung eines Rechtecksignals und korrespondierender Zählerwerte der Zähler der Vorrichtung gemäß 2;
• 4 eine grafische Darstellung der Zählerwerte der Zähler als Funktion der Zeit beim Heraufzählen;
• 5 eine schematische Darstellung einer Ausführungsform einer Vorrichtung zur Regelung des Tastverhältnisses eines periodischen Signals unter Verwendung von Schaltungsanordnungen mit jeweils einem Kondensator;
• 6 eine grafische Darstellung eines Rechtecksignals und der Spannungssignale der Kondensatoren als Funktion der Zeit;
• 7 eine grafische Darstellung der Spannungssignale der Kondensatoren beim Entladen;
• 8 eine grafische Darstellung eines Stellsignals als Funktion der Differenz der Spannungssignale der Kondensatoren der Vorrichtung gemäß 5;
• 9A eine grafische Darstellung eines Rechtecksignals als Funktion der Zeit und von zugeordneten Korrekturintervallen, in denen die Korrektur des Tastverhältnisses vorgenommen wird, und
• 9B eine grafische Darstellung eines Rechtecksignals als Funktion der Zeit und von zugeordneten Korrekturintervallen für eine modifizierte Korrektur des Tastverhältnisses.

The idea on which the invention is based will be explained in more detail below with reference to the exemplary embodiments shown in the figures. Show it:

• 1 a graphical representation of a periodic signal;
• 2 a schematic representation of a device for regulating the duty cycle of a periodic signal using two counters;
• 3 a graphical representation of a square wave signal and corresponding counter values of the counters of the device according to FIG 2 ;
• 4th a graphical representation of the counter values of the counters as a function of time when counting up;
• 5 a schematic representation of an embodiment of a device for regulating the duty cycle of a periodic signal using circuit arrangements, each with a capacitor;
• 6th a graphical representation of a square wave signal and the voltage signals of the capacitors as a function of time;
• 7th a graphic representation of the voltage signals of the capacitors during discharge;
• 8th a graphical representation of a control signal as a function of the difference between the voltage signals of the capacitors of the device according to FIG 5 ;
• 9A a graphical representation of a square-wave signal as a function of time and of assigned correction intervals in which the correction of the duty cycle is carried out, and
• 9B a graphical representation of a square wave signal as a function of time and associated correction intervals for a modified correction of the duty cycle.

When regulating the speed of motorized drives, for example actuators for machine tools, speed control usually takes place in that means for generating a periodic signal in the form of a sinusoidal signal are provided on a moving part, for example a rotating motor axis, on the basis of which the speed and position are provided of the moving part is detected. For example, one or more magnets can be arranged on a motor axis, which interact with two Hall sensors that are offset from one another by 90 ° in the circumferential direction of the motor axis to generate two sinusoidal signals phase-shifted by 90 °. The position, speed and direction of rotation of the motor axis can then be determined from these sinusoidal signals.

In order to be able to record the speed and position of a moving part exactly, it is necessary to correct errors in the periodic signals generated. This is necessary because the generated periodic signals can have errors in their DC component (offset), their amplitudes and their phase angle. In addition, the periodic signal can be distorted, so that although the signal is periodic, its shape differs from a pure sinusoidal shape.

An example of a periodic signal V_0 a tension V as a function of time t is in 1 shown. The periodic signal V_0 has positive half-waves HW1 , HW3 and negative half waves HW2 , HW4 with different amplitudes A1 , A2 and can be used as the output signal of a sensor to determine the position and speed of a moving part, for example a motorized drive.

The periodic signal V_0 according to 1 differs greatly in shape from a pure sinusoidal shape. With a conventional correction method, the signal is V_0 for example to adjust the amplitudes A1 , A2 detected and corrected at its maximum and minimum points by adding the offset of the signal V_0 is adjusted. A corrected signal results V_0k , its amplitudes A1k , A2k are the same.

This in 1 periodic signal shown V_0 has a duty cycle of 1: 1, determined by the ratio of the half-wave duration t1 , t3 of the positive half-waves HW1 , HW3 to the main wave duration t2 , t4 of the negative half-waves HW2 , HW4 . This corresponds to the duty cycle of an ideal sinusoidal signal. The corrected signal V_0k however, its amplitudes A1k , A2k are matched to one another, differs greatly in its duty cycle, due to the fact that the zero crossings are shifted due to the adaptation of the DC component and the half-wave duration of the positive half-waves of the corrected signal V_0k and the half-wave duration of the negative half-waves of the corrected signal V_0k are enlarged.

By correcting by adjusting the amplitudes A1 , A2 of the signal V_0 is thus in accordance with the example 1 an error in the duty cycle has been generated. Is based on the corrected signal V_0k If the speed and position of a moving part are determined, larger errors may arise than when determining the speed and position from the uncorrected signal V_0 result. Is z. B. in the corrected signal V_0k according to 1 a speed determination based on the distances between the zero crossings of the corrected signal V_0k is carried out, positive and negative errors are recorded alternately and the speed is readjusted accordingly in an oscillating manner. This can lead to a whistling noise in the motor.

To correct a periodic signal V_0 for the purpose of determining the speed and position of a moving part, for example, the pulse duty factor of the periodic signal is therefore advantageously used V_0 regulated to a predetermined target value, for example a value of 1: 1.

An embodiment of a device for regulating the duty cycle of at least one periodic signal V_0 is in 2 shown. The periodic signal V_0 is an input signal at an amplifier 1 on and is used by the amplifier 1 to an amplified signal V_A changed. The amplified signal V_A is at the negative input of a comparator 2 on and is made by means of the comparator 2 with a reference voltage V_REF compared. The comparator 2 generated depending on the instantaneous value of the signal V_A a square wave signal V_R , that of a control logic 3 is supplied and its half-wave durations are those of the periodic signal V_0 correspond.

The control logic 3 is used to control two counters 41 , 42 and generated for this on the basis of the square-wave signal V_R Start signals Start1 , Start2 , Stop signals Stop1 , Stop2 and reset signals Reset 1 , Reset2 as well as a comparison signal comp and a clock signal CLK_b . By means of the start signals Start1 , Start2 can be a counting process of the counter 41 , 42 started while the stop signals Stop1 , Stop2 conversely, they are used to end a counting process that has been started. With the reset signals Reset 1 , Reset2 can be the respective value of the counter 41 , 42 reset.

About the comparison signal comp controls the control logic 3 a comparison logic 5 by the counters 41 , 42 generated counter values Z1 , Z2 compares and depending on the counter values Z1 , Z2 Control signals up , down for incrementing or decrementing a correction counter 6th generated.

Depending on the one through the control logic 3 provided clock signal CLK b gives the correction counter 6th a counter value Z to a digital-to-analog converter 7th from showing the counter value Z into an offset voltage to adjust the DC component of the signal V_A converts this offset voltage to the positive input of the amplifier 1 for superimposition with the periodic signal V_0 feeds.

The counters Z1 , Z2 generate depending on one by an oscillator 43 provided clock signal CLK_a the counter values Z1 , Z2 , by means of which the half-wave duration of two half-waves of the periodic signal V_0 generated square wave signal V_R is captured. Exemplary courses of the counter values Z1 , Z2 are in 3 shown.

The counters 41 , 42 are controlled by the control logic 3 controlled. The control logic 3 generates the start signals Start1 , Start2 to start the counters 41 , 42 and the stop signals Stop1 , Stop2 to stop the counters 41 , 42 based on the rising and falling edges of the square wave signal V_R . About the half-wave durations t1-t6 different half waves HW1-HW6 to record and to set them in relation to one another to determine the duty cycle is first of all, as in 3 is shown, the counter value Z1 reset and on the falling edge of the positive half-wave HW1 of the square wave signal V_R the start signal Start1 to start the counter 41 generated. The counter 41 thus begins its counting process, with the counter value Z1 incrementally depending on the clock signal CLK_a is increased, which specifies a clock whose frequency is many times greater than the frequency of the square wave signal V_R is.

During the half-wave period t2 the negative half-wave HW2 of the square wave signal V_R the counter counts 41 up. At the end of the negative half-wave HW2 generates the control logic 3 synchronous with the rising edge of the positive half-wave HW3 a stop signal Stop1 and thus stops the counter 41 .

During the following positive half-wave HW3 is now the counter value Z1 of the counter 41 with the previously determined, stored counter value Z2 of the counter 42 , which reflects the half-wave duration of a previous positive half-wave, compared and a difference Double room the counter values Z1 , Z2 determined.

At the end of the positive half-wave HW3 generates the control logic 3 the reset signal Reset2 and thus sets the counter 42 back to a starting value. On the following rising edge of the positive half-wave HW5 generates the control logic 3 the start signal Start2 to start the counter 42 , which then occurs during the positive half-wave HW5 incrementally counts up depending on the clock signal CLK a. At the end of the positive half-wave HW5 becomes the stop signal Stop2 to stop the counter 42 generated, and during the following negative half-wave HW6 becomes the generated counter value Z2 of the counter 42 again with the one in the counter 41 stored counter value Z1 compared.

The process continues, alternating the half-wave duration t1 , t3 , t5 a positive half-wave HW1 , HW3 , HW5 and the half-wave duration t2 , t4 , t6 a negative half-wave HW2 , HW4 , HW6 determined and compared with one another for continuous correction of the duty cycle.

The comparison logic 5 according to the device 2 carries out the comparison of the counter values Z1 , Z2 the counter 41 , 42 through and forms the difference Double room the counter values Z1 , Z2 . Depending on the difference Double room forms the comparison logic 5 a control signal up , down , which can have the value +1 (up) or -1 (down) or the value 0. By means of the control signal up , down increases or decreases the comparison logic 5 the counter value Z of the correction counter 6th or, if the value is 0, leaves the counter value Z unchanged. The counter value Z is made by means of the digital-to-analog converter 7th converted into an offset voltage and the periodic signal to correct the duty cycle V_0 superimposed.

The correction of the duty cycle takes place repeatedly and continuously while the periodic signal V_0 on the amplifier 1 is present. By repeatedly determining the difference Double room showing the inequality of the half-wave durations t1-t6 of half waves HW1-HW6 of the periodic signal V_0 reflects the counter value Z and thus the periodic signal V_0 Superimposed offset voltage is successively adjusted until the pulse duty factor of the periodic signal V_0 corresponds to the desired setpoint, for example 1: 1.

Using the in 2 The device shown schematically can determine the duty cycle of a periodic signal V_0 can be corrected to a predetermined target value, for example a ratio of 1: 1. In the device according to 2 the correction is carried out by recording the half-wave durations t1-t6 different half waves HW1-HW6 of the periodic signal V_0 via the linear counters 41 , 42 whose characteristic curve when enumerated in 4th is illustrated schematically.

The linear enumeration has the effect of correcting the duty cycle of the periodic signal V_0 at different frequencies of the periodic signal V_0 takes place with a different sensitivity. This is due to the fact that in the event of an incorrect pulse duty factor, the differences between the half-wave durations that occur t1-t6 decrease with increasing frequency and thus the difference Double room the counter values Z1 , Z2 the counter 41 , 42 at a large frequency of the periodic signal V_0 a small and at a low frequency of the periodic signal V_0 assumes a large value even though the underlying defective duty cycle is actually identical. In 4th is this by the difference DZL resulting from the counter values Z1L , Z2L at a low frequency of the periodic signal V_0 results, and the difference DZH resulting from the counter values Z1H , Z2H at a large frequency of the periodic signal V_0 results shown. Although the underlying defective duty cycle is the same (e.g. 1.2: 1), the differences are different DZL , DZH considerably.

It is also shown in 4th a maximum counter value Zmax , which is the maximum count of the counter 41 , 42 indicates. The maximum counter value Zmax leads to an overflow of the counter 41 , 42 and only occurs with very long half-wave periods t1-t6 of half waves HW1-HW6 of the periodic signal V_0 on, i.e. at low frequencies of the periodic signal V_0 , for which a correction of the duty cycle is not necessary.

Another embodiment of a device for regulating the duty cycle of at least one periodic signal is shown in FIG 5 shown. in the Difference from the embodiment according to 2 uses the embodiment according to 5 instead of the counter 41 , 42 two circuit arrangements 81 , 82 each one with switches 810 , 811 respectively. 820 , 821 wired capacitor 812 respectively. 822 exhibit. The switches 810 , 811 , 820 , 821 are controlled by a control logic 3 controlled, depending on one of the control logic 3 supplied square wave signal V_R Switching signals S1 , S2 , S3 , S4 generated.

Analogous to the embodiment according to 2 there is a periodic signal to be corrected V_0 as an input signal to an amplifier 1 on and is used by the amplifier 1 into an amplified signal V_A converted from which a comparator 2 by comparison with a reference voltage V_REF a square wave signal V_R generated. The square wave V_R becomes the control logic 3 fed in as a function of the square wave signal V_R the switching signals S1 , S2 , S3 , S4 to control the circuit arrangement 81 , 82 and clock signals CLK_a , CLK_b for controlling an evaluation logic 5 ' and a correction counter 6th generated. The correction counter 6th generates a counter value Z , which is a digital-to-analog converter 7th is supplied and converted by this into an analog offset voltage that is applied to the amplifier 1 the periodic signal V_0 is superimposed.

The device according to 5 uses to correct the duty cycle of the periodic signal V_0 the discharge behavior of two capacitors 812 , 822 the circuit arrangements 81 , 82 the end. By means of the discharge behavior of the capacitors 812 , 822 characteristic values are generated which correspond to the half-wave durations of different half-waves of the periodic signal V_0 correspond and based on which the duty cycle of the signal V_A is corrected.

An exemplary course of voltage signals V1 , V2 , the state of charge of the capacitors 812 , 822 correspond to the outputs of the circuit arrangements 81 , 82 is in 6th shown. The charging and discharging of the capacitors 812 , 822 is about the switching status of the switch 810 , 811 , 820 , 821 by means of the control logic 3 controlled.

At the beginning of a first positive half-wave HW1 closes the control logic 3 via the switching signal S1 the switch 810 and opens at the same time via the switching signal S2 the switch 811 . To the capacitor 812 with a capacity C1 thereby becomes the output voltage V_Start plus that with mass Gnd connected reference voltage V_REF applied, and the capacitor 812 is charged to an initial state.

On the following edge at the end of the half-wave HW1 opens the control logic 3 via the switching signal S1 the switch 810 and closes at the same time via the switching signal S2 the switch 811 . The condenser 812 will thus with a resistance 80 with the resistance value R. connected and forms together with the resistance 80 an RC element through which the capacitor 812 is discharged.

At the end of the negative half-wave HW2 opens the control logic 3 synchronous with the rising edge of the following positive half-wave HW3 the switch 811 so that the discharge of the capacitor 812 interrupted and the state of charge of the capacitor 812 at the end of the half-wave HW2 is saved. Now at the output of the circuit arrangement 81 applied voltage signal V1 becomes two comparators 83 , 84 fed that the voltage signal V1 with a voltage signal V2 , which shows the previously stored state of charge of the capacitor 822 indicates, compare.

The output values of the comparators 83 , 84 are the evaluation logic 5 ' supplied, which a control signal as a function of these output values up , down for setting the correction counter 6th generated. The comparators have during the half-wave HW3 Time to settle in. With the next edge, the falling edge of the half-wave HW3 , the output values from the evaluation logic 5 ' accepted, the counter value with the following edge Z of the correction counter 6th increased, decreased or left unchanged by one bit.

The charging and discharging of the capacitor 822 the circuit arrangement 82 takes place in the same way and is used to record the half-wave duration t1 , t3 , t5 a positive half-wave HW1 , HW3 , HW5 of the periodic signal V_0 . As in 6th is shown, the capacitor 822 by closing the switch 820 and opening the switch 821 by applying the voltages V Start plus V_REF charged to an initial state and during the positive half-wave HW5 unload. During the following half-wave HW6 are then the voltage signals V1 , V2 about the comparators 83 , 84 compared with each other and in the evaluation logic 5 ' evaluated.

The comparators 83 , 84 compare the voltage signals V1 , V2 at the outputs of the circuit arrangements 81 , 82 and thus detect a difference DV of the voltage signals V1 , V2 . To the positive input of the comparator 84 becomes the voltage signal V1 applied and with the one applied to the negative input to a relevance threshold V_A2 increased voltage signal V2 compared. At the positive input of the comparator 83 however, the voltage signal is V2 and is compared with the one applied to the negative input to a relevance threshold V_A1 increased Voltage signal V1 compared. The comparators generate depending on the comparison of the signals present 83 , 84 output values 0 or 1 in the evaluation logic 5 ' be evaluated.

Depending on the difference DV of the voltage signals V1 , V2 generate the comparators 83 , 84 different combinations of output values. Is the difference DV (according to the difference between the voltage signals to be compared V2-V1 of the discharged capacitors 812 , 822 ) greater than the relevance threshold V_A1 so gives the comparator 83 eg the initial value 1 and the comparator 84 the output value 0. Is the difference DV smaller than the relevance threshold V_A1 , but greater than the negative relevance threshold - V_A2 so both have comparators 83 , 84 eg the output value 0. Is the difference DV smaller than the negative relevance threshold - V_A2 so indicates the comparator 83 eg the output value 0 and the comparator 84 the initial value 1 on.

Depending on the output values of the comparators 83 , 84 generates the evaluation logic 5 ' the control signals up , down to increment, decrement or leave the counter value Z of the correction counter 6th . This is schematically in 8th shown. Is the difference DV above the upper relevance threshold V_A1 , so the evaluation logic increments 5 ' the correction counter 6th up by one bit (+1). Is the difference DV between the negative relevance threshold - V_A2 and the positive relevance threshold V_A1 , so leaves the evaluation logic 5 ' the correction counter 6th unchanged. And is the difference DV smaller than the negative relevance threshold - V_A2 , so the evaluation logic decrements 5 ' the correction counter 6th down one bit (-1).

The positive relevance threshold V_A1 and the negative relevance threshold - V_A2 are advantageously chosen to be the same in terms of their magnitude and serve to avoid a duty cycle correction in the event of minor errors in the duty cycle.

The device according to 5 uses the discharge behavior of the capacitors 812 , 822 for recording the half-wave durations t1-t6 of half waves HW1-HW6 of the periodic signal V_0 the end. The capacitors 812 , 822 have an exponential discharge behavior, the time constant of which is given by the product of the capacitance values C1 , C2 with the resistance value R. is determined. The capacitors 812 , 822 advantageously have an identical capacitance C = C1 = C2, so that the capacitors 812 , 822 discharged with the same time constant RC = RC1 = RC2.

The exponential discharge behavior of the capacitors 812 , 822 is schematic in the form of that on the capacitors 812 , 822 occurring voltage signals V1 , V2 in 7th shown. It is characteristic here that the capacitors 812 , 822 initially discharge quickly, due to the exponential behavior the discharge speed increases over time t however slowed down. This has the consequence that with short discharge times - as is the case with a periodic signal V_0 high frequency with small half-wave durations t1-t6 occur - a small difference DtH in the discharge times to a large difference DVH in the voltage signals V1 , V2 leads. In the case of long discharge times, on the other hand, there is a comparatively larger difference DtM in the discharge times to a comparable difference DVM of the voltage signals V1 , V2 .

Due to the exponential discharge behavior of the capacitors 812 , 822 What is achieved is that the sensitivity in the correction of the duty cycle is approximately constant over a comparatively large frequency range and especially at high frequencies compared to the duty cycle correction by means of a linear counter (see 2 ) is increased. The differences DVH and DVM in the voltage signals V1 , V2 according to 7th are approximately equal in magnitude and correspond to an equal duty cycle of the half-waves HW1-HW6 of the periodic signal V_0 at different frequencies.

In 7th is a threshold V_thr which is a limit for the voltage signals V1 , V2 below which no correction of the duty cycle should take place. Fall below the voltage signals V1 , V2 due to a long discharge time at low frequencies of the periodic signal V_0 the threshold V_thr , so takes the evaluation logic 5 ' no adjustment of the correction counter 6th before.

The embodiments of the devices according to 2 and 5 enable the duty cycle of at least one periodic signal to be corrected V_0 for example in the context of determining the speed and position of a moving part of an actuator or the like. Compared to the embodiment according to 2 has the embodiment according to 5 by using the capacitors 812 , 822 for recording the half-wave durations t1-t6 of half waves HW1-HW6 of the periodic signal V_0 has the advantage that a largely constant sensitivity when correcting the duty cycle is achieved over a large frequency range.

The duty cycle is conventionally corrected by adding a characteristic value for the duty cycle as a ratio of the half-wave durations t1 , t2 , t3 , t4 , ... a positive half-wave HW1 , HW3 , ... to a negative half-wave HW2 , HW4 , ... or vice versa a negative half-wave HW2 , HW4 , ... to a positive half-wave HW1 , HW3 , ... is recorded and the duty cycle is then corrected to a specified target value using this characteristic value. The correction based on such a fixed ratio (positive to negative or negative to positive) is unproblematic if the periodic signal to be corrected V_0 has a constant frequency, since in this case it is always correctly recognized whether the half-wave duration t1 , t2 , ... a half-wave HW1 , HW2 , ... shorter or longer than the half-wave duration t1 , t2 , ... another half-wave HW1 , HW2 , ... and the duty cycle is therefore incorrect.

Detects the periodic signal V_0 however, for example as a result of the acceleration or braking of a moving part of a motor to be detected, the duty cycle correction leads to problems if the duty cycle correction is fixed on the basis of the ratio of the half-wave durations t1 , t2 , ... the positive to the negative half-waves HW1 , HW2 , ... or the negative to the positive half-waves HW1 , HW2 , ... is determined.

This is exemplified in 9A illustrated in which a square wave signal V_R an accelerated periodic signal V_0 with increasing frequency and ever shorter half-waves HW1-HW8 is shown. In the example according to 9A the duty cycle is always based on the ratio of the half-wave duration t1 , t3 , t5 , t7 a positive half-wave HW1 , HW3 , HW5 , HW7 for half-wave duration t2 , t4 , t6 , t8 a negative half-wave HW2 , HW4 , HW6 , HW8 certainly. This results in correction intervals 11, 12, 13, 14, in each of which the ratio of the half-wave durations t1-t8 is recorded and in which the half-wave duration t1 , t3 , t5 , t7 the positive half-wave HW1 , HW3 , HW5 , HW7 each greater than the half-wave duration t2 , t4 , t6 , t8 the negative half-wave HW2 , HW4 , HW6 , HW8 is. This leads to an error in the pulse duty factor of the same polarity being determined in the context of the duty cycle correction, since the half-wave duration t1 , t3 , t5 , t7 the positive half-wave HW1 , HW3 , HW5 , HW7 always greater than the half-wave duration t2 , t4 , t6 , t8 the subsequent negative half-wave HW2 , HW4 , HW6 , HW8 is. The correction counter is therefore used for correction 6th (please refer 2 or 5 ) always changed in the same direction, so its value Z runs away.

As a result of the ever shorter half-wave durations t1-t8 due to the change in frequency of the periodic signal V_0 , this leads to an incorrect correction of the duty cycle.

To with a frequency change of the periodic signal V_0 to avoid an incorrect correction of the duty cycle, in the example according to 9B the correction of the duty cycle is not fixed based on the ratio of the positive to the negative half-wave duration t1-t8 made, but alternately.

First, in the example according to 9B in a correction interval I1 the duty cycle of a positive half-wave HW1 to a negative half-wave HW2 recorded. This results, due to the fact that the half-wave duration t1 the positive half-wave HW1 greater than the half-wave duration t2 the negative half-wave HW2 is to correct the duty cycle in one direction, for example by incrementing the counter value Z of the correction counter 6th (please refer 2 or 5 ).

In a second correction interval I2 now becomes the ratio of the half-wave duration t2 the negative half-wave HW2 for half-wave duration t3 of the following positive half-wave HW3 recorded, and due to the fact that the negative half-wave duration t2 greater than the positive half-wave duration t3 is the counter value Z of the correction counter 6th corrected in the opposite direction compared to the first correction interval I1 and thus compensated for the first correction.

The correction of the pulse duty factor now takes place alternately in the correction intervals I3-I7 , where the counter value Z of the correction counter 6th corrected in different directions in each case and therefore no adjustment of the pulse duty factor is made overall. By means of the alternating correction of the duty cycle by alternately referencing the positive half-wave HW1 , HW3 , HW5 , HW7 to the negative half-wave HW2 , HW4 , HW6 , HW8 and vice versa the negative half-wave HW2 , HW4 , HW6 , HW8 to the positive half-wave HW1 , HW3 , HW5 , HW7 is thus an incorrect correction of the duty cycle as a result of a frequency change of the periodic signal V_0 avoided.

Used as the maximum correction increment when adjusting the correction counter 6th If the least significant bit is used, the effect of the correction on the control of a motor is negligible overall.

The based 9B Correction made to the duty cycle, especially in the case of variable frequency periodic signals V_0 can advantageously in connection with both the device according to 2 as well as with the device according to 5 can be used.

The idea on which the invention is based is not restricted to the exemplary embodiments described above. In particular, other circuit arrangements for correcting the pulse duty factor of at least one periodic signal using a capacitor can be used, which advantageously correct the pulse duty factor of two periodic signals that are 90 ° out of phase signals on a motor for determining the speed and position of a rotating part be generated.

List of reference symbols

1

amplifier

2

Comparator

3

Control logic

41, 42

counter

43

oscillator

5

Comparison logic

5 '

Evaluation logic

6th

Correction counter

7th

Digital-to-analog converter

80

resistance

81, 82

Circuit arrangement

810, 811, 820, 821

counter

812,822

capacitor

83.84

Comparator

A1, A2

amplitude

A1k, A2k

Corrected amplitude

C1, C2

capacity

CLK_a, CLK_b

Clock signal

comp

Comparison signal

DtH, DtM

difference

DV, DVH, DVM

difference

DZ, DZH, DZL

difference

Gnd

Dimensions

HW1-HW8

Half wave

11-17

Correction interval

R.

Resistance value

Reset1, Reset2

Reset signal

Start1, Start2

Start signal

Stop1, Stop2

Stop signal

S1, S2, S3, S4

Switching signal

t

Time

t1-t8

Half-wave duration

up, down

Control signal

V

tension

V_0

Input signal

V_0k

Corrected input signal

V_A

amplified signal

V_A1, V_A2

Relevance threshold

V_R

Square wave signal

V_REF

Reference voltage

V_START

Output voltage

V_thr

Threshold

V1, V2

Voltage signal

Z

Counter value

Z1, Z2

Counter value

Z1L, Z2L

Counter value at low frequency

Z1H, Z2H

Counter value at high frequency

Zmax

Maximum counter value

Claims (14)

Method for regulating the pulse duty factor of at least one periodic signal, in which the pulse duty factor is corrected to a predetermined target value based on the ratio of the half-wave durations (t1-t8) of two half-waves (HW1-HW8) of the periodic signal (V_0), whereby to determine a characteristic value for the half-wave duration (t1-t8) of a half-wave (HW1-HW8) to correct the duty cycle - a capacitor (812, 822) is brought into an initial state in which the capacitor (812, 822) is charged, - the capacitor (812, 822) is discharged during the half-wave duration (t1-t8) of the half-wave (HW1-HW8) starting from the initial state and - based on the state of charge of the capacitor (812, 822) at the end of the half-wave (HW1-HW8), which is a characteristic value for the Half-wave duration (t1-t8) of the half-wave (HW1-HW8), the duty cycle is corrected, characterized in that a first capacitor (812) during the half-wave duration (t1, t3 , t5, t7) of a first half-wave (HW1, HW3, HW5, HW7) and a second capacitor (822) during the half-wave duration (t2, t4, t6, t8) of a second, from the first half-wave (HW1, HW3, HW5, HW7) different half-wave (HW2, HW4, HW6, HW8) is discharged, the state of charge of the first Capacitor (812) at the end of the first half-cycle (HW1, HW3, HW5, HW7) a characteristic value for the half-cycle duration (t1, t3, t5, t7) of the first half-cycle (HW1, HW3, HW5, HW7) and the state of charge of the second capacitor (822) at the end of the second half-wave (HW2, HW4, HW6, HW8) represents a characteristic value for the half-wave duration (t2, t4, t6, t8) of the second half-wave (HW2, HW4, HW6, HW8) and based on the difference (DV ) the charge states of the two capacitors (812, 822) the duty cycle is corrected. Procedure according to Claim 1 , characterized in that a control signal (up, down) for correcting the duty cycle is generated on the basis of the difference (DV) of the charge states of the capacitors (812, 822). Procedure according to Claim 2 , characterized in that the charging states of the capacitors (812, 822) are compared with one another via at least one comparator (83, 84), the control signal (up, down) the counter value ( Z) a correction counter (6) for correcting the duty cycle is incremented, decremented or left unchanged. Procedure according to Claim 2 or 3 , characterized in that the states of charge of the capacitors (812, 822) are compared with one another via two comparators (83, 84), the control signal (up, down) determining the counter value (Z) based on the output values of the two comparators (83, 84) a correction counter (6) - incremented when the difference (DV) of the states of charge of the capacitors (81, 82) exceeds a positive relevance threshold (V_A1), - decrements when the difference (DV) of the states of charge of the capacitors (81, 82) a falls below negative relevance threshold (V_A2) - leaves unchanged if the difference (DV) of the charge states of the capacitors (81, 82) is between the positive relevance threshold (V_A1) and the negative relevance threshold (V_A2). Method according to one of the preceding claims, characterized in that a square-wave signal (V_R) is formed from the periodic signal (V_0) representing an input signal and the pulse duty factor is corrected on the basis of the square-wave signal (V_R). Method according to one of the preceding claims, characterized in that the capacitor (812, 822) is connected to switches (810, 811, 820, 821) whose switching states for charging and discharging the capacitor (812, 822) via a control logic (3 ) being controlled. Procedure according to Claim 6 , characterized in that the capacitor (812, 822) for charging is connected to an output voltage (V_START) via a first switch (810, 820). Procedure according to Claim 6 or 7th , characterized in that the capacitor (812, 822) is connected to a resistor (80) for discharging via a second switch (811, 821) and discharged via the resistor (80). Method according to one of the preceding claims, characterized in that the duty cycle is alternately based on the ratio of the half-wave duration (t1, t3, t5, t7) of a positive half-wave (HW1, HW3, HW5, HW7) to the half-wave duration (t2, t4, t6, t8 ) a following negative half-wave (HW2, HW4, HW6, HW8) and the ratio of the half-wave duration (t2, t4, t6, t8) of a negative half-wave (HW2, HW4, HW6, HW8) to the half-wave duration (t1, t3, t5, t7 ) a following positive half-wave (HW1, HW3, HW5, HW7) is corrected. Procedure according to Claim 9 , characterized in that based on the respective ratio of the half-wave durations (t1-t8) a control signal (up, down) for correcting the duty cycle of the periodic signal (V_0) is generated, depending on the respective ratio of the half-wave durations (t1-t8) Control signal (up, down) the counter value (Z) of a correction counter (6) for correcting the duty cycle of the periodic signal (V_0) incremented, decremented or unchanged. Procedure according to Claim 10 , characterized in that the control signal (up, down) has a step size corresponding to a least significant bit. Device for regulating the pulse duty factor of at least one periodic signal, with at least one circuit arrangement (81, 82) for correcting the pulse duty factor to a predetermined target value based on the ratio of the half-wave durations (t1-t8) of two half-waves (HW1-HW8) of the periodic signal (V_0) , the circuit arrangement (81, 82) having at least one capacitor (812, 822) for determining a characteristic value for the half-wave duration (t1-t8) of a half-wave (HW1-HW8), the circuit arrangement (81, 82) being designed and provided - to bring the capacitor (812, 822) into an initial state in which the capacitor (812, 822) is charged, - the capacitor (812, 822) during the half-wave duration (t1-t8) of the half-wave (HW1-HW8) starting from the initial state to discharge and - based on the state of charge of the capacitor (812, 822) at the end of the half-wave (HW1-HW8) a characteristic value for the half-wave duration (t1-t8) of the Half-wave (HW1-HW8) for correcting the duty cycle, characterized by two circuit arrangements (81, 82) each with a capacitor (812, 822) for determining a characteristic value for the half-wave duration (t1-t8) of two different half-waves (HW1-HW8) of the periodic signal (V_0). Device according to Claim 12 , characterized by at least one comparator (83, 84) for comparing the charge states of the capacitors (812, 822) of the two circuit arrangements (81, 82). Device according to Claim 13 , characterized by at least one evaluation logic (5 ') for determining an actuating signal (up, down) for correcting the pulse duty factor from the output values of the at least one comparator (83, 84).

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