DE102008062452A1 - Method for controlling pulse-duty factor of periodic signal during regulation of speed and position of rotary motor shaft of engine of machine tool, involves correcting pulse-duty factor based on charging condition of capacitors - Google Patents

Abstract

The method involves correcting a pulse-duty factor to a predetermined reference value based on the ratio of half wave durations (t1-t4) of half waves (HW1-HW4) of a periodic signal (V-0). Two capacitors are brought to a starting condition and charged for determining a characteristic value for the half wave durations. The capacitors are uncharged during half wave durations of the half waves based on the starting condition. The factor is corrected based on the charging condition of the capacitors at an end of the half waves that represents a characteristic value for half wave duration. An independent claim is also included for a device for controlling a pulse-duty factor of a periodic signal, comprising two capacitors.

Description

The The invention relates to a method for controlling the duty cycle at least one periodic signal according to the preamble of claim 1 and a device for controlling the duty cycle.

at Such a method is based on the ratio the half-wave durations of two half-waves of a periodic signal corrected the duty cycle to a predetermined setpoint.

at The speed control of an engine is usually a rotational movement of a rotatable part of the engine (eg. the motor shaft) by detecting two mutually phase-shifted by 90 ° periodic sinusoidal signals determined. The sinusoidal signals can for example, by staggered, the movement of the moving part receiving sensors (eg, Hall sensors) are generated, respectively an approximately sinusoidal, with the rotational movement of the part Generate correlated signal. However, the generated signals in their amplitude, their phase and their DC component (offset) can be flawed and also distorted in their shape, the signals must be corrected to the speed and to be able to detect the position of the rotatable part exactly.

easy Correction methods, for example, resemble the amplitudes of a positive and one negative half cycle of the periodic signal to each other by the signal by adjusting the DC component (Offset) is shifted in total. The detection of signal errors takes place only selectively with a fixed clock or on fixed angular positions, so that when distorted, from a sinusoidal shape strongly deviating signals may be a wrong one Correction value is determined, which deteriorates the waveform rather and the accuracy in determining the speed and position of the rotatable part decreases.

Around an exact determination of the speed and position of the Rotatable part of the engine to ensure therefore, the generated periodic signals are regulated and corrected in this way, that their duty cycle corresponds to a predetermined desired value.

Under the duty ratio here is the ratio of temporal duration (half-wave duration) of two half-waves of the periodic To understand signals. At a duty cycle of 1: 1 Half-wave durations of half-waves of the periodic signal are identical and the zero crossings of the periodic signal the same distance.

At one of the DE 35 14 155 A1 known methods for controlling the duty cycle in a position measuring system, a periodic signal is controlled to a constant desired duty cycle by a variable gain amplifier generates a difference signal by comparing the predetermined target duty cycle with an instantaneous actual duty cycle, which is supplied to an actuating unit for forming a control signal , To correct the duty cycle, the control signal is then superimposed on the actual signal.

At one of the US 4,475,086 known methods, a counter is used which counts incrementally upwards during a first half-wave and incrementally down again during a subsequent second half-wave. The counter value at the end of the second half-wave indicates an index of the difference between the half-wave durations of the two half-waves, and the duty cycle is adjusted as a function of this characteristic.

conventional Method for determining and correcting the duty cycle insert a counter that represents a difference between the half-wave durations detected two half-waves, have a frequency dependence due to the fact that at high frequencies of the to be corrected periodic signal, the difference of the half-wave durations is low, although the duty cycle may be heavily dependent on the set Setpoint deviates. The usually linear using a fixed clock counter can be such a low Difference of half-wave durations not with sufficient accuracy capture, so the sensitivity of the duty cycle correction decreases with increasing frequency.

Of the The present invention is based on the object, a method and a device for controlling the duty cycle to create at least one periodic signal, one of the frequency of the periodic signal largely independent Duty cycle correction with sufficient sensitivity even at high frequencies.

These The object is achieved by a method having the features of the claim 1 solved.

• – ein Kondensator in einen Ausgangszustand gebracht wird, in dem der Kondensator geladen ist,
• – der Kondensator während der Halbwellendauer der Halbwelle ausgehend von dem Ausgangszustand entladen wird und
• – anhand des Ladezustands des Kondensators am Ende der Halbwelle, der einen Kennwert für die Halbwellendauer der Halbwelle darstellt, das Tastverhältnis korrigiert wird.

According to the invention, it is provided that for determining a characteristic value for the half-wave duration of a half-wave for correcting the duty cycle

• A capacitor is brought into an initial state in which the capacitor is charged,
• - The capacitor is discharged during the half-wave duration of the half-wave starting from the initial state and
• - Based on the state of charge of the capacitor at the end of the half-wave, a characteristic value for represents the half-wave duration of the half-wave, the duty cycle is corrected.

The The present invention is based on the idea, instead of a Counter for (linear) determination of the half-wave duration of a Half-wave to use a circuit arrangement with a capacitor and to exploit the characteristic of the discharging behavior of the capacitor, in particular for periodic signals of high frequency sufficient Accuracy in the duty cycle correction to achieve. The capacitor is used to determine a characteristic value for the half-wave duration of a half wave first by applying a voltage loaded in a defined initial state. During the Half-wave duration of the half-wave, the capacitor is then discharged and is at the end of the half wave in a state of charge, in the remaining charge is stored in the capacitor. This charge state depends on the half-wave duration, which dictates the time, during which the capacitor can discharge.

Around the accuracy in the duty cycle correction in particular to increase at high frequencies of the periodic signal, the (negative) exponential characteristic of the capacitor is used, the conditionally that the capacitor is to be detected during the Half-wave duration initially relatively quickly discharges, however, the discharge rate decreases with time. This results in, that for signals of high frequency (their half-waves a small half-wave duration have) a small time difference of the half-wave duration two half-waves to a big difference in the charge states at the end of the respective half wave leads.

in principle is possible, based on just a capacitor, a correction the duty cycle of a two half-waves having periodic signal. This can be done first over the capacitor is the characteristic value for the half-wave duration of the determined first half wave and by means of a so-called sample & hold member be cached. Subsequently, with the same Capacitor the parameter for the second half-wave duration determined and, if both characteristic values are available, corrected the duty cycle. Alternatively, it is also possible the charge states corresponding to the characteristic values of the capacitor at the end of the first half-wave and at the end of the second half-wave under Using an analog-to-digital converter to digitize each and digitally process.

Around to correct the duty cycle, are advantageous two capacitors are provided, one of which is a first capacitor a characteristic value for the half-wave duration of a first half-wave and a second capacitor a characteristic for the half-wave duration a second half-wave different from the first half-wave supplies. The two half waves represent a positive and a negative Half-wave of the periodic signal whose duty cycle, for example to be regulated to a value of 1: 1. As part of the duty cycle correction is during the half-wave duration of the first half of the first capacitor and during the half-wave duration of the second Half wave discharged the second capacitor. The state of charge of the first Capacitor at the end of the first half-wave gives a characteristic value for the half-wave duration of the first half-wave, while the State of charge of the second capacitor at the end of the second half cycle a characteristic value for the half-wave duration of the second half-wave supplies. The charge states of the capacitors at the end of the two Halfwaves are then stored in the capacitors, and based on the difference of the charge states of the two capacitors the duty cycle is corrected.

to Correction of the duty cycle can be based on the difference the charge states of the capacitors generates a control signal become. The charge states of the capacitors can be compared with each other via at least one comparator, being dependent on the output value of the at least one comparator the control signal the counter value of a correction counter incremented to correct the duty cycle, decremented or unchanged. Dependent on from the counter value of the correction counter becomes, for example the DC component (offset) of the periodic signal to be corrected adjusted, the correction being repeated until the duty cycle has reached the desired setpoint.

• – inkrementiert, wenn die Differenz der Ladezustände der Kondensatoren eine positive Relevanzschwelle überschreitet,
• – dekrementiert, wenn die Differenz der Ladezustände der Kondensatoren eine negative Relevanzschwelle unterschreitet,
• – unverändert lässt, wenn die Differenz der Ladezustände der Kondensatoren zwischen der positiven Relevanzschwelle und der negativen Relevanzschwelle liegt.

Advantageously, the charge states of the capacitors are compared with each other via two parallel comparators, wherein based on the output values of the two comparators, the control signal the counter value of a correction counter

• Incremented when the difference in the charge states of the capacitors exceeds a positive relevance threshold,
• - decrements when the difference in the charge states of the capacitors falls below a negative relevance threshold,
• - Leaves unchanged if the difference between the states of charge of the capacitors lies between the positive relevance threshold and the negative relevance threshold.

For this purpose, for example, a voltage signal of the first capacitor (positive input of the first comparator) and a voltage signal of the second capacitor (negative input of the first comparator) increased by the negative relevance threshold can be applied to the first comparator On the other hand, the second comparator receives the voltage signal of the second capacitor (positive input of the second comparator) and the voltage signal of the first capacitor (negative input of the second comparator) increased by the positive relevance threshold.

to Correction of the duty cycle of the periodic signal a rectangular signal is preferably formed from the periodic signal and corrected by the square wave signal the duty cycle. Of the Capacitor can be connected in a circuit arrangement with switches be that control the charging and discharging of the capacitor and their switching states for charging and discharging the capacitor via a control logic be switched. The control logic determines from the square wave signal doing the flanks of the square wave signal and switches the switches using the flanks to charge the capacitor and a discharge process to start and finish.

For example The capacitor can be charged via a first switch be connected to an output voltage which is the capacitor into an initial state with a predetermined charge. To unload the first switch is opened, and the Capacitor is connected via a second switch with a Resistor connected so that the capacitor together with the resistor forms an RC element. About the resistor is the capacitor discharged, taking at the end of the half-wave - determined by the control logic based on the corresponding edge of the square wave signal - too the second switch is open and the charge state at the end the half-wave is thus stored in the capacitor.

at an advantageous method for correcting the duty cycle the duty cycle is alternately based on the ratio the half-wave duration of a positive half-wave to the half-wave duration a subsequent negative half wave and the ratio the half-wave duration of a negative half-wave to the half-wave duration a subsequent positive half wave corrected.

this the idea is based on a correction of the duty cycle not fixed by the ratio of a positive one to make a negative half-wave duration (or vice versa), but alternating. For example, in a first step first on the basis of the ratio of the half-wave duration a positive half-wave to the half-wave duration of a subsequent negative half-wave corrected the duty cycle. Subsequently vice versa, the duty cycle is based on the ratio the half-wave duration of a negative half-wave to the half-wave duration a subsequent positive half wave corrected. Subsequently becomes again a positive half wave to a negative, then a negative related to a positive half wave, etc.

The so performed alternating duty cycle correction has the effect that when a frequency change of corrective periodic signal - for example at a frequency increase due to an acceleration of a to be detected moving part of an engine - a correction in different Directions made and so a total erroneous duty cycle correction avoided due to a frequency-variable signal becomes.

For example become with a periodic signal with increasing frequency the half-wave durations of successive half waves are getting shorter and shorter. The alternating duty cycle correction then becomes first to the large duty cycle, too small a duty cycle in the next step, then again too large a duty cycle, etc. determined, so that the duty cycle correction with different Polarity occurs and balances overall.

Based the respective ratio of the half-wave durations of the periodic Signal can be a control signal to correct the duty cycle the periodic signal are generated, depending from the respective ratio of the half-wave durations the Control signal the counter value of a correction counter for correcting the duty cycle of the periodic signal incremented, decremented or unchanged. If the control signal has a step size, the smallest one Bit (Least Significant Bit) matches, so is the alternating one Duty cycle correction variable with a periodic signal Total frequency negligible for the control of an engine.

• – den Kondensator in einen Ausgangszustand zu bringen, in dem der Kondensator geladen ist,
• – den Kondensator während der Halbwellendauer der Halbwelle ausgehend von dem Ausgangszustand zu entladen und
• – anhand des Ladezustands des Kondensators am Ende der Halbwelle einen Kennwert für die Halbwellendauer der Halbwelle zur Korrektur des Tastverhältnisses bereitzustellen.

The object is also achieved by a device for controlling the duty cycle of at least one periodic signal, with at least one circuit arrangement for correcting the duty cycle to a predetermined desired value based on the ratio of half-wave durations of two half-waves of the periodic signal. It is provided that the circuit arrangement has at least one capacitor for determining a characteristic value for the half-wave duration of a half-wave, the circuit arrangement being designed and provided,

• To bring the capacitor into an initial state in which the capacitor is charged,
• - To discharge the capacitor during the half-wave duration of the half-wave, starting from the initial state and
• - Based on the state of charge of the capacitor at the end of the half-wave, a characteristic value for the Half-wave duration of the half-wave to provide for the correction of the duty cycle.

The Device is particularly suitable and designed for implementation of the method described above and enables by exploiting the discharge characteristic of a capacitor, a Duty cycle correction even at high frequencies with a sufficient sensitivity and accuracy.

advantageously, The device has two circuit arrangements, each with a Capacitor for determining a characteristic for the half-wave duration two different half-waves of the periodic signal. Based on the state of charge of the first capacitor is then on the Half-wave duration of a first half-wave and the state of charge of the second capacitor to the half-wave duration of a second half-wave closed. By means of at least one comparator can the charge states of the capacitors of the two circuit arrangements be compared by at least one evaluation logic of the Output values of the at least one comparator, a control signal to determine the correction of the duty cycle.

Of the The idea underlying the invention is based on the following the embodiments shown in the figures closer be explained. Show it:

1 a graphical representation of a periodic signal;

2 a schematic representation of an apparatus for controlling the duty cycle of a periodic signal using two counters;

3 a graphical representation of a square wave signal and corresponding counter values of the counter of the device according to 2 ;

4 a graphical representation of the counter values of the counters as a function of time when counting up;

5 a schematic representation of an embodiment of a device for controlling the duty cycle of a periodic signal using circuit arrangements each having a capacitor;

6 a graphical representation of a rectangular signal and the voltage signals of the capacitors as a function of time;

7 a graphical representation of the voltage signals of the capacitors during discharge;

8th a graphical representation of a control signal as a function of the difference of the voltage signals of the capacitors of the device according to 5 ;

9A a graphical representation of a square wave signal as a function of time and associated correction intervals in which the correction of the duty cycle is made, and

9B a graphical representation of a square wave signal as a function of time and associated correction intervals for a modified correction of the duty cycle.

at the speed control of motor drives, for example with actuators for machine tools, usually takes place a speed control characterized in that on a moving part, for example, a rotating motor axis, means for generating a periodic signal provided in the form of a sine signal be based on which the speed and position of the moving Part is recorded. For example, on a motor axis one or more magnets may be arranged with two bearing or on the housing side offset by 90 ° in the circumferential direction of the motor axis mutually arranged Hall sensors to generate two by 90 ° to each other phase-shifted sinusoidal signals interact. From these sinusoidal signals then the position, the speed and the direction of rotation the motor axis are determined.

Around accurately detect the speed and position of a moving part it is necessary to be able to make mistakes in the generated periodic Correct signals. This is necessary as the generated periodic signals error in their DC component (offset), their Amplitudes and their phase angle may have. moreover the periodic signal may be distorted so that the signal is periodic is, in its form but deviates from a pure sinusoidal form.

An example of a periodic signal V_0 of a voltage V as a function of time t is in 1 shown. The periodic signal V_0 has positive half waves HW1, HW3 and negative half waves HW2, HW4 with different amplitudes A1, A2 and can, as an output signal of a sensor, serve to determine the position and speed of a moving part, for example a motor drive.

The periodic signal V_0 according to 1 Its shape deviates greatly from a pure sinusoidal form. In a conventional correction method For example, to equalize the amplitudes A1, A2 at its maximum and minimum positions, the signal V_0 is detected and corrected by adjusting the DC component (offset) of the signal V_0. The result is a corrected signal V_0k whose amplitudes A1k, A2k are the same.

This in 1 illustrated periodic signal V_0 has a duty ratio of 1: 1, determined by the ratio of the half-wave duration t1, t3 of the positive half-waves HW1, HW3 to the main shaft duration t2, t4 of the negative half-waves HW2, HW4. This corresponds to the duty cycle of an ideal sine signal. The corrected signal V_0k, on the other hand, whose amplitudes A1k, A2k are matched to one another, differs greatly in its duty factor, due to the fact that the zero crossings are shifted by the adaptation of the DC component and the half-wave duration of the positive half-waves of the corrected signal V_0k is reduced and the half-wave duration of the negative Half-waves of the corrected signal V_0k are increased.

By the correction via the equalization of the amplitudes A1, A2 of the signal V_0 is thus in the example according to 1 an error has been generated in the duty cycle. If the velocity and position of a moving part are determined on the basis of the corrected signal V_0k, larger errors may possibly result than in the determination of the velocity and position from the uncorrected signal V_0. If z. B. in the corrected signal V_0k according to 1 a speed determination carried out due to the distances of the zero crossings of the corrected signal V_0k, so positive and negative errors are detected alternately, and the speed is readjusted accordingly oscillating. This can lead to a whistling sound in the engine.

to Correction of a periodic signal V_0 for the purpose of, for example the velocity and position of a moving part is therefore advantageously the duty cycle of the periodic Signals V_0 to a predetermined setpoint, such as a Value of 1: 1, regulated.

An embodiment of a device for regulating the duty cycle of at least one periodic signal V_0 is shown in FIG 2 shown. The periodic signal V_0 is present as an input signal to an amplifier 1 on and off of the amplifier 1 converted to an amplified signal V_A. The amplified signal V_A is at the negative input of a comparator 2 and is determined by means of the comparator 2 compared with a reference voltage V_REF. The comparator 2 generates in dependence on the instantaneous value of the signal V_A a square wave signal V_R, that of a control logic 3 is supplied and whose half-wave durations correspond to those of the periodic signal V_0.

The control logic 3 is used to control two counters 41 . 42 and generates for this purpose based on the square wave signal V_R start signals Start1, Start2, stop signals Stop1, Stop2 and reset signals Reset1, Reset2 and a comparison signal comp and a clock signal CLK_b. By means of the start signals Start1, Start2 can count the counter 41 . 42 while stop signals Stop1, Stop2 are reversed to terminate a started count. With the reset signals Reset1, Reset2 the respective value of the counter 41 . 42 be reset.

The control logic is controlled via the comparison signal comp 3 a comparison logic 5 that from the counters 41 . 42 generated counter values Z1, Z2 compares and in response to the counter values Z1, Z2 control signals up, down for incrementing or decrementing a correction counter 6 generated.

Depending on the control logic 3 provided clock signal CLK_b is the correction counter 6 a counter value Z to a digital-to-analog converter 7 from that converts the counter value Z into an offset voltage for adjusting the DC component of the signal V_A and this offset voltage to the positive input of the amplifier 1 for superposition with the periodic signal V_0 supplies.

The counters Z1, Z2 generate in response to a by an oscillator 43 provided clock signal CLK_a the counter values Z1, Z2, by means of which the half-wave duration of two half-waves of the generated from the periodic signal V_0 square wave signal V_R is detected. Exemplary curves of the counter values Z1, Z2 are in 3 shown.

The counters 41 . 42 be through the control logic 3 controlled. The control logic 3 generates the start signals Start1, Start2 to start the counters 41 . 42 and the stop signals Stop1, Stop2 for stopping the counters 41 . 42 based on the rising and falling edges of the square wave signal V_R. In order to detect the half-wave durations t1-t6 of different half-waves HW1-HW6 and to relate them to each other for determining the duty cycle, first, as in FIG 3 is shown, the counter value Z1 reset and at the falling edge of the positive half wave HW1 of the square wave signal V_R the start signal Start1 to start the counter 41 generated. The counter 41 thus begins its counting process, wherein the counter value Z1 is increased incrementally in response to the clock signal CLK_a, which specifies a clock whose frequency is many times greater than the frequency of the square wave signal V_R.

During the half-wave duration t2 of the negative half wave HW2 of the square wave signal V_R, the counter counts 41 up. At the end of the negative half wave HW2 generates the control logic 3 synchronously with the rising edge of the positive half wave HW3 a stop signal Stop1 and thus stops the counter 41 ,

During the following positive half cycle HW3, the counter value Z1 of the counter is now 41 with the previously determined, stored counter value Z2 of the counter 42 , which reflects the half-wave duration of a preceding positive half-wave, compared and a difference DZ of the counter values Z1, Z2 determined.

At the end of the positive half wave HW3 generates the control logic 3 the reset signal Reset2 and thus sets the counter 42 back to a starting value. At the following rising edge of the positive half wave HW5 generates the control logic 3 the start signal Start2 to start the counter 42 which then increments incrementally in response to the clock signal CLK_a during the positive half-wave HW5. At the end of the positive half wave HW5, the stop signal Stop2 stops to stop the counter 42 is generated, and during the following negative half cycle HW6, the generated counter value Z2 of the counter 42 turn with the counter 41 stored counter value Z1 compared.

Of the Process continues, alternating the half-wave duration t1, t3, t5 of a positive half wave HW1, HW3, HW5 and the half-wave duration t2, t4, t6 of a negative half wave HW2, HW4, HW6 and to continuous correction of the Tastverhaltnisses compared become.

The comparison logic 5 the device according to 2 performs the comparison of the counter values Z1, Z2 of the counters 41 . 42 and forms the difference DZ of the counter values Z1, Z2. Depending on the difference DZ forms the comparison logic 5 a control signal up, down, which can take the value +1 (up) or -1 (down) or the value 0. By means of the control signal up, down increases or decreases the comparison logic 5 the counter value Z of the correction counter 6 or leaves, at a value 0, the counter value Z unchanged. The counter value Z is determined by means of the digital-to-analog converter 7 converted into an offset voltage and superimposed on the periodic signal V_0 to correct the duty cycle.

The correction of the duty cycle is repeated and continuous, while the periodic signal V_0 at the amplifier 1 is applied. The repeated determination of the difference DZ, which reflects the inequality of the half-wave durations t1-t6 of the half-waves HW1-HW6 of the periodic signal V_0, the counter value Z and thus the periodic signal V_0 superposed offset voltage is successively adjusted until the duty cycle of the periodic Signal V_0 the desired setpoint, for example, 1: 1 corresponds.

By means of in 2 schematically illustrated device, the duty cycle of a periodic signal V_0 to a predetermined setpoint, for example, a ratio of 1: 1, be corrected. In the device according to 2 the correction is effected by detecting the half-wave durations t1-t6 of different half-waves HW1-HW6 of the periodic signal V_0 via the linearly operating counters 41 . 42 whose characteristic curve is listed in 4 is illustrated schematically.

The linear enumeration has the effect of correcting the duty ratio of the periodic signal V_0 at different frequencies of the periodic signal V_0 with a different sensitivity. This is due to the fact that at a faulty duty cycle, the differences occurring in the half-wave durations t1-t6 become smaller with increasing frequency and thus the difference DZ of the counter values Z1, Z2 of the counter 41 . 42 at a large frequency of the periodic signal V_0 takes a small value and at a low frequency of the periodic signal V_0 a large value, although the underlying erroneous duty cycle is actually identical. In 4 this is represented by the difference DZL resulting from the counter values Z1L, Z2L at a low frequency of the periodic signal V_0 and the difference DZH resulting from the counter values Z1H, Z2H at a large frequency of the periodic signal V_0. Although the underlying erroneous duty cycle is identical (eg, 1.2: 1), the differences DZL, DZH differ considerably.

Also marked in 4 a maximum counter value Zmax, which is the maximum counter value of the counter 41 . 42 indicates. The maximum counter value Zmax leads to overflow of the counters 41 . 42 and occurs only at very long half-wave durations t1-t6 of the half-waves HW1-HW6 of the periodic signal V_0, ie at low frequencies of the periodic signal V_0, where a correction of the duty cycle is not required.

Another embodiment of a device for regulating the duty ratio of at least one periodic signal is shown in FIG 5 shown. Unlike the embodiment according to 2 uses the embodiment according to 5 instead of the counter 41 . 42 two circuit arrangements 81 . 82 , each one with switches 810 . 811 respectively. 820 . 821 wired capacitor 812 respectively. 822 exhibit. The switches 810 . 811 . 820 . 821 be through a control logic 3 controlled, depending on of one of the control logic 3 supplied square wave signal V_R switching signals S1, S2, S3, S4 generated.

Analogous to the embodiment according to FIG 2 is to be corrected periodic signal V_0 as an input to an amplifier 1 on and off of the amplifier 1 converted into an amplified signal V_A, from which a comparator 2 produced by comparison with a reference voltage V_REF a square wave signal V_R. The square wave signal V_R becomes the control logic 3 supplied in response to the square wave signal V_R the switching signals S1, S2, S3, S4 for controlling the circuit arrangement 81 . 82 and clock signals CLK_a, CLK_b for controlling an evaluation logic 5 ' and a correction counter 6 generated. The correction counter 6 generates a counter value Z, which is a digital-to-analog converter 7 is fed and converted by this into an analog offset voltage, which is connected to the amplifier 1 superimposed on the periodic signal V_0.

The device according to 5 uses the discharge behavior of two capacitors to correct the duty cycle of the periodic signal V_0 812 . 822 the circuit arrangements 81 . 82 out. By means of the discharge behavior of the capacitors 812 . 822 characteristic values are generated which correspond to the half-wave durations of different half-waves of the periodic signal V_0 and by means of which the duty cycle of the signal V_A is corrected.

An exemplary course of voltage signals V1, V2, the charge states of the capacitors 812 . 822 correspond to the outputs of the circuit arrangements 81 . 82 is in 6 shown. The charging and discharging of the capacitors 812 . 822 is doing on the switching states of the switch 810 . 811 . 820 . 821 by means of the control logic 3 controlled.

At the beginning of a first positive half wave HW1 closes the control logic 3 via the switching signal S1, the switch 810 and simultaneously opens the switch via the switching signal S2 811 , To the capacitor 812 with a capacitance C1, the output voltage V_Start plus the reference voltage V_REF connected to ground Gnd is thereby applied, and the capacitor 812 is charged to an initial state.

At the following edge at the end of the half wave HW1 the control logic opens 3 via the switching signal S1, the switch 810 and simultaneously closes via the switching signal 82 the switch 811 , The capacitor 812 so it comes with a resistance 80 connected to the resistance R and forms together with the resistor 80 an RC element, over which the capacitor 812 unloaded.

At the end of the negative half wave HW2 opens the control logic 3 synchronously with the rising edge of the following positive half cycle HW3 the switch 811 , so that the discharging process of the capacitor 812 interrupted and the state of charge of the capacitor 812 is stored at the end of the half wave HW2. That now at the output of the circuit 81 applied voltage signal V1 becomes two comparators 83 . 84 supplied, the voltage signal V1 with a voltage signal V2, the pre-stored state of charge of the capacitor 822 indicates, compare.

The output values of the comparators 83 . 84 become the evaluation logic 5 ' supplied in response to these output values, a control signal up, down to provide the correction counter 6 generated. The comparators have to settle during the half wave HW3 time. With the next edge, the falling edge of the half wave HW3, the output values of the evaluation logic 5 ' taken with the following edge the counter value Z of the correction counter 6 increased, decreased or left unchanged by one bit.

Charging and discharging the capacitor 822 the circuit arrangement 82 takes place analogously and serves to detect the half-wave duration t1, t3, t5 of a positive half-wave HW1, HW3, HW5 of the periodic signal V_0. As in 6 is shown, the capacitor 822 by closing the switch 820 and opening the switch 821 by applying the voltages V_Start plus V_REF loaded in an initial state and discharged during the positive half wave HW5. During the following half cycle HW6 then the voltage signals V1, V2 via the comparators 83 . 84 compared with each other and in the evaluation logic 5 ' evaluated.

The comparators 83 . 84 Compare the voltage signals V1, V2 at the outputs of the circuits 81 . 82 and thus detect a difference DV of the voltage signals V1, V2. To the positive input of the comparator 84 In this case, the voltage signal V1 is applied and compared with the voltage applied to the negative input to a relevance threshold V_A2 increased voltage signal V2. At the positive input of the comparator 83 In contrast, the voltage signal V2 is present and is compared with the voltage applied to the negative input, a relevance threshold V_A1 increased voltage signal V1. Depending on the comparison of the applied signals, the comparators generate 83 . 84 output values 0 or 1, respectively, in the evaluation logic 5 ' be evaluated.

Depending on the difference DV of the voltage signals V1, V2 generate the comparators 83 . 84 different combinations of Off gang values. Is the difference DV (corresponding to the difference of the voltage signals V2-V1 of the discharged capacitors to be compared 812 . 822 ) greater than the relevance threshold V_A1, so gives the comparator 83 z. B. the output value 1 and the comparator 84 the output value 0 off. If the difference DV is smaller than the relevance threshold V_A1 but greater than the negative relevance threshold -V_A2, then both comparators have 83 . 84 z. If the difference DV is smaller than the negative relevance threshold -V_A2, then the comparator 83 z. B. the output value 0 and the comparator 84 the initial value 1.

Depending on the output values of the comparators 83 . 84 generates the evaluation logic 5 ' the control signals up, down for incrementing, decrementing or leaving the counter value Z of the correction counter 6 , This is schematic in 8th shown. If the difference DV lies above the upper relevance threshold V_A1, then the evaluation logic increments 5 ' the correction counter 6 up one bit (+1). If the difference DV lies between the negative relevance threshold -V_A2 and the positive relevance threshold V_A1, then the evaluation logic leaves 5 ' the correction counter 6 unchanged. And if the difference DV is smaller than the negative relevance threshold -V_A2, the evaluation logic decrements 5 ' the correction counter 6 down one bit (-1).

The positive relevance threshold V_A1 and the negative relevance threshold -V_A2 are advantageously chosen equal in their amount and serve to provide a duty cycle correction for minor errors to avoid in the duty cycle.

The device according to 5 Uses the discharge behavior of the capacitors 812 . 822 for detecting the half-wave durations t1-t6 of the half-waves HW1-HW6 of the periodic signal V_0. The capacitors 812 . 822 have an exponential discharge behavior whose time constant is determined by the product of the capacitance values C1, C2 with the resistance value R. The capacitors 812 . 822 advantageously have an identical capacitance C = C1 = C2, so that the capacitors 812 . 822 be discharged with the same time constant RC = RC1 = RC2.

The exponential discharge behavior of the capacitors 812 . 822 is schematic in the form of the on the capacitors 812 . 822 occurring voltage signals V1, V2 in 7 shown. Characteristic here is that the capacitors 812 . 822 initially discharged quickly, but slows down the discharge speed with time t due to the exponential behavior. This has the consequence that with short discharge times - as they occur in a periodic signal V_0 large frequency with small half-wave durations t1-t6 - a small difference DtH leads in the discharge to a large difference DVH in the voltage signals V1, V2. In the case of long discharge times, on the other hand, a comparatively larger difference DtM in the discharge times leads to a comparable difference DVM of the voltage signals V1, V2.

Due to the exponential discharge behavior of the capacitors 812 . 822 It is achieved that the sensitivity in the correction of the duty cycle over a relatively large frequency range is approximately constant and in particular at high frequencies compared to the duty cycle correction by means of a linear counter (see 2 ) is increased. The differences DVH and DVM in the voltage signals V1, V2 according to 7 are approximately equal in magnitude and correspond to an equal duty cycle of the half-waves HW1-HW6 of the periodic signal V_0 at different frequencies.

In 7 is a threshold V_thr located, which indicates a limit for the voltage signals V1, V2, below which no correction of the duty cycle should take place. If the voltage signals V1, V2 fall below the threshold value V_thr due to a long discharge time at low frequencies of the periodic signal V_0, the evaluation logic decreases 5 ' no adjustment of the correction counter 6 in front.

The embodiments of the devices according to 2 and 5 allow a correction of the duty ratio of at least one periodic signal V_0, for example in the context of speed and position determination of a moving part of an actuator or the like. Compared to the embodiment according to 2 The embodiment according to FIG 5 doing so by using the capacitors 812 . 822 for detecting the half-wave durations t1-t6 of the half-waves HW1-HW6 of the periodic signal V_0 has the advantage that a largely constant sensitivity in the correction of the duty cycle is achieved over a large frequency range.

Conventionally, the correction of the duty cycle takes place in that a characteristic value for the duty cycle as the ratio of the half-wave durations t1, t2, t3, t4,... Of a positive half-wave HW1, HW3,... To a negative half-wave HW2, HW4,... or conversely a negative half-wave HW2, HW4, ... to a positive half-wave HW1, HW3, ... detected and then the duty cycle is corrected to a predetermined setpoint based on this characteristic. The correction on the basis of such a fixed ratio (positive to negative or negative to positive) is unproblematic if the periodic signal V_0 to be corrected has a constant frequency, since in this case it is always correctly recognized, whether the half-wave duration t1, t2, ... a half-wave HW1, HW2, ... is shorter or longer than the half-wave duration t1, t2, ... another half-wave HW1, HW2, ... and the duty cycle is thus erroneous.

has However, the periodic signal V_0, for example due to the acceleration or decelerating a moving part of an engine to be detected a variable frequency, so does the Duty cycle correction to problems when the duty cycle correction fixed by the ratio of the half-wave durations t1, t2,... of the positive to the negative half-waves HW1, HW2, ... or the negative to the positive half-waves HW1, HW2, ... is determined.

This is exemplified in 9A illustrated, in which a square wave signal V_R an accelerated periodic signal V_0 with increasing frequency and shorter and shorter half waves HW1-HW8 is shown. In the example according to 9A the duty cycle is always determined based on the ratio of the half-wave duration t1, t3, t5, t7 a positive half-wave HW1, HW3, HW5, HW7 to half-wave duration t2, t4, t6, t8 a negative half wave HW2, HW4, HW6, HW8. This results in correction intervals I1, I2, I3, I4, in each of which the ratio of the half-wave durations t1-t8 is detected and in which the half-wave duration t1, t3, t5, t7 of the positive half-wave HW1, HW3, HW5, HW7 are each greater than is the half-wave duration t2, t4, t6, t8 of the negative half-wave HW2, HW4, HW6, HW8. This leads to an error in the duty cycle of the same polarity being determined in each case within the duty cycle correction since the half-wave duration t1, t3, t5, t7 of the positive half-wave HW1, HW3, HW5, HW7 is always greater than the half-wave duration t2, t4, t6 , t8 is the subsequent negative half wave HW2, HW4, HW6, HW8. For correction, therefore, the correction counter 6 (please refer 2 or 5 ) always changes in the same direction, so that its value Z runs away.

As a result the shorter and shorter half-wave durations t1-t8, conditioned by the frequency change of the periodic signal V_0, there is thus an incorrect correction of the duty cycle.

In order to avoid erroneous correction of the duty cycle in the event of a frequency change of the periodic signal V_0, the example according to FIG 9B the correction of the duty cycle not fixed on the basis of the ratio of the positive to the negative half-wave duration t1-t8 made, but alternately.

First, in the example according to 9B detected in a correction interval I1, the duty cycle of a positive half-wave HW1 to a negative half-wave HW2. Due to the fact that the half-wave duration t1 of the positive half-wave HW1 is greater than the half-wave duration t2 of the negative half-wave HW2, this leads to a correction of the duty cycle in one direction, for example by incrementing the counter value Z of the correction counter 6 (please refer 2 or 5 ).

In a second correction interval 12 Now, the ratio of the half-wave duration t2 of the negative half-wave HW2 to the half-wave duration t3 of the following positive half-wave HW3 is detected, and due to the fact that the negative half-wave duration t2 is greater than the positive half-wave duration t3, the counter value Z of the correction counter 6 corrected in the opposite direction compared to the first correction interval I1 and thus compensated for the first correction.

The correction of the duty cycle in the correction intervals I3-I7 takes place alternately, the counter value Z of the correction counter 6 each corrected in different directions and thus no adjustment of the duty cycle is made. By means of the alternating correction of the duty cycle by alternating the positive half wave HW1, HW3, HW5, HW7 to the negative half wave HW2, HW4, HW6, HW8 and vice versa of the negative half wave HW2, HW4, HW6, HW8 to the positive half wave HW1, HW3, HW5, HW7 thus an erroneous correction of the duty cycle due to a change in frequency of the periodic signal V_0 is avoided.

Used as the maximum correction increment when adjusting the correction counter 6 the Least Significant Bit is used, the effect of the correction on the control of an engine is negligible overall.

The basis 9B Correction of the duty cycle, in particular in the case of frequency-variable periodic signals V_0, can advantageously be used in conjunction both with the device according to FIG 2 as well as with the device according to 5 be used.

Of the The idea underlying the invention is not based on the preceding limited embodiments described. In particular, other circuit arrangements for the correction of Duty cycle of at least one periodic signal can be used using a capacitor, which advantageously a correction of the duty cycle of two periodic Make signals that as 90 ° out of phase with each other Signals on a motor to determine the speed and position a rotating part are generated.

1

amplifier

2

comparator

3

control logic

41 42

counter

43

oscillator

5

comparison logic

5 '

evaluation logic

6

correction counter

7

Digital to analog converter

80

resistance

81, 82

circuitry

810 811, 820, 821

switch

812 822

capacitor

83 84

comparator

A1, A2

amplitude

a1k, a2k

corrected amplitude

C1, C2

capacity

clk_a, clk_b

clock signal

comp

comparison signal

DtH, DtM

difference

DV, DVH, DVM

difference

DZ, DZH, DZL

difference

Gnd

Dimensions

HW1-HW8

half-wave

I1-I7

correction interval

R

resistance

Reset1, Reset2

Reset signal

Start1, Start 2

start signal

Stop1, Stop2

stop signal

S1, S2, S3, S4

switching signal

t

Time

t1-t8

Half-wave duration

up, down

actuating signal

V

tension

V_0

input

V_0k

corrected input

V_A

reinforced signal

V_A1, V_A2

relevance threshold

V_R

square wave

V_REF

reference voltage

V_START

output voltage

V_thr

threshold

V1, V2

voltage signal

Z

count

Z1, Z2

count

Z1L, Z2L

count at low frequency

z 1, Z2H

count at high frequency

Zmax

maximum count

QUOTES INCLUDE IN THE DESCRIPTION

This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.

Cited patent literature

• - DE 3514155 A1 [0007]
• US 4475086 [0008]

Claims (16)

Method for controlling the duty cycle of at least one periodic signal in which the duty cycle is corrected to a predetermined desired value on the basis of the ratio of the half-wave durations of two half-waves of the periodic signal, characterized in that for determining a characteristic value for the half-wave duration (t1-t8) of a half wave ( HW1-HW8) for correcting the duty cycle - a capacitor ( 812 . 822 ) is brought into an initial state in which the capacitor ( 812 . 822 ), - the capacitor ( 812 . 822 ) during the half-wave duration (t1-t8) of the half-wave (HW1-HW8) is discharged starting from the initial state and - based on the state of charge of the capacitor ( 812 . 822 ) at the end of the half-wave (HW1-HW8), which represents a characteristic value for the half-wave duration (t1-t8) of the half-wave (HW1-HW8), the duty cycle is corrected. A method according to claim 1, characterized in that for correcting the duty cycle, a first capacitor ( 812 ) during the half-wave duration (t1, t3, t5, t7) of a first half-wave (HW1, HW3, HW5, HW7) and a second capacitor ( 822 ) during the half-wave duration (t2, t4, t6, t8) of a second half-wave (HW2, HW4, HW6, HW8) which is different from the first half-wave (HW1, HW3, HW5, HW7), the state of charge of the first capacitor ( 812 ) at the end of the first half-cycle (HW1, HW3, HW5, HW7) a characteristic value for the half-wave duration (t1, t3, t5, t7) of the first half-wave (HW1, HW3, HW5, HW7) and the state of charge of the second capacitor ( 822 ) at the end of the second half-wave (HW2, HW4, HW6, HW8) represents a characteristic value for the half-wave duration (t2, t4, t6, t8) of the second half-wave (HW2, HW4, HW6, HW8) and the difference (DV) of Charge states of the two capacitors ( 812 . 822 ) the duty cycle is corrected. A method according to claim 2, characterized in that based on the difference (DV) of the charge states of the capacitors ( 812 . 822 ) A control signal (up, down) for correcting the duty cycle is generated. Method according to Claim 3, characterized in that the states of charge of the capacitors ( 812 . 822 ) via at least one comparator ( 83 . 84 ), wherein, depending on the output value of the at least one comparator ( 83 . 84 ) the control signal (up, down) the counter value (Z) of a correction counter ( 6 ) is incremented, decremented or unchanged to correct the duty cycle. Method according to Claim 3 or 4, characterized in that the states of charge of the capacitors ( 812 . 822 ) via two comparators ( 83 . 84 ) are compared with each other, based on the output values of the two comparators ( 83 . 84 ) the control signal (up, down) the counter value (Z) of a correction counter ( 6 ) - incremented when the difference (DV) of the charge states of the capacitors ( 81 . 82 ) exceeds a positive relevance threshold (V_A1), - decrements when the difference (DV) of the charge states of the capacitors ( 81 . 82 ) falls below a negative relevance threshold (V_A2), - leaves unchanged when the difference (DV) of the charge states of the capacitors ( 81 . 82 ) lies between the positive relevance threshold (V_A1) and the negative relevance threshold (V_A2). Method according to one of the preceding claims, characterized in that from the representing an input signal periodic signal (V_0) formed a square wave signal (V_R) and corrected by the square wave signal (V_R) the duty cycle becomes. Method according to one of the preceding claims, characterized in that the capacitor ( 812 . 822 ) with switches ( 810 . 811 . 820 . 821 ) whose switching states for charging and discharging the capacitor ( 812 . 822 ) via a control logic ( 3 ) to be controlled. Method according to claim 7, characterized in that the capacitor ( 812 . 822 ) for charging via a first switch ( 810 . 820 ) is connected to an output voltage (V_START). Method according to claim 7 or 8, characterized in that the capacitor ( 812 . 822 ) for discharging via a second switch ( 811 . 821 ) with a resistor ( 80 ) and via the resistor ( 80 ) is unloaded. Method according to one of the preceding claims, characterized in that the duty cycle alternately by the ratio of the half-wave duration (t1, t3, t5, t7) of a positive half-wave (HW1, HW3, HW5, HW7) to the half-wave duration (t2, t4, t6, t8) of a following negative half-wave (HW2, HW4, HW6, HW8) and the ratio of the half-wave duration (t2, t4, t6, t8) of a negative half-wave (HW2, HW4, HW6, HW8) to the half-wave duration (t1, t3, t5, t7) of a following positive half cycle (HW1, HW3, HW5, HW7) is corrected. A method according to claim 10, characterized in that based on the respective ratio of the half-wave durations (t1-t8), an actuating signal (up, down) for correcting the duty cycle of the periodic signal (V_0) is generated, wherein dependent on the respective ratio of the half-wave durations (t1-t8) the control signal (up, down) the counter value (Z) of a correction counter ( 6 ) for correcting the duty cycle of the periodic signal (V_0) is incremented, decremented or left unchanged. Method according to claim 11, characterized in that the control signal (up, down) is a least significant bit corresponding step size has. Device for controlling the duty cycle of at least one periodic signal, with at least one circuit arrangement for correcting the duty cycle to a predetermined desired value on the basis of the ratio of the half-wave durations of two half-waves of the periodic signal, characterized in that the circuit arrangement ( 81 . 82 ) at least one capacitor ( 812 . 822 ) for determining a characteristic value for the half-wave duration (t1-t8) of a half-wave (HW1-HW8), wherein the circuit arrangement ( 81 . 82 ) and is provided, - the capacitor ( 812 . 822 ) in an initial state in which the capacitor ( 812 . 822 ), - the capacitor ( 812 . 822 ) during the half-wave duration (t1-t8) of the half-wave (HW1-HW8) starting from the initial state and - based on the state of charge of the capacitor ( 812 . 822 ) at the end of the half-wave (HW1-HW8) provide a characteristic value for the half-wave duration (t1-t8) of the half-wave (HW1-HW8) for correcting the duty cycle. Apparatus according to claim 13, characterized by two circuit arrangements ( 81 . 82 ) each with a capacitor ( 812 . 822 ) for determining a characteristic value for the half-wave duration (t1-t8) of two different half-waves (HW1-HW8) of the periodic signal (V_0). Device according to claim 14, characterized by at least one comparator ( 83 . 84 ) for comparing the states of charge of the capacitors ( 812 . 822 ) of the two circuit arrangements ( 81 . 82 ). Apparatus according to claim 15, characterized by at least one evaluation logic ( 5 ' ) for determining an actuating signal (up, down) for correcting the duty cycle from the output values of the at least one comparator ( 83 . 84 ).