DE102008002546A1 - Arrangement for stress decoupling in a substrate with a chip - Google Patents
Arrangement for stress decoupling in a substrate with a chip Download PDFInfo
- Publication number
- DE102008002546A1 DE102008002546A1 DE200810002546 DE102008002546A DE102008002546A1 DE 102008002546 A1 DE102008002546 A1 DE 102008002546A1 DE 200810002546 DE200810002546 DE 200810002546 DE 102008002546 A DE102008002546 A DE 102008002546A DE 102008002546 A1 DE102008002546 A1 DE 102008002546A1
- Authority
- DE
- Germany
- Prior art keywords
- substrate
- chip
- arrangement according
- chip area
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09081—Tongue or tail integrated in planar structure, e.g. obtained by cutting from the planar structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10083—Electromechanical or electro-acoustic component, e.g. microphone
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10151—Sensor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Micromachines (AREA)
Abstract
Es wird eine Anordnung zur Stressentkopplung bei einem Substrat (5), insbesondere einer Leiterplatte, vorgeschlagen, wobei mindestens ein Chip (10) vorgesehen ist. Der Chip (10) ist auf einem Chip-Bereich (15) des Substrates (5) angeordnet. Weiter ist mindestens eine Aussparung (20) um den Chip-Bereich (15) im Substrat (5) vorgesehen. Die Aussparung (20) verläuft dabei vertikal durch die gesamte Dicke des Substrates (5).An arrangement for stress decoupling in a substrate (5), in particular a printed circuit board, is proposed, wherein at least one chip (10) is provided. The chip (10) is arranged on a chip area (15) of the substrate (5). Furthermore, at least one recess (20) is provided around the chip area (15) in the substrate (5). The recess (20) extends vertically through the entire thickness of the substrate (5).
Description
Stand der TechnikState of the art
Die Erfindung betrifft eine Anordnung zur Stressentkopplung bei einem Substrat, insbesondere bei einer Leiterplatte, mit einem Chip gemäß dem Oberbegriff des Anspruchs 1.The The invention relates to an arrangement for stress decoupling in a Substrate, in particular in a printed circuit board, with a chip according to the preamble of claim 1.
In der elektronischen Aufbau- und Verbindungstechnik (AVT) ist es bekannt, einen Chip auf einem Substrat, beispielsweise auf einer Leiterplatte, zu montieren. Dabei ist eine sichere und feste Verbindung zwischen dem Chip und dem Substrat zu gewährleisten. Verschiedene Techniken, die in vielen Fällen auch miteinander kombiniert werden können, sind hierfür entwickelt worden. So können die Chips bei sogenannten „Chip an Board”-Aufbauten (COB) mittels „Flip Chip”-Technik auf das Substrat gelötet werden. Auch ist der Vorgang bekannt, dabei die Chips ganz oder teilweise mit einer Moldmasse zu umhüllen.In the electronic assembly and connection technology (AVT) it is known a chip on a substrate, for example on a circuit board, too assemble. There is a secure and firm connection between to ensure the chip and the substrate. Various Techniques, which in many cases also combined have been developed for this purpose. So the chips can with so-called "chip on board" constructions (COB) using "flip chip" technique on the substrate be soldered. Also, the process is known, while the chips completely or partially with a molding compound to wrap.
In allen bekannten Techniken ist jedoch das Auftreten von thermomechanischen Spannungen eine Problematik, die die Zuverlässigkeit des gesamten Aufbaus gefährdet. Als eine Hauptursache für das Auftreten von thermomechanischen Spannungen bzw. Stress werden die unterschiedlichen thermischen Ausdehnungskoeffizienten der am Aufbau beteiligten Materialien angesehen.In however, all known techniques involve the occurrence of thermomechanical Tensions a problem that affects the reliability of the entire structure endangered. As a main cause of that Occurrence of thermo-mechanical stresses or stress will be the different coefficients of thermal expansion of the building involved Materials viewed.
Ein Ansatz zur Stressreduzierung besteht darin, durch geeignete Materialauswahl die Ausdehnungskoeffizienten der jeweiligen Materialen so aufeinander abzustimmen, dass der Unterschied der Ausdehnungskoeffizienten möglichst gering wird. In der Praxis jedoch besteht keine ausreichende, zufriedenstellende Kombinationsmöglichkeit der Materialauswahl, insbesondere bei mehrschichtigen Aufbauten.One Approach to stress reduction is by appropriate material selection the expansion coefficients of the respective materials to each other to agree that the difference of the expansion coefficients as possible becomes low. In practice, however, there is no sufficient, satisfactory Possible combination of material selection, in particular in multi-layered structures.
Ein
anderer Ansatz sieht vor, im Aufbau Aussparungen zur Stressreduzierung
vorzusehen. So wird beispielsweise in
Jedoch hat der Chip in der vorgeschlagenen Anordnung in allen lateralen Richtungen eine mechanische Verbindung zum Substrat, da die grabenförmige Struktur um den Chip nur ansatz- bzw. teilweise vertikal in die Substratschicht hinein verläuft. Folglich liegt trotz der grabenförmigen Struktur eine weitgehende mechanische Entkopplung des Chips vom Rest des Substrats nicht vor.however has the chip in the proposed arrangement in all lateral Directions a mechanical connection to the substrate, as the trench-shaped Structure around the chip only partially or partially vertically into the Substrate layer extends into it. Consequently, despite the trench-shaped structure a substantial mechanical decoupling of the chip from the rest of the substrate.
Vorteile der ErfindungAdvantages of the invention
Die erfindungsgemäße Anordnung eines Substrates mit einem Chip hat den Vorteil, dass eine weitgehende Stressentkopplung des Chips vom Substrat erzielt wird. Ermöglicht wird diese Wirkung durch die Merkmale des Anspruchs 1. Durch die Maßnahme, dass eine Aussparung um den Chip vorgesehen ist, die vertikal durch die gesamte Dicke des Substrates verläuft, wird an diesen Stellen eine komplette thermomechanische Abkopplung des Chips vom Rest des Substrates erreicht. Die Anordnung ermöglicht so, einen stressentkoppelten ”Chip an Board”-Aufbau bereitzustellen.The inventive arrangement of a substrate with a chip has the advantage that a substantial stress decoupling of the chip is achieved by the substrate. This is possible Effect of the features of claim 1. By the measure, that a recess is provided around the chip, the vertically through the entire thickness of the substrate runs, is at this Make a complete thermomechanical decoupling of the chip from Remains of the substrate reached. The arrangement allows so, a stress-decoupled "chip on board" structure provide.
Vorteilhafte Weiterbildungen der Erfindung sind in den Unteransprüchen angegeben und in der Beschreibung beschrieben.advantageous Further developments of the invention are in the subclaims specified and described in the description.
Zeichnungdrawing
Ausführungsbeispiele der Erfindung werden anhand der Zeichnungen und der nachfolgenden Beschreibung näher erläutert. Es zeigen:embodiments The invention will be apparent from the drawings and the following Description explained in more detail. Show it:
Beschreibung der AusführungsbeispieleDescription of the embodiments
Es wird eine Anordnung zur Stressentkopplung bei einem Substrat, insbesondere bei einer Leiterplatte, mit mindestens einem Chip vorgeschlagen, wobei der Chip auf einem Chip-Bereich des Substrates angeordnet ist und mindestens eine Aussparung um den Chip-Bereich im Substrat vorgesehen ist. Dabei verläuft die Aussparung erfindungsgemäß vertikal durch die gesamte Dicke des Substrates. Die Tiefe der Aussparung entspricht also mindestens der Dicke des Substrates. Die Erzeugung der Aussparungen kann je nach Dicke, Fläche und Material des Substrates durch Ätzen, Fräsen, Lasern oder Bohren erfolgen.An arrangement for stress decoupling in a substrate, in particular in a printed circuit board, with at least one chip is proposed, wherein the chip is arranged on a chip region of the substrate and at least one recess is provided around the chip region in the substrate. The recess according to the invention extends vertically through the entire thickness of the substrate. The depth of the recess thus corresponds at least to the thickness of the substrate. Depending on the thickness, area and material of the substrate, the production of the recesses can take place by etching, milling, lasering or drilling.
Ein
erstes Ausführungsbeispiel wird nun gemäß der
in
Die
Aussparungen
Weiter
weist der Chip-Bereich
Es
wird festgestellt, dass der Chip-Bereich
Im übrigen
wird darauf hingewiesen, dass die erfindungsgemäße
Anordnung besonders für solche Fälle geeignet
ist, wenn der Chip
Auf
dem Substrat
In
einem zweiten Ausführungsbeispiel gemäß
In
einem dritten Ausführungsbeispiel gemäß
Im übrigen
können mehrere Federstrukturen
Bei
der Auslegung des Chip-Bereiches
ZITATE ENTHALTEN IN DER BESCHREIBUNGQUOTES INCLUDE IN THE DESCRIPTION
Diese Liste der vom Anmelder aufgeführten Dokumente wurde automatisiert erzeugt und ist ausschließlich zur besseren Information des Lesers aufgenommen. Die Liste ist nicht Bestandteil der deutschen Patent- bzw. Gebrauchsmusteranmeldung. Das DPMA übernimmt keinerlei Haftung für etwaige Fehler oder Auslassungen.This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.
Zitierte PatentliteraturCited patent literature
- - DE 10323296 A1 [0005] - DE 10323296 A1 [0005]
Claims (10)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE200810002546 DE102008002546A1 (en) | 2008-06-20 | 2008-06-20 | Arrangement for stress decoupling in a substrate with a chip |
PCT/EP2009/055101 WO2009153094A1 (en) | 2008-06-20 | 2009-04-28 | Arrangement for decoupling stress in a substrate with a chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE200810002546 DE102008002546A1 (en) | 2008-06-20 | 2008-06-20 | Arrangement for stress decoupling in a substrate with a chip |
Publications (1)
Publication Number | Publication Date |
---|---|
DE102008002546A1 true DE102008002546A1 (en) | 2009-12-24 |
Family
ID=40943794
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE200810002546 Ceased DE102008002546A1 (en) | 2008-06-20 | 2008-06-20 | Arrangement for stress decoupling in a substrate with a chip |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE102008002546A1 (en) |
WO (1) | WO2009153094A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011009501A1 (en) | 2009-07-20 | 2011-01-27 | Sony Ericsson Mobile Communications Ab | Method for arranging a component on a circuit board |
WO2020201574A1 (en) * | 2019-04-05 | 2020-10-08 | Sensirion Automotive Solutions Ag | Sensor module, particularly for measuring ambient temperature |
EP3736534A4 (en) * | 2018-01-05 | 2021-08-18 | SZ DJI Technology Co., Ltd. | Circuit board and unmanned aerial vehicle using circuit board |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102020001590A1 (en) | 2020-03-04 | 2021-09-09 | Ziehl-Abegg Se | Monitoring device of a device, in particular an electric motor, and method for detecting vibrations and / or shocks acting on devices |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10323296A1 (en) | 2003-05-21 | 2005-01-05 | Infineon Technologies Ag | Arrangement for stress reduction for substrate-based chip packages has uniform trench-shaped structures on chip side of substrate to interrupt or displace thermally induced mechanical stress |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3905657A1 (en) * | 1989-02-24 | 1990-08-30 | Telefunken Electronic Gmbh | Flexible supporting film |
USH921H (en) * | 1990-10-18 | 1991-05-07 | The United States Of America As Represented By The Secretary Of The Army | Stress controlling mounting structures for printed circuit boards |
US20050006141A1 (en) * | 2003-07-10 | 2005-01-13 | Stillabower Morris D. | Circuit assembly having compliant substrate structures for mounting circuit devices |
DE102005051615A1 (en) * | 2005-10-27 | 2007-05-16 | Rossmax Int Ltd | Anti-pressure linear circuit board manufacture for making circuit board, comprises providing a first circuit board, and cutting the first circuit board to form cut grooves |
CN101524001A (en) * | 2006-10-10 | 2009-09-02 | Tir科技公司 | Circuit board with regional flexibility |
-
2008
- 2008-06-20 DE DE200810002546 patent/DE102008002546A1/en not_active Ceased
-
2009
- 2009-04-28 WO PCT/EP2009/055101 patent/WO2009153094A1/en active Application Filing
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10323296A1 (en) | 2003-05-21 | 2005-01-05 | Infineon Technologies Ag | Arrangement for stress reduction for substrate-based chip packages has uniform trench-shaped structures on chip side of substrate to interrupt or displace thermally induced mechanical stress |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011009501A1 (en) | 2009-07-20 | 2011-01-27 | Sony Ericsson Mobile Communications Ab | Method for arranging a component on a circuit board |
US8294037B2 (en) | 2009-07-20 | 2012-10-23 | Sony Ericsson Mobile Communications Ab | Method for arranging a component on a circuit board |
EP3736534A4 (en) * | 2018-01-05 | 2021-08-18 | SZ DJI Technology Co., Ltd. | Circuit board and unmanned aerial vehicle using circuit board |
US11304292B2 (en) | 2018-01-05 | 2022-04-12 | SZ DJI Technology Co., Ltd. | Circuit board and unmanned aerial vehicle including the same |
WO2020201574A1 (en) * | 2019-04-05 | 2020-10-08 | Sensirion Automotive Solutions Ag | Sensor module, particularly for measuring ambient temperature |
Also Published As
Publication number | Publication date |
---|---|
WO2009153094A1 (en) | 2009-12-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
R012 | Request for examination validly filed | ||
R012 | Request for examination validly filed |
Effective date: 20150303 |
|
R016 | Response to examination communication | ||
R002 | Refusal decision in examination/registration proceedings | ||
R003 | Refusal decision now final |