DE102006013419A1 - Integrated electronic circuit manufacturing method, involves subjecting porous silicon in wafer to thermal treatment, and closing pores at process of treatment, where material needed for closing is derived from low lying layer of silicon - Google Patents

Abstract

The method involves producing a circuit structure (20) in a defined wafer section (18), which is cut from a semiconductor wafer (10) by using shearing force. A p-doped silicon in the region of an upper surface (12) of the wafer is converted into porous silicon with several pores by an anodic etching process. The porous silicon is then subjected to a thermal treatment. The pores at the upper surface are closed at the process of the treatment, where material necessary for closing the pores is derived from a low lying layer of porous silicon. An independent claim is also included for an integrated circuit with a circuit structure.

Description

• – Bereitstellen eines Halbleiterwafers mit einer ersten und einer zweiten Oberfläche,
• – Erzeugen von zumindest einer Schaltungsstruktur in einem definierten Waferabschnitt im Bereich der ersten Oberfläche, und
• – Heraustrennen des definierten Waferabschnitts aus dem Halbleiterwafer, wobei der Waferabschnitt in einem ersten Prozessablauf freigestellt wird, so dass er nur noch über lokale, stegartige Verbindungen an dem verbleibenden Halbleiterwafer gehalten wird, und wobei die stegartigen Verbindungen in einem zweiten Prozessablauf aufgetrennt werden.

The present invention relates to a method for producing an integrated circuit, comprising the steps:

• Providing a semiconductor wafer having a first and a second surface,
• Generating at least one circuit structure in a defined wafer section in the region of the first surface, and
• - Separating the defined wafer portion of the semiconductor wafer, wherein the wafer portion is released in a first process flow, so that it is held only on local, web-like compounds on the remaining semiconductor wafer, and wherein the web-like compounds are separated in a second process flow.

One such method is known from WO 2005/104223 A1.

The in particular, the present invention relates to a method of manufacturing of so-called chips with an integrated electronic circuit, wherein the chips or the chip material are very thin. Chips according to the invention can have a thickness of significantly less than 300 microns, advantageously a thickness of 50 microns and less. Such a thin one Chips are well suited for the production of so-called 3D chips, where several thin chips each stacked with an integrated circuit. About that In addition, such thin ones have Chips due to the low material thickness some flexibility, so that on flexible substrates, such as. a plastic film, can be used.

One way to produce such thin chips with an integrated circuit is to first fabricate the integrated circuit on a semiconductor wafer having a thickness of, for example, 500 μm to 1 mm. After the integrated circuit is fabricated, the back side of the semiconductor wafer is removed by a mechanical and / or chemical process. Subsequently, the semiconductor wafer, which typically carries a plurality of integrated circuits, must be singulated to the chips. Conventionally, this is done by sawing, cutting, cutting or scribing and breaking. A method of separating semiconductor wafers into chips is known in DE 40 29 973 A1 described.

The The procedure described has the disadvantage that a considerable Part of the wafer material is lost by the removal unused. Furthermore, must relatively large distances be provided between the individual chips on a wafer, with enough Space for sawing, Cutting loops etc. available stands. Typical distances are here in an order of magnitude from 500 μm to 1 mm. This all adversely affects the cost of manufacturing of thin integrated circuits, i. Chips with material thicknesses of less than 150 μm.

The WO 2005/104223 A1, referred to above, describes a method in which at the first surface of the semiconductor wafer first a variety of vertical trenches by an anisotropic etching process getting produced. Subsequently will the open first surface closed again by an epitaxial layer and the semiconductor wafer becomes a heat treatment (Annealing) subjected. As a result, individual closed channels below the first surface be formed. In another anisotropic etching process then vertical Additions to the hidden channels created. Subsequently become the interior walls of the channels and the vertical accesses provided with an oxide layer by an oxidation process. The channels and vertical accesses surround a wafer portion at the first surface, in FIG then in conventional Way a circuit structure is generated. Subsequently, the Oxide layer in the channels and vertical accesses another etching process removed, so that the wafer section only via web-like connections connected to the rest of the wafer at its bottom. These Connections are broken by the wafer section after torn out of the top of the remaining semiconductor wafer, being supplementary also a torsional motion is proposed. With this procedure Chips are to be made with a thickness of less than 10 microns.

adversely At this procedure appears that the bottom of the isolated Chips a high roughness (compared to the material thickness of the chips) should have because at the bottom of the wafer section irregular break edges the former bar-type connections remain. Besides that is generating the deep oxide layers below the wafer section and their later, selective rejection elaborate and difficult.

From an article by Overstolz et al. entitled "A Clean Wafer-Scale Chip-Release Process Without Dicing Based on Vapor Phase Etching", 17th IEEE International Conference on Micro Electro Mechanical Systems, January 2004, pages 717 to 720, discloses a micromechanical sensor, namely a Inclinometer, by means of different etching processes from a silicon material to dissolve.As starting material an SOI wafer (Silicon on Insulator) is used.To release the inclination sensor trenches and holes etched from both the front and back of the wafer material. In addition, the oxide film disposed in the semiconductor material is partially etched by bringing a hydrofluoric acid vapor into the inside of the semiconductor wafer through the holes on the front side and the back side.

US 6,165,813 describes a method for detaching thin chips attached to a flexible substrate by bending the substrate. US 6,521,068 describes a method of dicing chips from a substrate by heating a region underneath the chip with a laser.

JP 2002-299500 describes the removal of chips by means of a so-called Dummy substrate.

Finally, in the prior art, the production and use of porous silicon is known. DE 197 52 208 A1 discloses a method of making a membrane sensor wherein a thin layer of silicon carbide or silicon nitride is deposited over a region of porous silicon. The porous silicon is then removed as sacrificial material with ammonia. As a result, a cavity which thermally decouples the sensor membrane from the remaining substrate is formed under the membrane layer of silicon carbide or silicon nitrite.

Of another becomes porous Silicon in the so-called ELTRAN process (epitaxial layer TRANsfer) used, with its help SOI wafer getting produced. The procedure is in a publication by T. Yonehara and K. Sakaguchi, entitled "ELTRAN; Novel SOI-Wafer Technology "in JSAP International No. 4, July 2001 appeared.

In front In this context, it is an object of the present invention to to provide an alternative method to possible thin integrated circuits as possible economical and with good quality and yield.

These Task is done according to a Aspect of the present invention by a method of the preamble solved kind, in which the wafer section is thus released in the first process sequence is that the web-like connections on a lateral periphery of the wafer section are arranged.

The new procedure differs from the procedure of the beginning mentioned WO 2005/104223 A1 in that the load-bearing web-like connections, which hold the wafer section before the final singulation, attack substantially laterally on the wafer portion. Preferably the web-like connections hold the wafer section at several opposite corners or sides surrounding the wafer portion. In some embodiments The invention relates to the web-like connections at the corners of a arranged rectangular wafer section. In other embodiments can the web-like connections on the longitudinal sides of a rectangular wafer section to sit. About that In addition, the present invention is not limited to rectangular wafer sections (and corresponding chips) limited. For example, you can web-like connections also on the outer circumference of a round in the base or be arranged elliptical wafer section.

The present invention includes not that individual web-like connections also below of the triggering Wafer section exist. However, this is dependent on the method, with the wafer section is released in the first process sequence, a "residual effect" (below) running).

In First, however, the wafer portion according to the present invention will be from the local, web-like connections at its lateral periphery held.

By the new way of "suspending" the wafer section on its periphery it is possible to use the Press wafer section into the semiconductor wafer to the web-like connections break. The wafer section can thus according to the new method by a pressure force from above from the remaining material of the Semiconductor wafers are broken out. In contrast, must in the method according to the aforementioned WO 2005/104223 A1 A tensile force must be applied, and this traction must be so strong be that they have the web-like connections in their longitudinal direction separates. In contrast, you can shear forces in the new process used to separate the web-like connections. Considered that the wafer section in preferred embodiments of the Invention very thin is (material thickness smaller than 150 μm and preferably in the range below 50 microns), one recognizes that the danger damage of the wafer portion is smaller in the new method. Furthermore are the separation points on the lateral periphery of the wafer section, a certain distance from the sensitive circuit structures may have in the wafer portion. In contrast, they are violently broken Separation points in the known method directly below the sensitive circuit structures.

With the present invention, therefore, the risk that the wafer portion is damaged when singulated, can be significantly reduced. Above it hi In addition, the separation can be carried out in preferred embodiments in a very cost-effective manner with known devices that are used for handling and assembly of SMD components (Surface Mounted Devices).

Furthermore the new method has the advantage that the remaining semiconductor wafer be used again for the production of integrated circuits can be, if one abrades the remaining web remainders on the first surface. In order to the semiconductor wafer is used optimally. The manufacturing costs for thin integrated Circuits can be reduced.

Finally owns the new process has the advantage of having the bottom of the wafer sections (at least largely) free of breakages and artifacts, whereby the wafer section or the chip is processed more easily and accurately can be, for example, when stacking for a 3D chip or when arranging on a thin one Foil.

All in all allows the new process thus a cost-effective and high-quality production of thin integrated circuits. The object mentioned is therefore completely solved.

As already mentioned, be the web-like compounds in a preferred embodiment of Procedure with the help of a pressure from above on the first surface broken. Alternative or supplementary can do this the web-like connections also by means of a torsional movement be broken up.

These Design allows the handling of the wafer sections with the aid of gripping tools, as they are also used to handle SMD components. This is a particularly cost-effective and rational production of thin Chips possible.

In Another embodiment includes the first process step the creation of a closed wafer cavity below the defined wafer portion. Preferably, the circuit structure becomes over the closed wafer cavity generated.

The Realization of the new method with a closed cavity has the advantage that the semiconductor wafer despite cavity (or. with a variety of such cavities for one Variety of such wafer sections) can be stored in stock, which further streamlines the production process and even more cost-effective can be made.

• – Bereitstellen eines Substratwafers mit einer Oberseite aus einem ersten Halbleitermaterial, insbesondere einem hoch-p-dotierten Silizium,
• – Erzeugen einer Vielzahl von porösen Bereichen in dem ersten Halbleitermaterial, wobei jeder poröse Bereich eine Flächenausdehnung besitzt, die in etwa der Flächenausdehnung des definierten Waferabschnitts entspricht, und
• – Erzeugen einer Deckschicht auf der Oberseite, die die porösen Bereiche überdeckt.

In another embodiment, the production of the wafer cavity includes the following steps:

• Providing a substrate wafer having a top side made of a first semiconductor material, in particular a highly p-doped silicon,
• Producing a multiplicity of porous regions in the first semiconductor material, each porous region having an areal extent which corresponds approximately to the areal extent of the defined wafer section, and
• - Generating a cover layer on the top, which covers the porous areas.

Preferably covered the cover layer covers the entire surface of the semiconductor wafer, so that the semiconductor wafer from the outside hardly or not at all to be distinguished from a semiconductor wafer without cavities is.

With This configuration can be very suitable wafer cavities economical produce. This embodiment is therefore particularly advantageous for mass production of integrated circuits.

In In a further embodiment, each porous area with a large-pored produced lower layer and a fine-pored upper layer.

The Penetration depth and pore size of the layers can when producing the porous Areas can be varied by, for example, the current density of a stream is varied by a solution from hydrofluoric acid and ethanol flows, in which the substrate wafer of monocrystalline silicon as the anode is arranged (see the above-mentioned publication of Yonehara / Sakaguchi). By having a large pore bottom Layer and a fine-pored upper layer produced, can be the wafer cavity easier to close up. Below provides a large pore lower layer for that, that the wafer section is as free as possible over the remaining wafer material "floats." The larger the Pore size here is, the less is the wafer portion with the underlying Wafer material connected.

In In a further embodiment, the substrate wafer is after the production the porous one Areas heated to produce the topcoat.

In this embodiment, the substrate wafer is subjected to a heat treatment (annealing) after the production of the porous regions. This closes the pores on the top. In addition, so the pore size in the deeper areas can be increased. There is a kind of reflow process, with the help of which (preferably fine-pored) material on the top like which is transformed into a monocrystalline structure. The required material comes from the deeper, preferably large-pored layer. This embodiment is particularly advantageous to produce a suitable cavity in a cost effective manner.

In Another embodiment is on the top of a second Semiconductor material applied to produce the cover layer. In preferred embodiments The invention is an epitaxial layer on the uppermost crystalline Grown up by the above-described reflow process above the Cavity was created.

These Design facilitates later production of the circuit structures in the wafer portion, because the circuit structures in a "normal" monocrystalline Semiconductor material can be generated. Therefore, it is possible the new method in this embodiment particularly simple in Integrate existing production processes.

In In a further embodiment, the substrate wafer has a third one Semiconductor material, preferably a low p-type semiconductor material (for Example silicon), which under the first semiconductor material (preferably highly p-doped silicon), the porous regions only be produced in the first semiconductor material.

These Embodiment is particularly advantageous to a possible level surface over the cavities too receive. For the production of the porous It is namely layers advantageous to use a highly p-doped silicon. In contrast, be for the Circuit structure often Less heavily doped areas needed. It is therefore an advantage the already mentioned Epitaxial layer on the top of the semiconductor wafer to apply. However, different high dopings can cause stresses in the material due to different lattice constants. These Tensions can entail that the surface of the semiconductor wafer is wavy. By now the porous areas generated in a highly doped layer on a third semiconductor material is arranged, one can by suitable choice of the process parameters take care Bear in mind that the lattice constants of the materials after manufacturing the porous one Layer are better adapted to each other. This can be done At least reduce stresses and consequent ripples.

In In a further embodiment of the invention, the wafer section in the first process flow from the second surface optional.

In This embodiment is material below the herauszuösenden wafer section from the bottom, ie from the second surface ago, removed. This can in addition happen to a cavity under the wafer section. Prefers However, this configuration is without a cavity under the wafer section realized. This embodiment of the method is particularly preferred realized with an SOI wafer, wherein the wafer portion with the Circuit structures in the upper semiconductor layer of the SOI wafer is formed and wherein the lower material layer (bulk silicon) is etched out before or after the generation of the circuit structures.

These Design is particularly advantageous to a very smooth surface on the Obtain the underside of the wafer section. Accordingly suitable This configuration especially for applications that are very high Requirements for the surface quality of the backside of the isolated chip. Nevertheless, this configuration also makes from the fundamental Advantages of the new method use, in particular the possibility the chips with the help of conventional SMD gripping tools too to separate and process.

In Another embodiment includes the first process flow the creation of trenches the first surface of the semiconductor wafer after the circuit pattern is formed in the wafer portion has been.

In this embodiment, the first process flow can be divided into two, by including at least two temporally separate stages. This For example, if the wafer section using a Cavity which is advantageously produced, before the circuit patterns are fabricated in the wafer section. In contrast, become the trenches after this embodiment of the method only after manufacture the circuit structure etched or otherwise generated. However, the present embodiment is also advantageous in the alternative variants of the new method, in which a cavity is dispensed with. Generally owns the Design the advantage that the production of the integrated circuit easier and thus cheaper in existing production processes can be integrated, since the semiconductor wafer in the manufacture of Circuit structures has a (at least largely) closed surface.

In a further embodiment, a semiconductor wafer is provided, which has at least one upper, one middle and one lower material layer, wherein the circuit structure is produced in the upper material layer, and wherein the middle material layer is etched out in the first process step to expose the wafer section. virtue example, an SOI wafer is used as the starting material in this embodiment.

As already mentioned above is, can be using a multi-layer semiconductor wafer chips with a very smooth and high quality back produce. The use of an SOI starting material contributes beyond to a reduction in production costs, because SOI wafers as Standard products cost-effective to disposal stand.

In In another embodiment, at least one passage opening in generated to the wafer portion to an etchant to the middle material layer respectively.

These Embodiment is advantageous because it is an exact "undercutting" of the wafer section facilitates, in particular if the wafer section laterally an extension owns, which is significantly larger than the thickness of the second material layer. The production of the integrated Circuits are accelerated in this way and the yield is increased.

In In another embodiment, the wafer section is in the semiconductor wafer arranged in [100] orientation or in [110] orientation and the web-like Connections become at the corners or at the side edges of the wafer section arranged.

Because in particular the breaking behavior of semiconductor wafers in dependence different from the position of a fracture edge relative to the crystal lattice, you can through this configuration for separating the compounds required forces and also influence the formation of the separation points. With the preferred Embodiments leaves an optimal triggering reach the wafer section.

It it is understood that the above and the following yet to be explained features not only in the specified combination, but also in other combinations or alone, without to leave the scope of the present invention.

embodiments The invention are illustrated in the drawings and in the following description explained. Show it:

1 a simplified, schematic representation for explaining a first embodiment of the new method,

2 a simplified representation for explaining a variant of the method in which a wafer cavity is produced under the wafer portion,

3 a schematic representation of the separation of the chips in an embodiment of the new method,

4 a schematic representation for explaining a further embodiment of the new method, and

5 a schematic representation for explaining a further embodiment.

In 1 is a semiconductor wafer with the reference numeral 10 designated. The semiconductor wafer 10 has a first surface 12 and an opposing second (lower) surface 14 , Below the first surface 12 is a cavity 16 arranged so that a wafer section 18 is suspended above the cavity, as in 1a ), the semiconductor wafer has a plurality of such cavities 16 which are hidden inside the semiconductor material.

In a first embodiment of the invention, such a semiconductor wafer 10 provided ( 1a ). Subsequently, in the wafer sections 18 above the cavities 16 each generates a circuit structure in a conventional manner. The circuit structure is in 1b at the reference number 20 indicated schematically. It lies in preferred embodiments in [100] or [110] direction with respect to the crystal lattice of the wafer material. The wafer section 18 with the circuit structure 20 forms a future chip with an integrated circuit, which now consists of the semiconductor wafer 10 must be removed.

This is done in the embodiment shown in that a plurality of trenches 22 in the surface 12 of the semiconductor wafer 10 etched into it, with the individual trenches 22 through web-like areas 24 are separated from each other. In the preferred embodiment, the trenches are 22 latticed on the surface 12 of the semiconductor wafer 10 distributed and they form a pattern of vertical and horizontal trenches. There, where a vertical and a horizontal ditch 22 is a web-like area 24 remained, which was not etched. Four trenches each surround a wafer section 18 with the integrated circuit structure 20 , Accordingly, here is each wafer section 18 only at its four corners by the web-like connections 24 held. Alternatively, the wafer sections could 18 also be held over web-like connections, not at the corners, but for example at the center of the side edges of each wafer section 18 are arranged.

As in 1c is shown, the individual wafer sections 18 from the grid of trenches 22 be broken out, and you get in this way chips 26 with an integrated semiconductor structure.

2 shows a preferred embodiment to a semiconductor wafer 10 to 1 manufacture. According to 2a initially becomes a substrate wafer 32 provided, for example, consists of monocrystalline, weakly p-doped silicon. According to 2 B becomes the substrate wafer 32 with a photomask 34 provided and exposed. The photomask 34 covers the surface of the substrate wafer 32 only partially and the vacancies can be processed in a known manner.

In the illustrated embodiment, the substrate wafer 32 through the mask 34 P-doped to a high-p-doped semiconductor region 36 to obtain. The underlying substrate material 32 ' still has only a lower p-type doping.

According to 2c then become porous layers 38 . 40 in the highly doped semiconductor material 36 generated. For this purpose, the substrate wafer is added in a preferred embodiment as an anode in a solution of hydrofluoric acid and ethanol, so that a current can flow through the solution to the substrate wafer. As a result, porous silicon forms in the region of the highly doped semiconductor material 36 wherein the pore size can be varied by varying the current density. In the preferred embodiment, a fine-pored layer 38 on the surface of the substrate wafer and a large pore layer 40 underneath it. A more detailed description of the preparation of these layers is contained in the above-mentioned publication by Yonehara / Sakaguchi, which is incorporated herein by reference.

According to 2d becomes the photomask 34 subsequently removed and the wafer 32 '' with the porous layers 38 . 40 is subjected to a heat treatment. As a result, the pores in the upper fine-pored layer 38 at least partially reclose and the upper layer 38 again in a largely uniform, monocrystalline layer 42 is transformed, under the large-pored layer 40 ' is located, whose pore size has increased. The large-pored layer 40 now forms the cavity that is in 1 with the reference number 16 is designated. Within this cavity still isolated webs (not shown here) may remain, which is the upper layer 42 with the underlying substrate material 32 ''' connect. However, such lands are the result of process variations and practical shortcomings in creating the cavity 16 , The wafer section is held 18 out 1 primarily through the side next to the cavity 16 remaining bridges 24 due to the mask structure 34 have stopped.

According to 2f will be another layer next 44 as a cover layer on the surface of the substrate material 32 ''' applied. In a preferred embodiment, this is an epitaxial layer of monocrystalline, moderately p-doped silicon, which on the layer 42 or grown on the entire surface of the semiconductor wafer. This gives a semiconductor wafer 10 according to the process steps according to 1 is provided as starting material.

As from the synopsis of 1 and 2 As can be seen, the lateral surface extent corresponds to the porous layers 38 . 40 in about the lateral surface extent of the cavity 16 and thus also approximately the lateral surface extent of the wafer section 18 in which the circuit structure 22 is produced. Thus determines the lateral surface extent of the porous layers 38 . 40 also the chip area of the later chip 26 ,

3 shows a preferred embodiment for separating the chips 26 , Thereafter, the individual chips with the help of a gripping tool 50 that captures the chips 26 (more precisely, the wafer sections 18 still at the web-like connections 24 hang) with vacuum sucks. By a pressure from above (Pfeil 52 ) become the web-like connections 24 broken up by the single chip 26 is pushed down into the cavity. Then the chip can 26 with the gripping tool 50 be picked up and processed further. Alternatively or additionally, the chips 26 also by tensile forces and / or torsional forces from the wafer 10 to be broken out.

Among the advantages of in 1 and 2 It is heard that the remaining semiconductor wafer 10 after removing all chips 26 can be recycled. For this purpose, the semiconductor wafer 10 with the remaining web areas 24 ( 3d ) ground and polished on its upper side, as in 3e at the reference number 54 is shown symbolically. This yields a (somewhat thinner) substrate wafer 32 , the process sequence again 2 can be subjected.

As in 3 is shown grips the gripping tool 50 the individual chips 26 largely congruent. Accordingly, the gripping tool 50 in the area of its lower gripping surface 56 formed approximately the same size as the lateral surface extent of the chip 26 , This allows the gripping tool 50 the sensitive chips 26 si keep it. The risk of damage when breaking out of the semiconductor wafer 10 will be further minimized.

4 shows a further embodiment of the new method. Here is a semiconductor wafer 60 provided as a starting material, which is an upper material layer 62 , a middle material layer 64 and a lower material layer 66 has. In a preferred embodiment, it is an SOI wafer in which the upper and lower layers of material 62 . 66 consist of monocrystalline silicon, while the middle material layer 64 made of silicon dioxide. In general, it is preferred if the upper material layer 62 and the middle material layer 64 relatively thin compared to the lower material layer 66 are.

According to 4b becomes the semiconductor wafer 60 (before or after fabricating the circuit structure, which is not shown here for clarity) on its underside with a photomask 68 provided an area below the future chip 26 leaves free. Subsequently, according to 4c the lower layer of material removed, as far as not through the photomask 68 is covered. In the illustrated embodiment, the lower material layer 66 removed by an etching process when reaching the middle material layer 64 is stopped. A chemical wet or dry etching process may be used.

According to 4d Next, the middle material layer is removed, as far as they are by the removal of the lower material layer 66 was exposed. Now is the (future) chip 26 only held laterally, as in 4d is shown. Next are trenches 22 produced, with only web-like connections 24 left over. The introduction of the trenches can after the in 4c shown process step or earlier done.

Subsequently, the chip 26 from the semiconductor wafer 60 broken out like this in 3 is shown.

Alternatively or additionally, the mean material layer can also be used 64 remain wholly or partially to web-like connections between the chip 26 and the remaining wafer material. In this case, the trenches 22 in the upper material layer 62 surround the entire chip area (not shown here). The web-like connections 24 then lie below the surface 12 in the middle material layer 64 but still on the periphery of the future chip 26 ,

5 shows a further embodiment in which a semiconductor wafer 60 with at least three superposed material layers 62 . 64 . 66 is used as starting material. Again, an SOI wafer is suitable as a starting material.

According to 5b become trenches 22 from above into the two upper material layers 62 . 64 etched, leaving only bar-like connections 24 remain, which are in the illustrated embodiment, again in the corner areas, where converging trenches 22 to meet. As in 5b is shown, the trenches are enough 22 down to the lower material layer 66 down.

The trenches 22 are again arranged in the form of a grid, so that rectangular areas arise in which the circuit structures (not shown here) are generated in a conventional manner. It is preferred if the circuit structures before the etching of the trenches 22 in the upper material layer 62 of the semiconductor wafer 60 getting produced.

In preferred variants of this embodiment also through openings 72 in the area of the chip area 26 etched, with the openings 72 only through the upper material layer 62 through rich. This provides access to the middle material layer 64 in the area of the chip area 26 created.

As in 5b can be seen, in this embodiment, two trenches each 22 etched parallel next to each other so that between the two parallel trenches 22 a narrow bridge area 72 remains. According to 5c become these web areas 74 then with a photomask 76 covered, which is designed so that they are the exposed sides of the chip area 26 not covered.

Now according to 5d ) removes the middle material layer (oxide layer) with the aid of hydrofluoric acid. So the chips are hanging 26 only at the web-like connections 24 in the corner areas. The chips 26 can now be separated in the same way as based on 3 was explained. The remaining semiconductor wafer ( 5f ) can then be recycled and used for a new manufacturing process.

Claims (14)

A method of manufacturing an integrated circuit, comprising the steps of: - providing a semiconductor wafer ( 10 ; 60 ) having a first and a second surface ( 12 . 14 ), - generating at least one circuit structure ( 20 ) in a defined wafer section ( 18 ) in the region of the first surface ( 12 ), and - separating out the defined wafer section ( 18 ) from the semiconductor wafer ( 10 ; 60 ), wherein the wafer section ( 18 ) in a first process so that it only has local, web-like connections ( 24 ) on the remaining semiconductor wafer ( 10 ; 60 ), and wherein the web-like connections ( 24 ) are separated in a second process sequence, characterized in that the wafer section ( 18 ) is released so that the web-like connections ( 24 ) at a lateral periphery of the wafer section ( 18 ) to be ordered. A method according to claim 1, characterized in that the web-like connections ( 24 ) by means of a pressure ( 52 ) from above onto the first surface ( 12 ) are broken up. Method according to claim 1 or 2, characterized in that the first process step comprises the production of a closed wafer cavity ( 16 ) under the defined wafer section ( 18 ) includes. Method according to Claim 3, characterized in that the circuit structure ( 20 ) over the closed wafer cavity ( 16 ) is produced. Method according to claim 3 or 4, characterized in that the production of the wafer cavity ( 16 ) comprises the following steps: - providing a substrate wafer ( 32 ' ) having a top side made of a first semiconductor material ( 36 ), - generating a plurality of porous regions ( 38 . 40 ) in the first semiconductor material ( 36 ), each porous region ( 38 . 40 ) has a surface extent which is approximately the surface area of the defined wafer section ( 18 ), and - producing a cover layer ( 42 . 44 ) on the top, covering the porous areas ( 38 . 40 ) covered. Method according to claim 5, characterized in that each porous area is provided with a large-pored lower layer ( 40 ) and a fine-pored upper layer ( 38 ) is produced. Method according to claim 5 or 6, characterized in that the substrate wafer ( 32 '' ) after the creation of the porous regions ( 38 . 40 ) is heated to the top layer ( 42 ) to create. Method according to one of claims 5 to 7, characterized in that a second semiconductor material ( 44 ) is applied to the top to create the cover layer. Method according to one of claims 5 to 8, characterized in that the substrate wafer ( 32 ' ) a third semiconductor material ( 32 ), which under the first semiconductor material ( 36 ), the porous regions ( 38 . 40 ) only in the first semiconductor material ( 36 ) be generated. Method according to one of claims 1 to 9, characterized in that the wafer section ( 18 ) in the first process flow from the second surface ( 14 ) is released. Method according to one of claims 1 to 10, characterized in that the first process sequence, the production of trenches ( 22 ) on the first surface ( 12 ), after the circuit structure ( 20 ) in the wafer section ( 18 ) was generated. Method according to claim 11, characterized in that a semiconductor wafer ( 60 ), which has at least one upper, one middle and one lower material layer ( 62 . 64 . 66 ), wherein the circuit structure in the upper material layer ( 62 ) and the average material layer ( 64 ) is etched out in the first process step to form the wafer section ( 18 ). A method according to claim 12, characterized in that at least one passage opening ( 72 ) in the wafer section ( 18 ) is generated to an etchant to the middle material layer ( 64 ) respectively. Method according to one of claims 1 to 13, characterized in that the wafer section ( 18 ) is arranged in the semiconductor wafer in the [100] -direction or in the [110] -direction and that the web-like connections ( 24 ) at corners or at side edges of the wafer section ( 18 ) to be ordered.