DE10137752C1 - Device for triggering a switch element has a source of signals linked to a control input for a switch element generating a control signal to determine the switching status of the switch element. - Google Patents

Abstract

A source of signals (3,5) links to a control input for a switch element (T1,T2) and generates a control signal to determine the switching status of the switch element. A test element (8,10) detects a test signal (IDRAIN,USOURCE) that returns a current flowing through the switch element or a voltage at the output of the switch element. An Independent claim is also included for a method for triggering a controllable switch element.

Description

The invention relates to a device for controlling a Switching element such as a power amplifier according to the preamble of claim 1 and a corresponding one Operating method according to the preamble of claim 12.

As is known, for switching inductive loads Power amplifiers with transistors, especially MOSFET Transistors, used as circuit breakers. At the scarf ten of the transistors must be in the inductive consumer stored energy either through a zener of the final stage or be broken down via a freewheeling diode, whereby for Las with high inductive energy may be free running diode is used. A disadvantage of such amplifiers consists in the fact that this considerable electromagnetic interference generate stanchions. This is known to be due to the fast Voltage changes at the output of the circuit breakers and caused by rapid current changes in the supply line fen.

DE 198 55 604 C1 describes a method for controlling a Power output stage known to reduce e leads to electromagnetic interference when switching. With these known control methods, the power stage during of a switching process in succession with different Current values controlled. So at the beginning of a shift operation each with a relatively large Control current to achieve the desired switching speed pass. This is then followed by control with a lower current value in order to change the rate of change (slew Rate) at the output of the power stage and thus also the e limit electromagnetic interference. The dimension tion of the two in succession during a switching operation  current values for controlling the power output stage follows as part of a compromise between the goal the highest possible switching speed on the one hand and the aim of minimizing electromagnetic interference other hand.

A disadvantage of the known control described above The procedure for a final power stage is, on the one hand, that it neglected the fact that current and voltage at ei nem inductive consumer are not in phase, so that Rate of change of voltage from rate of change of current can deviate. It would therefore be desirable to have the An Control of the power stage and both the rate of change Set voltage as well as the rate of change of current can.

Another disadvantage of the known described above Control procedure for a power stage consists of that the sequential control with only two current rate a relatively good one during each switching operation Compromise between the desired switching speed ei on the other hand and the desired prevention of electromagnetic interferences on the other hand, but in stationary Ren final state of the switching element after completion of each shifting to a possibly unsatisfactory Continuity or blocking resistance leads.

The invention is therefore based on the object Known control methods described above improve that the rates of change of the current and the span can be influenced separately and beyond the lowest possible pass-through after a switching operation the resistance or the greatest possible blocking resistance becomes.

The invention is based on the above described NEN known control method for a power stage  according to the preamble of claim 1, by the character nenden features of claim 1 solved.

The invention comprises the general technical teaching, an e electrical switching element such as a power power amplifier one after the other during a switching process to be controlled with at least three different control signals.

It is in the preferred embodiment of the invention the control signals differed by current signals Lichen current values, for example the gate charge current of a MOSFET transistor. The switching element will here in each case during a switching operation controlled with at least three different current values ert, preferably four different current values during of a switching operation follow one another. The first current value is preferably relatively large in order to be as possible to achieve fast switching speed. The second By contrast, the current value is preferably relatively small and determined the rate of change (slew rate) of the current, while the third Current value preferably the rate of change (slew rate) of the Tension determined. When switching on is the second Amount of current preferably less than the third Current value, whereas the second current value on an off switching operation is preferably greater in amount than that third current value.

Finally, the switching element is controlled while rend a switching operation preferably with a fourth Current value, the fourth current value preferably amount ß is larger than the previous current values, in order to ei Nem switching operation as low a continuity stood or to achieve the greatest possible blocking resistance chen.

Each switching operation of the switching element is thus shared the control method according to the invention in at least three  Phases in which the control of the switching element with different control signals or current values.

The change between the individual phases can be selected here rend each time controlled, in which each phase has a predetermined period of time.

In the preferred embodiment of the invention, the Change between the individual phases during a shift process depending on the measured fort step of switching. For example, the current flowing through the switching element can be measured, the already changes during a switching operation, so that the current value of the current flowing through the switching element information about the progress of the switching process tains. There is also the option at the exit of the Switching element to measure applied voltage, which is just if changes already during a shift, so that also the current value of the voltage at the output of the switch mentes information about the progress of the switching device gangs included. In this context it should be mentioned that current and voltage at the output of the switching element an inductive consumer with a free-wheeling diode not in Phase, but are out of phase with each other. In the preferred embodiment therefore takes place both Measurement of the current flowing through the switching element as also a measurement of the voltage at the output of the switching element tes to get information about the. from these two measurement signals To derive progress of the switching state.

Determining the progress of the shift from the measurement signals determined during the switching process takes place preferably by comparison with one or more thresholds.

So is the current flowing through the switching element in each case during the switching process preferably with a given  NEN current limit value compared, the control signal or the current value for controlling the switching element when over- or falling below the current limit value is changed.

Similarly, there is also the possibility that during of a switching operation at the output of the switching element de voltage with at least one voltage threshold compare and control the switching element at Ü Exceeding or falling below the voltage threshold change.

Other developments of the invention are in the dependent claims Chen are marked below or together with the Description of the preferred embodiment of the invention tion explained in more detail with reference to the figures. Show it:

Fig. 1 shows an inventive device for dently tion of a switching element for a Elektromo gate,

Fig. 2 is a timing diagram to illustrate the zeitli chen course of gate current, drain current and drain voltage in the illustrated in FIG. 1 arrangement,

FIGS. 3a-3c, the driving method according to the invention in the form of a flow chart, wherein the positions 3a shows Preset Fig., A switching process A whereas Fig. 3b and reproduces a gear Ausschaltvor Fig. 3c.

The arrangement shown in Fig. 1 in the form of a schematic block diagram is used to control an Elektromo gate 1 , wherein the electric motor 1 can be controlled with any polarity to allow operation in both directions of rotation.

In the following, the structural design of the circuit is first described, in order to subsequently explain the mode of operation of the circuit using the time diagram shown in FIG. 2 and the flow diagram shown in FIGS . 3a to 3b.

The electric motor 1 has two connections, the first connection of the electric motor 1 being connected to a battery U _BAT via a transistor T1 in the form of a MOSFET transistor, while the second connection of the electric motor 1 is connected to ground GND via a transistor T4 is. When the transistors T1 and T4 are switched on, the electric motor 1 is thus supplied with voltage and thus rotates in a predetermined first direction of rotation.

In addition, the first connection of the electric motor 1 is connected to ground GND via a transistor T3, while the second connection of the electric motor 1 is connected to the battery U _BAT via a transistor T2. When the transistors T2 and T3 are switched on, the reverse polarity of the voltage is applied to the electric motor 1 and therefore rotates in a predetermined second direction of rotation.

The control of the transistors T3 and T4 can in conventional cher way take place and plays no wide for the invention re role. However, it is also possible to use the transistors T3 and Control T4 also in the manner according to the invention.

It is pointed out that the circuit shown in FIG. 1 is constructed in mirror image, the circuit arrangement for controlling the transistor T1 being almost identical to the circuit arrangement for controlling the transistor T2. In the following, therefore, for simplification, only the part of the circuit shown in FIG. 1 will be written, which is used to drive the transistor T1, where the same reference numerals are used for the part of the circuit used to drive the transistor T2.

The only difference between the circuit arrangement used to control transistor T1 and the circuit arrangement used to control transistor T2 is that the circuit arrangement used to control transistor T2 is implemented using PMOS technology, whereas the circuit arrangement used to control transistor T1 in NMOS technology is implemented, so that a charge pump 2 is additionally required.

The gate input of the transistor T1 is connected to ground via a controllable current sink 3 , the current sink 3 drawing a current during a switch-off operation of the transistor T1, which current is specified by a control unit 4 , as will be described in detail below.

Furthermore, the gate input of the transistor T1 is connected to a controllable current source 5 , which drives a gate current during a switch-on operation, which is predetermined by the control unit 4 , as is also to be described in detail.

The controllable current source 5 is connected to a voltage supply unit 6 , which in turn is connected to ground GND.

The control of the switch-on process or the switch-off process of the transistor T1 is carried out by a logic unit 7 , but the control unit takes into account the current progress of the switching process.

To determine the current progress of the switching process, a current sensor 8 is provided, which is only shown schematically and measures the electrical current I _{DRAIN flowing} through the transistor T1.

On the output side, the current sensor 8 is connected to a comparator unit 9 , which in each case _{compares the} current I _DRAIN flowing through the transistor T1 with a predetermined current limit value I _TH during a switching operation in order to determine the current progress of the switching operation. The comparator unit 9 therefore sends a status signal to the control unit 4 , which indicates whether the current flowing through the transistor T1 is above or below the current limit value I _TH .

To determine the current progress of the switching process, a voltage sensor 10 is also provided, which measures the source voltage at the output of the transistor T1, ie between the transistor T1 and the electric motor 1 .

On the output side, the voltage sensor 10 is connected to a comparator unit 11 , which compares the measured source voltage of the transistor T1 with two predetermined voltage limit values U _TE1 and U _TH2 . On the output side, the comparator unit 11 transmits a status signal to the control unit 4 , which indicates whether the source voltage of the transistor is above or below the two voltage limit values U _TH1 and U _TH2 .

Depending on the state signals generated by the comparator units 9 and 11 and in dependence on the logic unit 7 , the control unit 4 then controls the controllable current source 5 or the controllable current sink 3 such that the desired gate current for the transistor T1 is activated provides.

The mode of operation of the circuit according to the invention will now be described with reference to the time diagram shown in FIG. 2 and the flow diagram shown in FIGS . 3a to 3b.

Thus, the timing diagram in Fig. 2 shows an on and off switching operation of the transistor T1. The switching times of the transistor are small compared to the time constant of the load. Between the times t ₁ and t ₅ , the diagram shows a switch-on process of the transistor T1 and between the times t ₆ and t ₁₀ a switch-off process of the transistor T1, while the transistor T4 is switched on statically. In contrast, between times t ₅ and t ₆ , transistor T1 is switched through, while transistor T1 is blocked from time t ₁₀ .

In FIG. 2, the time characteristic is the top of the gate current of the transistor T1 shown, wherein it can be seen that each switching operation in four phases with different gate currents splits.

In the following, the individual phases are first described during a switch-on process between times t ₁ and t ₅ . In the first phase of the switch-on process between times t ₁ and t ₂ , the gate current initially assumes a relatively large value T _S1 in order to achieve the fastest possible switching speed. In the second phase of the switch-on process between times t ₂ and t ₃ , the gate current then decreases to a relatively small value I _A in order to limit the rate of change (slew rate) of the output current. In the third phase of the switch-on process between the times t ₃ and t ₄ , the gate current then increases again to a somewhat larger value I _B , the value I _{B determining} the rate of change (slew rate) of the output voltage. Finally, the gate current for transistor T1 increases in the fourth phase of the switch-on process between times t ₄ and t ₅ to a relatively large value I _CP1 , this current value I _{CP1 being} sufficiently large to fully open the transistor and thereby to achieve the lowest possible contact resistance after completing the switching process.

The individual phases of the switch-off process of the transistor T1 between the times t ₆ and t ₁₀ will now be described, the following details relating in each case to an inverse polarity of the gate current. In the first phase of the switch-off process between times t ₆ and t ₇ , the gate current initially assumes a relatively large value I _S2 in order to achieve the highest possible switching speed. In the second phase of the switch-off between the times t ₇ and t ₈ , the gate current then drops to a smaller value I _B , this value determining the change values (slew rate) of the output voltage of the transistor T1. In the third phase of the switch-off process between the times t ₈ and t ₉ , the gate current then drops to an even smaller value I _A , this value I _{A being} the rate of change (slew rate) of the drain current of the transistor T1 Right. In the fourth phase of the switch-off process between the times t ₉ and t ₁₀ , the gate current of the transistor T1 then finally assumes a relatively large value I _CP2 in order to control the transistor T1 as completely as possible and thereby do one after the end of the switch-off process to achieve the greatest possible blocking resistance.

In the following will now be described, the change between the individual phases of A as operation switching operation is carried out during the power, wherein the center in Fig. 2. detected time curve of the drain current and the curve shown in Fig. 2 below the source Voltage of transistor T1 is referenced.

The change from the first phase of the switch-on process to the second phase of the switch-on process takes place when the drain current I _{DRAIN exceeds} the predetermined current limit value I _TH , which is the case in the example shown at time t ₂ . The change from the second phase of the switch-on process to the third phase of the switch-on process takes place, on the other hand, when the source voltage of the transistor T1 exceeds the predetermined first voltage limit value U _TH1 , which is the case here at time t ₃ . Finally, the change from the third to the fourth phase of the switch-on process takes place when the source voltage U _{SOURCE of} the transistor T1 exceeds the predetermined second voltage limit value U _TH2 .

In the following, the change between the individual phases of the switching off of the transistor T1 will now be described. The change from the first phase to the second phase of the switch-on process takes place when the source voltage of the transistor T1 _falls below the predetermined second voltage limit value U _TH2 , which is the case here at the time t ₇ . The change from the second phase to the third phase of the switch-off operation takes place, however, when the source voltage U _{SOURCE falls below} the first voltage limit value U _TH1 , which is the case at time t ₈ . Finally, the change takes place from the third to the fourth phase of the switch-off process here at time t ₉ when the drain current I _{DRAIN falls below} the predetermined current limit value I _TH .

The operating method of the circuit shown in FIG. 1 will now be explained with reference to the flowchart shown in FIGS . 3a to 3c.

At the beginning there is first a setting process, which is shown in FIG. 3a, the values of the gate current being determined in the individual phases of the switching on and off process as part of the setting process.

Thus, in the first two steps of the setting process, the gate current I _{S1 is} first determined for the first phase of the switch-on process, this current value influencing the switch-on duration and therefore being determined as a function of the desired switch-on duration T _ON .

In the next two steps of the setting process, the gate current I _S2 is then determined for the first phase of the switch-off process, this current value influencing the switch-off duration and therefore being determined as a function of the desired switch-off duration T _OFF .

Then, in the next two steps, the gate current I _{A is determined} for the second phase of the switch-on process and the third phase of the switch-off process, this current value I _{A influencing} the rate of change (slew rate) for the source voltage of the transistor T1 and is therefore determined as a function of the maximum permissible rate of change SRU for the source voltage.

The gate current I _B for the third phase of the switch-on process and the second phase of the switch-off process is then determined in the next two steps, this current value I _{B influencing} the rate of change (slew rate) of the source voltage and therefore as a function of the maximum permissible rate of change SRU of the source voltage is determined.

Furthermore, the gate current I _{CP1 is determined} for the fourth phase of the switch-on process, this value influencing the volume resistance of the transistor T1 after the switch-on process has ended and is therefore determined as a function of the desired volume resistance R _D.

Finally, the gate current I _{CP2 is determined} for the fourth phase of the switch-off process, this value influencing the blocking resistance R _{S of} the transistor T1 after the switch-off process has ended and is therefore determined as a function of the desired blocking resistor.

The flowchart in FIG. 3b, which shows a switching-on process of the transistor T1, is now explained below. So the gate current I _{S1 is} maintained until the measured drain current I _{DRAIN of} the transistor T1 exceeds the predetermined current limit value I _TH , whereupon the gate current I _{A is then set} for the second phase of the switch-on process.

This gate current I _{A is then} maintained until the source voltage U _{SOURCE of} the transistor T1 exceeds the predetermined first voltage limit value U _TH1 , whereupon the gate current I _{B is then set} for the third phase of the switch-on operation.

This value I _{B is} then maintained until the source voltage U _SOURCE also _exceeds the second predetermined voltage limit value U _TH2 , whereupon the gate current I _{CP1 is then set} for the fourth phase of the switch-on process.

In the following, the flow diagram shown in Fig. 3c will now be explained, which represents a switching off of the transistor T1.

Thus, the gate current I _S2 is initially set in the first phase of the switch-off process, this current value being maintained until the source voltage U _{SOURCE falls below} the second voltage limit value U _TH2 again, whereupon the current value I _B for the second phase of the switch-off process is set.

This current value I _B is then maintained in the second phase of the switching-off process between times t ₇ and t ₈ until the source voltage U _SOURCE also falls below the pregiven first voltage limit value U _TH1 , whereupon the gate current is set to the predetermined current value I _A for the third phase of the switch-off process.

This value I _A for the gate current is maintained until the drain current I _{DRAIN of} the transistor T1 _{falls below} the predetermined current limit value I _TH , whereupon the gate current is then set to the current value I _CP2 by the transistor To control T1 as completely as possible.

The invention is not to be described above preferred embodiment limited. Rather is one Numerous variations and modifications conceivable, the just if make use of the inventive idea and therefore fall within the protection area.

Claims (22)

1. Device for controlling a control input of a controllable switching element, with
a signal source ( 3 , 5 ) connected on the output side to the control input of the switching element (T1, T2) for generating a control signal (I _GATE ) which determines the switching state of the switching element (T1, T2),
a first measuring element ( 8 , 10 ) for detecting a first measuring signal (I _DRAIN , U _SOURCE ), which represents the current flowing through the switching element (T1, T2) or the voltage at the output of the switching element (T1, T2),
a control circuit ( 4 , 7 ) connected on the input side to the first measuring element ( 8 , 10 ) and on the output side to the signal source ( 3 , 5 ), which outputs the control signal (I _GATE ) emitted by the signal source ( 3 , 5 ) during a switching operation influenced depending on the first measurement signal,
characterized by
that the signal source ( 3 , 5 ) emits at least three different control signals (I _S1 , I _A , I _B , I _CP1 ) in succession as a function of the first measurement signal during a switching operation. 2. Device according to claim 1, characterized in that the signal source has a controllable current source ( 5 ) which is connected on the voltage side to the control input of the switching element (T1, T2), the output current of the current source ( 5 ) from the first measurement signal depends. 3. Device according to claim 1 or 2, characterized in that the signal source has a controllable current sink ( 3 ) which is connected on the ground side to the control input of the switching element (T1, T2), the input current of the current sink depending on the first measurement signal. 4. The device according to claim 2 or 3, characterized in that the output current of the current source and / or the input current of the current sink during a switching process in dependence on the first measurement signal successively at least three discrete current values (I _S1 , I _A , I _B , I _CP1 ) assumes. 5. The device according to at least one of the preceding claims, characterized in that the control circuit ( 4 , 7 ) on the input side is additionally connected to a second measuring element ( 8 , 10 ) which generates a second measurement signal, the control circuit ( 4 , 7 ) influences the control signal (I _GATE ) emitted by the signal source ( 3 , 5 ) during a switching operation as a function of the first measurement signal and the second measurement signal. 6. The device according to claim 5, characterized in
that the first measuring element is a current sensor ( 8 ), which measures the current flowing through the switching element as the first measuring signal, and
that the second measuring element is a voltage sensor ( 10 ) which, as the second measuring signal, measures the voltage at the output of the switching element (T1, T2). 7. The device according to claim 6, characterized in that
that the current sensor ( 8 ) is connected on the output side to a first comparator unit ( 9 ) which _{compares the} current (I _DRAIN ) flowing through the switching element with a predetermined current limit value (I _TH ),
wherein the control signal (I _GATE ) changes during a switch-on process from a larger first current value (I _S1 ) to a smaller second current value (I _A ) when the current flowing through the switching element (I _DRAIN ) _exceeds the current limit value (I _TH ). 8. The device according to claim 6 or 7, characterized in
that the voltage _sensor ( 10 ) is connected on the output side to a second comparator unit ( 11 ) which _detects the voltage (U _DRAIN , U _SOURCE ) at the output of the switching element (T1, T2) with at least one predetermined first voltage limit value (U _TH1 , U _TH2 ) compares
wherein the control signal (I _GATE ) changes from the second current value (I _A , I _B ) to a third current value (I _B , I _A ) when the voltage present at the output of the switching element (T1, T2) exceeds the first voltage limit value (U _TH1 ) exceeds when switching on or falls below when switching off. 9. The device according to claim 8, characterized in that the second current value (I _A ) is smaller in amount than the third current value (I _B ). 10. The device according to claim 8 or 9, characterized in that
that the second comparator unit ( 11 ) compares the voltage at the output of the switching element (T1, T2) with a predetermined second voltage _{limit value} (U _TH2 ),
the control signal changes during a switch-on process from the third current value (I _B ) to a fourth current value (I _CP1 ) when the measured voltage at the output of the switching element (T1, T2) exceeds the second voltage limit value (U _TH2 ) , 11. The device according to one of claims 8 to 10, characterized in that the control signal (I _GATE ) changes during a switch-off process from the first current value (I _S2 ) to the third current value (I _B ) when the measured voltage at the output of Schaltele elements (T1, T2) falls below the second voltage limit (U _TH2 ). 12. Method for driving a controllable switching element (T1, T2), with the following steps:

• - Control of the switching element (T1, T2) with a pregiven control signal (I _GATE ) to change the switching state of the switching element (T1, T2),
• - Detection of a first measurement signal (I _DRAIN , U _SOURCE ) during the switching process, the first measurement signal representing the current flowing through the switching element or the voltage at the output of the switching element (T1, T2),
• Change of the control signal during the switching process as a function of the first measurement signal,

characterized in that the control signal (I _GATE ) assumes at least three different values (I _S1 , I _A , I _B , I _CP1 ) in succession as a function of the first measurement signal during a switching operation. 13. The method according to claim 12, characterized in that
that in addition to the first measurement signal (I _DRAIN ), a second measurement signal (U _SOURCE ) is recorded during the switching process,
wherein the first measurement signal represents the current flowing through the switching element and the second measurement signal represents the voltage at the output of the switching element (T1, T2). 14. The method according to claim 13, characterized in that the first measurement signal is compared with a predetermined current limit value (I _TH ) during the switching process, the control signal (I _GATE ) being changed when the current limit value is _{fallen short of} or exceeded. 15. The method according to claim 13 or 14, characterized in that the second measurement signal (U _SOURCE ) is _compared during the switching process with at least one predetermined voltage limit value (U _TH1 , U _TH2 ), the control signal (I _GATE ) at the Un ter - or exceeding the voltage limit is changed. 16. The method according to at least one of the preceding claims 12 to 15, characterized in that at the beginning of a switching on and / or off depending on the desired switching speed, a first value (I _S1 , I _S2 ) for the control signal (I _GATE ) is given. 17. The method according to claim 16, characterized in that
that the control signal (I _GATE ) is changed from the first value (I _S1 ) to a second value (I _A ) when the first measurement signal (I _DRAIN ) _exceeds the predetermined current limit value (I _TH ),
wherein the second value (I _A ) of the control signal (I _GATE ) is predetermined as a function of the maximum permissible rate of change of the current flowing through the switching element. 18. The method according to claim 17, characterized in that
that the control signal (I _GATE ) is changed from the second value (I _A ) to a third value (I _B ) when the second measurement signal (U _SOURCE ) _exceeds the predetermined first voltage limit value (U _TH1 ),
wherein the third value (I _B ) of the control signal (I _GATE ) is predetermined as a function of the maximum permissible rate of change of the voltage (U _SOURCE ) present at the output of the switching element (T1, T2). 19. The method according to claim 18, characterized in
that the control signal (I _GATE ) is changed from the third value (I _B ) to a fourth value (I _CP1 ) when the second measurement signal (U _SOURCE ) _exceeds the predetermined second voltage limit value (U _TH2 ),
wherein the fourth value (I _CP1 ) of the control signal is predetermined as a function of the desired _{volume resistance of} the switching element (T1, T2). 20. The method according to at least one of the preceding claims 18 to 19, characterized in that
that the control signal (I _GATE ) is changed from the first value (I _S2 ) to the third value (I _B ) when the second measuring signal (U _SOURCE ) _{falls below} the predetermined second voltage limit value (U _TH2 ),
the third value (I _B ) of the control signal being predetermined as a function of the maximum permissible rate of change of the voltage present at the output of the switching element (T1, T2). 21. The method according to claim 20, characterized in
that the control signal (I _GATE ) is changed from the third value (I _B ) to the second value (I _A ) when the second measuring signal (U _SOURCE ) _{falls below} the predetermined first voltage limit value (U _TH1 ),
wherein the second value (I _A ) of the control signal (I _GATE ) is predetermined as a function of the maximum permissible rate of change of the current flowing through the switching element (I _DRAIN ). 22. The method according to claim 21, characterized in
that the control signal (I _GATE ) is changed from the second value (I _A ) to a fifth value (I _CP2 ) when the first measuring signal (I _DRAIN ) _{falls below} the predetermined current limit value (I _TH ),
wherein the fifth value (I _CP2 ) of the control signal (I _GATE ) is specified as a function of the desired blocking resistance of the switching element (T1, T2).