DE10038880C2 - Phase detector for a phase locked loop - Google Patents

Abstract

In a phase detector for a phase locked loop for comparing the phases of a first digital input signal and at least one second digital input signal, the phase detector generates an output signal which represents the phase relationship of the second digital input signal or input signals to the first digital input signal. The clock frequency of each of the digital input signals is divided before a phase comparison and / or a decision logic is provided which is supplied with the digital input signals which may be divided in the clock frequency and which controls the generation of the output signal as a function of the position of the input signals in relation to a first signal.

Description

The invention relates to a phase detector for a phase control loop for comparing the phases of a first digital Input signals and at least one second digital on output signals and a corresponding method for phase ver equal.

Phase locked loops are for integrated high speed circuits, in particular for use in mobile radio base stations tion, indispensable. The task of the phase detectors is the Si Ensuring in-phase processing or sampling of data signals of individual blocks in an integrated Circuit.

In general, such phase locked loops contain a Pha slider, a phase detector and an actuator. phases Detectors for high-frequency, periodic signals are becoming hay te usually from mixers or XOR gates with secondary switched low pass filtering built.

However, these phase detectors have the disadvantage that they Deliver output signals that are usually ambiguous. If one shifts two input signals at the detector by a full one Period (360 °) against each other, so you get - apart from for Phase positions with minimum or maximum output signal - for two different phases have the same output signal. It can not distinguish whether a phase position w or 360-w is available.  

However, an output signal is often required based on of which one can clearly see the phase position of input signals can determine each other. In particular, it is elec tronic circuits important, the exact phase position of a Input signal in relation to a "fixed" clock signal or Knowing input signal (reference signal). For this are Pha Transmit detectors required that have a phase range of 360 ° sweep.

A "lock detect circuit" is known from document US Pat. No. 5,394,444. known, the with the help of two "counter" arranged there determines whether a "reference frequency" refers to a "feedback frequency "is engaged. At the end of a first period and at the end of a second period of time there are output signals the "counter" compared as results. voices the results of the "counter" are both at the end of the first Period as well as at the end of the second period, are the "reference frequency" and the "feedback frequency" snapped onto each other.

Document US 4,940,952 describes a phase and frequency detector which has both a "phase comparator" for phase comparison of two input signals f _V and f _R , and a "phase frequency comparator" for comparing the frequency of the two input signals. Results of these two comparators are processed in parallel with one another and finally combined to form an output signal V ₀ , which represents deviations in the frequency and in the phase of the two input signals f _V and f _R.

In "Monolithic Phase-Locked Loops and Clock Recovery Ciruits - Theory and Design ", B. Razavi, IEEE Press, 1996" is on the Pages 24 to 25 describe a 360 ° phase detector that consists of  there are two D flip-flops and an AND gate. With this However, phase detector can be switched on due to the Input signals ent ambiguity of the output signal ent stand. If you want the phase position of a first input signal with respect to a second input signal must be there forth immediately after switching on the phase detector edge of the second input signal to be triggered on each First contact the D flip-flops. It tips over switching on the phase detector is the first input signal-assigned D flip-flop first, you get an off output signal, which has a phase shift of 360 ° -w and does not correspond to w.

The invention is therefore based on the object of a phase To create a detector for a phase locked loop, with which the Phase relationship of the digital input signals independent of each other gig of the on state and / or initial state of the phases detector can be determined, with an output signal that represents the phase position of the digital input signals, should be clear.

This task is accomplished by a phase detector with the characteristics len of claim 1 and by a method with the  Features of claim 12 solved. Preferred Ausge Events of the phase detector and the method are counter stood the dependent claims.

The invention relates to a phase detector for a phase control loop for comparing the phases of a first digital Input signals and at least one second digital on gang signal. The phase detector generates an output signal that the phase position of the second digital input signal or of the second digital input signals to the first digital Represents input signal. According to the clock frequency sequence of each of the digital input signals before a phase divided comparison and / or there is a decision logic seen who the possibly divided in the clock frequency digital input signals are supplied and which depend on ability of the position of the input signals to a first signal controls the generation of the output signal.

Such a phase detector is advantageously in the white constructed substantially symmetrically for each clock branch, d. H. the signal branches for each input signal are essentially chen identical or symmetrical. "Parasitic" Pha transmission rotations due to different signal propagation times in different signal branches, i.e. the input signals thereby largely avoided, whereby the phase detector a has high accuracy. Especially with input signals Such phases work with clock frequencies in the GHz range turns are particularly disruptive, since the switching times are single ner gate or flip-flops in the range of the period of the input signals can arrive. The invention Phase detector is therefore particularly suitable for processing in this way suitable input signals.  

Preferably, the clock frequency of each of the digital on output signals halved before a phase comparison. hereby are the input signals in their phase by a maximum of 180 ° postponed.

For each of the digital input signals, the Clock frequency in a preferred embodiment Frequency divider provided that the ge in the clock frequency shared signal on the negative edge of the digital one outputs signal. This is necessary because of the on inputs of the frequency divider after a reset Transition or change of state of the input signals in time cannot occur in a defined manner. Preferably, the Fre sequence divider designed as toggle flip-flops. Such digita len components are in different circuit technologies such as ECL or PECL, easy to implement.

Furthermore, is preferably for each digital input signal Weil provided a transmission gate, which he most signal is lockable and the respective input signal is fed before the division. The transmission gat ter serve in particular the inputs of downstream ten digital components when resetting the scarf device or the phase detector.

To compare the phases of the digital input signals points the phase detector has logic for phase comparison which preferably comprises an XOR gate. An XOR gate is generated with relatively little effort a signal that set of the signals logically linked by the XOR gate represents. In addition, an XOR gate is in various scarves technology can be implemented easily and inexpensively.  

In order to clearly detect the phase relationship of the digital The decision produces receiving input signals to each other derlogik a control signal that the processing of a by controls the phase comparison generated second signal. For this purpose, the second signal is preferably via a switch ter an inverter can be fed, the switch from the Control signal is controlled. So the control signal the further processing of the output signal of the phase ver set the same.

In a preferred embodiment, the decision maker comprises logic for each digital input signal a D flip-flop, where with the output signals of the D flip-flop at least one D Latch for generating the control signal are supplied. each digital input signal is a clock input of the the D input flip-flop assigned to the digital input signal and that first signal to the data input of each D flip-flop. The positive output of the first digital input signal assigned D flip-flops and the negative (s) off gear or outputs of the or the second input D-flip-flops assigned to the output signal (s) are or D-Latch (es) fed.

The invention further relates to a method for comparison the phases of a first digital input signal and min least a second digital input signal. Here will generates an output signal that the phase position of the or second digital input signal or input signals for represents the first digital input signal. The clock frequency each of the digital input signals is before a phase ver equally divided and / or those in the tact fre frequency divided digital input signals are an Ent logic supplied, depending on the location of the  Input signals to a first signal generating the off controls the control signal.

Preferably, the phase detector according to the invention is in egg nem phase locked loop of an integrated high-speed circuit, in particular in a mobile radio device set or used.

A particular advantage of the phase detector according to the invention can be seen in the fact that no corresponding circuit lei has feedback, especially at high frequency or high-speed circuits to an offset in the Output signal of the phase detector can lead. Such one Offset must then be elaborate from the output signal through differences filtered out with a complementary signal be what is not in the phase detector according to the invention more is needed.

Overall, according to the invention, a substantially symme trical phase detector are built, in which every two clarity of the output signaling a phase shift signals can be almost excluded. In particular is the phase detection regardless of the start or switch on stood the detector.

The phase detector according to the invention is particularly suitable as a version in an integrated circuit, the preferred way to process signals with clock frequencies in upper MHz or GHz range is used. Currently at such frequency ranges is accurate phase detection important. Such an integrated scarf is preferred bipolar ECL or PECL technology.

Further advantages and possible uses of the invention result from the following description of an embodiment Example of the phase detector in connection with the Drawings. In the drawings shows

Fig. 1 shows an embodiment of a phase detector according to the invention for a first and a second input signal;

Fig. 2 is a timing diagram of the signals of the phase detector shown in Figure 1, wherein after resetting the phase detector, the negative edge of the second input signal appears before the negative edge of the first input signal and the phase offset Dw of both input signals is 90 °.

Fig. 3 is a timing diagram of the signals of the phase detector shown in Fig. 1, wherein after resetting the phase detector, the negative edge of the first input signal appears before the negative edge of the second input signal and the phase shift Dw of both input signals is 270 °.

The following is a positive and a negative Edge of a digital signal the change of state of the Si gnals from logical zero to one or logical one to zero Roger that.

In Fig. 1, a first (digital) input signal 10 (also referred to as a reference signal) is fed to a first transmission gate 19 . The first transmission gate 19 is switched transparently via a first signal 14 (also referred to as a reset or reset signal). For this purpose, the first signal 14 is low-active, ie the transmission gate 19 is switched transparently when the first signal 14 is logically one.

A second (digital) input signal 11 , the phase position of which is to be determined in relation to the first input signal 10 , is fed to a second transmission gate 20 . The second transmission gate 20 is also switched transparently via the ste signal 14 .

The output signal 10 'of the first transmission gate 19 is fed to a first toggle flip-flop 15 as a first frequency divider. Likewise, the output signal 11 'of the second transmission gate 20 is fed to a second toggle flip-flop 16 as a frequency divider. The first and second toggle flip-flops 15 and 16 can be reset via the first signal 14 .

The first and second toggle flip-flops 15 and 16 each divide the signals 10 'and 11 ' at their inputs by a factor of two (frequency halving) and switch the divided signals to their output with the negative edge. The output state of the frequency dividers must always be changed with the negative edge of the input signals, since a transition from logical zero to logical one (or the corresponding level) at the divider inputs after a reset process is undefined in time during the entire logical input Condition can occur.

Halving the clock frequency of the two input signals 10 and 11 causes the two output signals of the two frequency dividers 15 and 16 (ge divided signals 17 and 18 ) to have a phase shift of at most 180 °. Thus, an ambiguity cannot occur in a subsequent phase comparison, as is often the case with the circuits known from the prior art.

The two divided signals 17 and 18 are supplied to an XOR gate 21 as logic for phase comparison. In parallel who the two divided signals 17 and 18 a decision logic 13 supplied.

The decision logic 13 has a first D flip-flop 26 and a second D flip-flop 27 . The first D flip-flop 26 is supplied with the divided signal 17 as a clock signal. More specifically, the divided signal 17 is supplied to the clock input of the D flip-flop 26 . Likewise, the divided signal 18 is fed to the clock input of the second D flip-flop 27 . The first signal 14 is present at the data inputs of the two D flip-flops 26 and 27 . In the operating state, the first signal 14 is logic one, ie logic one is always present at the data input of the two D flip-flops 26 and 27 of the decision logic 13 . A change in the output signals of the two D flip-flops 26 and 27 over time therefore only occurs on the first edge or change over time in the divided signals 17 and 18 supplied to the clock inputs.

The positive output signal 29 of the first D flip-flop 26 and the negative output signal 30 of the second D flip-flop 27 are fed to a D-latch 28 . Here, the negative output signal 30 is supplied to the clock input and the positive output signal 29 to the data input of the D latch 28 . At the output of the D-latch 28 there is a control signal 22 which is used to control the processing of a signal 23 , the output signal of the XOR gate 21 .

The second signal 23 is fed to a changeover switch 24 , which is controlled by the control signal 22 of the decision logic 13 . The switch 24 switches the second signal 23 either through an inverter 25 or directly to a low-pass filter 31st If the control signal 22 is logic zero, the switch 24 is switched in such a way that the second signal 23 of the XOR gate 21 is inverted via the inverter 25 and the low-pass filter 31 is supplied. On the other hand, if the control signal 22 is logic one, no inversion of the second signal 23 is required and this is thus fed directly to the low-pass filter 31 .

The low-pass filter 31 filters the supplied digital signal and generates a DC voltage as an output signal 12 which is linear to the phase difference of the two input signals 10 and 11 .

The mode of operation of the phase detector according to the invention is explained in more detail below on the basis of the timing diagrams shown in FIGS. 2 and 3.

The timing diagram shown in Fig. 2 illustrates the waveforms after a reset of the phase detector, wherein the negative edge of the second input signal 11 appears before the negative edge of the first input signal 10 with respect to the positive edge of the first signal 14 and the phase offset Dw of both Total input signals is about 90 °.

With the positive edge of the first signal 14 , the transmission gates 19 and 20 are switched transparently, so that the digital input signals 10 and 11 are present as signals 10 'and 11 ' at the outputs of the transmission gates 19 and 20 , respectively.

The signals 10 'and 11 ' are halved and inverted in their clock frequency by the toggle flip-flops 15 and 16 , ie, switched through with the negative edge at the input of the respective frequency divider as divided signals 17 and 18 .

The divided signals 17 and 18 are logically linked on the one hand by the XOR gate 21 , which results in the second signal 23 , and on the other hand fed to the two D flip-flops 26 and 27 of the decision logic 13 . At the outputs of the D flip-flops 26 and 27 , the positive output signal 29 and negative output signal 30 are fed to the D latch 28 , which generates the control signal 22 from the supplied signals. In the present case, the control signal 22 is logic zero, since in the logic one phase of the output signal 30 the signal 29 is logic zero and is stored in the D-latch 28 until a new one phase of the output signal 30 appears.

In other words, the decision logic 13 determines whether the negative edge of the second input signal 11 occurs before (control signal 22 is then logic zero) or after (control signal 22 is then logic one) the negative edge of the first input signal 10 to Divide clock 15 or 16 is present.

FIG. 3 also shows a timing diagram of the signals of the phase detector shown in FIG. 1. However, after the phase detector has been reset, the negative edge of the first input signal appears before the negative edge of the second input signal; in addition, the phase offset Dw of both input signals is 270 °. This leads to the fact that the control signal 22 with the first negative edge of the first digital input signal 10 after a reset process (positive edge of the first signal 14 ) becomes logic one and thus the output signal 23 of the XOR gate 21 via the switch 24 to the inverter 25 is supplied and inverted by this. Without inversion, the output signal 12 of the low-pass filter 31 would signal a phase shift Dw of the two input signals 10 and 11 of 360 ° -w, which, however, would not correspond to the actual phase shift.

It should also be mentioned that the phase detector is special well suited as an implementation in an integrated circuit, especially in bipolar ECL or PECL circuit technology. Especially with clock frequencies in the upper MHz or GHz range is the phase detection of the phase detector according to the invention advantageous because of the symmetrical structure of both branches or due to the lack of feedback loops no para stationary phase rotations can arise. Parasitic phases Rotations are particularly disruptive for circuits in the upper MHz or GHz range, since depending on the circuit techno logic the period of the input signals already ver is comparable to the signal transit times by the individual Gates, flip-flops or digital components.

inaccuracies of the circuit are particularly evident in faulty output signals of conventional phase detectors and, depending on the circuit technology used, the period of the input signals can already be comparable to the signal propagation times through the individual gates, flip-flops or digital components. In an embodiment in ECL or PECL technology, the XOR gate 21 , the changeover switch 24 and the inverter 25 in particular can advantageously be implemented as a single circuit block with few transistors.

Claims (15)

1. phase detector for a phase locked loop for comparing the phases of a first digital input signal ( 10 ) and at least one second digital input signal ( 11 ) with clock frequency,
in which each of the digital input signals ( 10 , 11 ) is fed to a frequency divider ( 15 , 16 ), with the aid of which the clock frequency of the respective digital input signal before a phase comparison depending on the position of the respective input signal ( 10 , 11 ) for a reset Signal ( 14 ) is divided and reaches the output of the respective frequency divider ( 15 , 16 ) as a divided signal ( 17 , 18 ),
The outputs of the frequency dividers ( 15 , 16 ) are connected on the one hand to inputs of a phase comparison stage ( 21 ) for phase comparison and on the other hand to inputs of a decision logic ( 13 ), the decision logic depending on the position of the digital signals ( 17 , 18 ) for the reset signal ( 14 ) controls the generation of an output signal ( 12 ) which represents the phase relationship of the at least second digital input signal ( 11 ) to the first digital input signal ( 10 ). 2. Phase detector according to claim 1, characterized in that the phase detector has frequency dividers ( 15 , 16 ) by means of which the clock frequency of each of the digital input signals ( 10 , 11 ) is halved before a phase comparison. 3. Phase detector according to claim 1 or 2, characterized in that a frequency divider ( 15 , 16 ) is provided for each of the digital input signals ( 10 , 11 ) for dividing the clock frequency, which divides the signal ( 17 , 18 ) on the negative edge of the digital input signal ( 10 , 11 ). 4. phase detector according to claim 3, characterized in that the frequency dividers are designed as toggle flip-flops ( 15 , 16 ). 5. Phase detector according to one of the preceding claims, characterized in that the respective frequency divider is preceded by a transmission gate ( 19 , 20 ) which can be blocked by means of the reset signal ( 14 ). 6. Phase detector according to one of claims 1 to 5, characterized in that the phase comparison stage ( 21 ) has an XOR gate. 7. Phase detector according to one of the preceding claims, characterized in that a comparison signal ( 23 ) occurring at the output of the phase comparison stage ( 21 ) can be controlled by a control signal ( 22 ) of the decision logic ( 13 ). 8. phase detector according to claim 7, characterized in that the phase comparison stage ( 21 ) a switch ( 24 ), an inverter ( 25 ) and a low pass ( 31 ) are connected in such a way that the comparison signal ( 23 ) via the switch ( 24 ) either to the inverter ( 25 ) and subsequently to the low pass ( 31 ) or directly to the low pass ( 31 ), the changeover switch ( 24 ) being controlled by the control signal ( 22 ) of the decision logic ( 13 ) and the low pass ( 31 ) provides the output signal ( 12 ) of the phase detector. 9. Phase detector according to one of the preceding claims, characterized in that the decision logic ( 13 ) for each divided digital signal ( 17 , 18 ) has a D flip-flop ( 26 , 27 ) and the output signals of the two D flip-flops ( 26 , 27 ) at least one D-latch ( 28 ) for generating the control signal ( 22 ) are supplied. 10. Phase detector according to claim 9, characterized in that each divided digital signal ( 17 , 18 ) a clock input of the D-flip-flop ( 26 , 27 ) assigned to the divided signal ( 17 , 18 ) and the reset signal ( 14 ) the data input of each D flip-flop ( 26 , 27 ) is supplied. 11. Phase detector according to claim 9 or 10, characterized in that the positive output ( 29 ) of the D-flip-flop ( 26 ) assigned to the first divided signal ( 17 ) and the or the negative (n) output ( 30 ) or Outputs ( 30 ) of the D flip-flop ( 27 ) associated with the second divided signal (s) ( 18 ) are fed to the D latch (es) ( 28 ). 12. A method for comparing the phases of a first digital input signal ( 10 ) and at least one second digital input signal ( 11 ), wherein an output signal ( 12 ) is generated which is the phase position of the second digital input signal or input signals ( 11 ) represents the first digital input signal ( 10 ), the clock frequency of each of the digital input signals before a phase comparison depending on the position of the input signals ( 10 , 11 ) is divided into a reset signal ( 14 ) and the divided signals ( 17 , 18 ) of a decision logic ( 13 ) are supplied and the decision logic ( 13 ) controls the generation of the output signal ( 12 ) depending on the position of the divided signals ( 17 , 18 ) relative to the reset signal ( 14 ). 13. Use of the phase detector according to one of claims 1 to 11 or the method of claim 12 in a pha control loop of an integrated High speed switching, especially in one Mobile device. 14. Integrated circuit with a phase detector after a of claims 1 to 13 for processing signals with Clock frequencies in the upper MHz or GHz range. 15. Integrated circuit according to claim 14, characterized ge indicates that these are in bipolar ECL or PECL Technology is executed.