WO2013156060A1

WO2013156060A1 - Linear 360° range phase detector

Info

Publication number: WO2013156060A1
Application number: PCT/EP2012/057015
Authority: WO
Inventors: Peter VAN DER CAMMEN; Adrianus Van Bezooijen
Original assignee: Epcos Ag
Priority date: 2012-04-17
Filing date: 2012-04-17
Publication date: 2013-10-24

Abstract

A phase detector providing linear phase information from -180° to +180° is disclosed. The phase detector comprises frequency divider and phase shifter and a mixer circuit, frequency divider and phase shifter has an output port connected to an input port of the mixer circuit.

Description

Linear 360° Range Phase Detector The present invention refers to phase detectors that can cover 360° and provide a linear phase signal.

Phase detectors convert phase differences between two input signals into an output signal where the value of an output voltage or an output current is an analog measure for the phase difference. Digital phase detectors may comprise simple gates like EXOR gates or NAND gates, or flip-flops such as SR-flip-flops or D-flip-flops . Conventional phase detectors work well at phase differences around 90°. Multiplicative phase detectors, for example, have input ports that can be swapped without affecting the output value. Thus, such detectors do not give information about the sign of the phase difference and work theoretically from 0° to 180°. However, non-linearity occurs around 0° and around 180°. Thus, the actual range in which a precise phase

information can be obtained is limited.

Sequential phase detectors comprise a memory function and can, thus, detect the sign of the phase difference. Then, the theoretical detection range would comprise the interval from -180° to + 180°. However, the non-linearity problem around 0° and 180° remains. Phase and frequency detectors often used in phase lock loop (PLL) systems also have problems in providing precise phase information around 0°. Thus, it is an object of the present invention to provide a phase detector that gives precise phase information even at phase differences around 0° and that has a detection range of 360° .

For that, the present invention provides a phase detector according to claim 1. Dependent claims provide preferred and advantageous embodiments of the phase detector. A phase detector is provided that comprises a frequency divider and phase shifter. The frequency divider and phase shifter is a circuit that may comprise sub-circuits which perform frequency division and/or sub-circuits which perform a phase shift. The phase detector further comprises a mixer circuit. The frequency divider and phase shifter is provided for receiving a first and a second input signal. The

frequency divider and phase shifter has an output port that is connected to an input port of the mixer circuit. The frequency divider and phase shifter can provide two output signals. Both output signals of the frequency divider and phase shifter may have the same frequency that is the frequency of the input signal divided by a constant factor, e.g. factor of 2. The frequency divider and phase shifter may provide an output signal where at least one of the first input signal and the second input signal is phase shifted by a certain value, e.g. 90°. Further, the first and the second output signal of the frequency divider and phase shifter may be phase shifted with respect to each other, e.g. by 90°. Thus, the frequency divider and phase shifter may provide an in-phase signal and a quadrature signal, each with half of the frequency of the input signal. The two output signals of the frequency divider and phase shifter may be transmitted to the mixer circuit. The mixer circuit can mix, i.e. multiply, these signals and provide an output signal that is related to the phase difference of the first and the second input signals.

It is possible that the frequency divider and phase shifter provides four output signals to the mixer circuit. All four output signals are divided by the same factor compared to the input signals. The frequency divider and phase shifter may provide an in-phase signal relative to the frequency divided input signals. Further, in addition to each in-phase output signal, the frequency divider and phase shifter may provide a respective quadrature signal that is shifted by 90°.

In one embodiment, the phase detector is a divide-by-two frequency divider and phase shifter and provides two output signals having a phase shift of 90° relative to each other. Thus, for at least one input signal, a frequency divided in- phase signal and a frequency divided quadrature signal are provided. Further, a frequency divided in-phase and/or quadrature signal of the respective other input signal may be provided, too. Then, at least three signals are transmitted to the mixer circuit: two in-phase signals and at least one quadrature signal or two quadrature signals and at least one in-phase signal . In one embodiment, the phase detector further comprises a range selector. Then, the mixer circuit has an output port connected to an input port of the range selector. The mixer circuit provides one or more phase signals to the range selector. Depending on the circuit elements of the frequency divider and phase shifter and of the mixer circuit, the precision of the phase difference signal may depend on the phase difference. The range selector may be utilized to improve the precision by determining the phase difference range and selecting a appropriate signals for further

processing. Then, further manipulations of the phase

difference signal in order to improve the precision can be performed.

In one embodiment, the frequency divider and phase shifter divides the frequency of its input signals by two and

provides a 90° phase shifted signal of at least one of the two frequency divided signals.

Thus, the range selector can choose which of these at least three signals are mixed and utilized to determine the phase difference signal.

In one embodiment, the frequency divider and phase shifter comprises two two-latch master-slave D-flip-flops . A first two-latch master-slave D-flip-flop may provide a frequency divided in-phase signal related to the first input signal and a frequency divided quadrature signal related to the first input signal. A second two-latch master-slave D-flip-flop may provide a frequency divided in-phase signal related to the second input signal and a frequency divided quadrature signal related to the second input signal.

In one embodiment, the frequency divider and phase shifter comprises an all-pass filter for providing a phase shift of at least one signal. In one embodiment, the phase detector is provided for working with balanced signals. Balanced signals are less susceptible to unwanted common mode signal disturbances. In one embodiment, the mixer circuit comprises one or two double balanced mixers.

In one embodiment, the mixer circuit comprises four double balanced mixers.

It is possible that an in-phase frequency divided signal related to the first signal and an in-phase frequency divided signal related to the second input signal are mixed via a first mixer. A quadrature frequency divided signal related to the first input signal and a quadrature frequency divided signal related to the second input signal may be mixed via a second mixer. An in-phase frequency divided signal related to the first input signal and a quadrature frequency divided signal related to the second input signal may be mixed via a third mixer. A quadrature frequency divided signal related to the first input signal and an in-phase frequency divided signal related to the second input signal may be mixed via a fourth mixer. The output signals of the first mixer and of the second mixer may be added and provided by the mixer circuit as an in-phase detector signal DETI. The output signals of the third mixer and of the fourth mixer may be added and provided as a quadrature detector signal DETQ of the mixer circuit. In one embodiment, the mixer circuit comprises a quadrature detector having resistance elements connected to its output port. The resistors provide a differential mode voltage and a common mode voltage. Then, phase information can be provided by the ratio between the differential mode voltage and the common mode voltage drop across the output resistors of the mixer circuit.

The differential-mode output voltage DETI and DETQ are proportionally to the output resistor R and the respective bias current. The common-mode voltage drop over R is also proportional to R and the current. Hence, the ratio becomes independent of R and the current, and thus independent of variations in R and It. Accordingly the detector's accuracy is improved.

In one embodiment, the phase information is, thus, derived from the ratio: differential mode voltage divided by common mode voltage.

In one embodiment, the common mode voltage is measured dynamically. Measured dynamically means that the common-mode voltage is measured at the outputs of the mixers that may actually provide the phase detection. This in contrast to using a dummy mixer circuit, without RF signals present, to measure an equivalent of the DC common-mode voltage. An advantage of measuring the DC common-mode voltage, while RF signals are present, is that any change in the DC operating point of the mixer due to RF is taken into account. This further improves the accuracy of detection.

In one embodiment, the mixer circuit comprises a quadrature detector providing an in-phase component and/or a quadrature component .

In one embodiment, the mixer circuit comprises a quadrature detector providing an in-phase component and a quadrature component. The range selector derives the phase difference of half of the 360° phase range from the in-phase component and of the other half of the phase range from the quadrature component .

Thus, by virtue of the range selector, the respective signals derived from the frequency divider and phase shifter and/or the mixer circuit can be chosen in such a way that for the respective phase range segment information for determining a linear phase difference signal is possible. Thus, linearity within the full 360° circle is obtained.

In one embodiment, the range selector evaluates the signs of the in-phase component and the quadrature component. However, it is also possible that the range selector evaluates whether the in-phase components and the quadrature components are bigger or equal than +1 or smaller or equal than -1.

Depending on the result of these evaluations, the range selector instructs the mixer circuit to regard the optimal signals obtained from the frequency divider and phase

shifter .

In one embodiment, thus, the range selector reconstructs the detected phase difference from the in-phase component and from the quadrature component and the phase difference ranges from -180° to +180° .

In one embodiment, the range selector comprises an A/D

(analog-to-digital) converter. The phase difference is converted into an n-bit digital word. The two most

significant bits of the word determine the 90° quadrant of the phase difference as shown in Fig. 6. In one embodiment, the range selector comprises two n-bit up- down counters, six switches, and a switch controller for controlling the switches depending on the value of the up- down counters .

Examples of phase detectors and respective comprised circuits are schematically shown in the figures.

Short description of the schematic drawings: shows the basic principle of the present phase detector comprising a frequency divider and ph shifter FDPS and a mixer circuit MC, shows a phase detector comprising a frequency divider and phase shifter FDPS, a mixer circuit MC and a range selector RS, shows a phase detector with four signal lines between the frequency divider and phase shifter FDPS and the mixer circuit MC, shows how frequency divided in-phase and quadrature signals are related to a respective input signal, shows more detailed versions of the frequency divider and phase shifter FDPS and of the mixer circuit MC, FIG. 6 shows four quadrants of the full 360° circle, shows a more complex embodiment of a mixer circuit MC that is connected to the frequency divider and phase shifter FDPS via four signal lines, shows the working principle of the range selector to obtain linear phase information from -180° to +180° phase difference, shows an embodiment of a phase detector comprising further switches and circuit elements of the range selector, schematically shows the non-linear ranges around 0° and 180° where conventional phase detectors have problems providing precise phase information,

FIG. 11 shows a known double balanced mixer for

conventional phase detectors providing phase information as shown in FIG. 12,

FIG. 12 shows that conventional phase detectors with double balance mixers have problems in providing precise phase information around 0° and 180°. Detailed description

FIG. 1 schematically shows a phase detector PD comprising a frequency divider and phase shifter FDPS and a mixer circuit MC . The frequency divider and phase shifter FDPS receives a first input signal IS1 via a first input port and a second input signal IS2 via a second input port. The frequency divider and phase shifter FDPS provides a frequency divided signal DIV1I that has a frequency of the first input signal divided by a fixed factor, e.g. by a factor of 2. Further, the frequency divider and phase shifter provides a second signal DIV2Q. The frequency of the signal DIV2Q is the frequency of the second input signal IS2 divided by a certain factor, e.g. 2. It may be preferred that the divisions ratios are equal. Further, the signal DIV2Q is phase shifted, e.g. by 90° .

The frequency divided signals DIVII and DIV2Q are transmitted to the mixer circuit MC . The signal DIVII can be an in-phase frequency divided signal and the signal DIV2Q can be a quadrature frequency divided signal, i.e. the phase shift of signal DIV2Q relative to signal DIVII is 90°. The frequency divider and phase shifter can transmit further signals derived by frequency division and/or phase shift from the first and the second input signals IS1, IS2 to the mixer circuit. The mixer circuit MC mixes at least two signals obtained from the frequency divider and phase shifter FDPS and provides an output signal OS that may be an output signal DETQ of the phase detector PD. For that, the mixer circuit MC may comprise at least one mixer that mixes, i.e. multiplies, signals obtained from the frequency divider and phase shifter FDPS . FIG. 2 shows an embodiment of the phase detector further comprising a range selector RS . The mixer circuit MC provides an in-phase detector signal DETI and a quadrature detector signal DETQ which are transmitted to the range selector.

Depending on the values, e.g. the actual voltages or currents of the signals DETI and/or DETQ, at least one of the signals DETI and DETQ are chosen as a source for the output signal OS providing linear phase information from -180° to +180°. FIG. 3 shows an embodiment of the phase detector where the frequency divider and phase shifter FDPS transmits four signals to the mixer circuit MC . All four signals are

frequency divided signals. The frequency divided signals DIV1I and DIV1Q are derived from the first input signal IS1 and the frequency divided signals DIV2I and DIV2Q are derived from the second input signal IS2. Signal DIV1Q is a

quadrature signal relative to the in-phase signal DIV1I, i.e. the phase difference generated by the frequency divider and phase shifter FDPS is 90°. Signal DIV2Q is a quadrature signal with respect to signal DIV2I. Thus, the mixer circuit MC has four sources for generating the in-phase detector signal DETI and the quadrature detector signal DETQ. The in-phase DETI and quadrature DETQ detector signals can be obtained by multiplication and addition according to the following two equations:

DET_I = (DIV1I * DIV2I) + (DIV1Q * DIV2Q)

DET_Q = (DIV1I * DIV2Q) + (DIV1Q * DIV2I)

FIG. 4 shows the relation between an input signal IS which may be the first input signal IS1 or the second input signal IS2 and the related frequency divided signals DIVI and DIVQ. The frequency divided signals have a frequency that is half of the input signal IS. The quadrature signal DIVQ is shifted 90° relative to the in-phase signal DIVI. Thus, signal DIVQ corresponds to a signal that is derived from the input signal IS by a phase shift of 180° and a frequency division by a factor of 2. The two D-flip-flops in a feedback loop can shift the phase und divide the frequency simultaneously.

FIG. 5 shows a more detailed version of the frequency divider and phase shifter FDPS comprising two two-latch master-slave D-flip-flops 2LFF. Each two-latch master-slave D-flip-flop is connected to an input of a mixer M of the mixer circuit MC . The mixer circuit MC provides a quadrature detector signal DETQ at its output.

FIG. 6 shows the four segments I, II, III, IV of a full 360° circle. Known phase detectors may work well at certain phase differences. However, the present invention solves the problem of providing a phase detector that works linear in all four segments, especially in the vicinity of 0° and 180°, i.e. at the border between the first and the fourth segment and between the second and the third segment.

FIG. 7 shows an embodiment of the phase detector where the mixer circuit MC comprises four mixers. Further, the

frequency divider and phase shifter FDPS comprises two two- latch master-slave D-flip-flops and provides frequency divided in-phase signals DIV1I deriving from the first input signal and DIV2I deriving from the second input signal, and two quadrature frequency divided signals DIVIQ deriving from the first input signal and DIV2Q deriving from the second input signal.

The mixer circuit MC further comprises two adding circuits where the first adding circuit provides the in-phase detector signal DETI and the second adding circuit provides the quadrature detector signal DETQ.

FIG. 8 shows the basic working principle of the range

selector. The range selector receives the in-phase detector signal DETI and the quadrature detector signal DETQ.

Alternative detector signals can be obtained by inverting the polarity of the respective signals. It can be seen that the quadrature detector signal DETQ is a good source for obtaining phase information between -90° and +90° including the problematic range around 0° as it has a constant slope in this phase range. However, due to non- linearities around +180° and/or -180°, the signal quality derived from DETQ would be reduced.

The in-phase detector signal DETI has non-linear components at around 0° but is a good measure for the phase difference around -180° and +180°.

In order to provide a precise and linear phase information from -180° to +180°, the range selector chooses either the in-phase detector signal DETI or the quadrature detector signal DETQ as the source for obtaining the phase

information. Thus, in the phase difference range from -180° to -90°, i.e. in quadrant I (compare FIG. 6), the quadrature detector signal DETI may serve as a base for determining precise phase information. In the range from -90° to 0°, i.e. in quadrant II, the quadrature detector signal DETQ is a good base for obtaining phase difference information. In the range from 0° to 90°, the quadrature detector signal DETQ is a good base for obtaining precise phase information, too. In the range from 90° to 180°, the in-phase detector signal DETI is a good base for obtaining phase difference information.

Both the in-phase detector signal DETI and the quadrature detector signal DETQ include a common mode signal and a differential mode signal. The signal may be a voltage drop across resistors of the mixers or a current. Phase

information is obtained by the ratio: differential mode / common mode . Further, by examining the sign of the in-phase detector signal and of the quadrature detector signal DETI, DETQ, in combination with amplitude information, the detector output can be set according to the following table:

A further possibility to provide precise phase information for all four quadrants is by using digital information. A corresponding circuit is shown in FIG. 9: in this embodiment, the phase detector comprises an n-bit up-down counter UDC. The two most significant bits of the up-down counter UDC determine the quadrant of the phase difference according to the following table:

Here, UDC_n-i is the most significant bit and UDC_n-2 is the second most significant bit. The two most significant bits the up-down counter UDC represent the four quadrants I-IV. The range selector RS shown in FIG. 9 comprises two switches SWA and SWB . Depending on the quadrant, the respective switch has to be closed according to the table to determine the source DETI or DETQ to derive phase difference information.

Further, the n-2 least significant bits, fed into the switch control SC, specify the phase in the particular quadrant in steps of 90/ (2^n~2-l) ° . Further switches SWX, SWY, SWZ and SWW are controlled in such a way that in the quadrant the up-down counter is in the proper quadrature detector output is chosen. If a differential quadrature detector is used, the sign of the detector signal DETI or DETQ is inverted. Depending on the measured sign of the respective unused detector signal, the following table:

shows which of the switches SWX to SWW has to be closed.

Then, the relevant detector signal (DETI or DETQ) is passed to a selection node SEL. If the phase difference information is encoded in voltage, then the voltage at node SEL is compared with a reference voltage REF that is multiplied by a factor between 0 and 1 controlled by a loop of the up-down counter. When the loop is settled, the n-2 least significant bits together with the two most significant bits specify the proper phase for quadrants I and III. In quadrants II and IV, the voltage at node SEL decreases with increasing phase. By inverting the n-2 least significant bits of the up-down counter before they are used as input for the digitally controlled attenuator in those quadrants (this is performed by an EXOR gate) , this is corrected. In order to maintain negative feedback, the up-down input of the up-down counter is inverted as well in quadrants II and IV.

If the least n-2 significant bits of the up-down counter are represented with K_Di_G, the loop is settled when

The digital attenuation can also be realized in the current domain and it could also be placed in series with the SEL- input rather than the REF input which can be - in practice - more convenient.

When the loop is not settled and when the up-down counter UDC is even in the wrong quadrant, this implementation will still lead the up-down counter to the proper setting in the

shortest possible way, provided that the up-down counter UDC is of a "wrap-around" type, i.e. counting up from position 2^n~1 to 0, counting down from 0 to 2ⁿ-l.

FIG. 10 shows the output of a conventional phase detector having problems due to decreasing linearity in the vicinity around 0° and 180°.

FIG. 11 shows a double-balanced mixer producing the output shown in FIG. 12.

FIG. 12 shows an output produced by a double-balanced mixer of FIG. 11 also having problems with linearity in the

vicinity around 0° and 180°. The phase detector is not limited to the embodiments

described in the specification or shown in the figures. Phas detectors comprising further elements such as further frequency dividing circuits, phase shifting circuits, mixing circuits and/or range selecting circuits and combinations thereof are also comprised by the present invention.

List of reference signs:

2LFF: two-latch master-slave D-flip-flop

ATTN: attenuator

CLK: clock signal

DETI: in-phase detector signal

DETQ: quadrature detector signal

DIV1I: first in-phase frequency divided signal

DIV1Q: first quadrature frequency divided signal DIV2I: second in-phase frequency divided signal

DIV2Q: second quadrature frequency divided signal

FDPS : frequency divider and phase shifter

I, II, III, IV: quadrants of a full 360° circle

INV: inverter

IS: input signal

IS1, IS2: first, second input signal

M: mixer

MC : mixer circuit

OS: output signal

OUT: output signal

REF: reference signal

RS : range selector

SC: switch control

SEL: selection node/selector node

SWA, SWB: switches

SWX, SWY, SWZ, SWW: switches

UDC : up-down counter

VCM: common mode voltage

VDM: differential mode voltage

XOR: XOR gate

ΔΦϋΕΤ: detected phase difference

ΔΦΙΝ: phase difference to be measured

Claims

Claims :

1. A phase detector, comprising

- a frequency divider and phase shifter (FDPS) and a mixer (MC) circuit, where

- the frequency divider and phase shifter is provided for receiving a first and a second input signal,

- the frequency divider and phase shifter has an output port connected to an input port of the mixer circuit.

2. The phase detector of the previous claim, where the

frequency divider and phase shifter is a divide-by-two frequency divider providing two output signals having a phase shift of 90° relative to each other.

3. The phase detector of one of the previous claims, further comprising

- a range selector, where

- the mixer circuit has an output port connected to an input port of the range selector.

4. The phase detector of the previous claim, where

- the frequency divider and phase shifter divides the frequency of its input signals by two and provides a 90° phase shifted signal of at least one of the two frequency divided signals.

5. The phase detector of one of the previous claims, where the frequency divider and phase shifter comprises two two-latch master-slave D flip-flops.

6. The phase detector of one of the previous claims, where the frequency divider and phase shifter comprises an all- pass filter for providing a phase shift.

7. The phase detector of one of the previous claims,

provided for working with balanced signals.

8. The phase detector of one of the previous claims, where the mixer circuit comprises one or two double balanced mixers.

9. The phase detector of the previous claim, where

the mixer circuit comprises four double balanced mixers.

10. The phase detector of one of the previous claims, where

- the mixer circuit comprises a quadrature detector having resistance elements connected to its output port,

- the resistors provide a differential mode voltage and a common mode voltage.

11. The phase detector of the previous claim, where phase information is derived from the ratio: differential mode voltage / common mode voltage.

12. The phase detector of one of the two previous claims, where the common mode voltage is measured dynamically.

13. The phase detector of one of the previous claims, where - the mixer circuit comprises a quadrature detector providing an in-phase component and/or a quadrature component .

14. The phase detector of the previous claim, where

- the mixer circuit comprises a quadrature detector providing an in-phase component and a quadrature

component,

- the range selector derives the phase difference of half of the 360° phase range from the in-phase component and of the other half of the phase range from the quadrature component .

15. The phase detector of the previous claim, where the range selector evaluates

- the signs of the in-phase component and the quadrature component or

- whether the in-phase components and the quadrature components are > +1 or < -1.

16. The phase detector of one of the previous 13 claims,

where

- the range selector reconstructs the detected phase difference from the in-phase component and from the quadrature component and

- the phase difference ranges from -180° to +180°.

17. The phase detector of one of the previous claims, where

- the range selector comprises an A/D converter,

- the phase difference is converted into a n-bit digital word,

- the two most significant bits of the word determine the 90° quadrant of the phase difference.

18. The phase detector of the previous claim, where the range selector comprises

- two n-bit up-down counters, - 6 switches, and

- a switch controller for controlling the switches depending on the value of the up-down counters.